Index: llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
+++ llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
@@ -113,7 +113,8 @@
   bool useSaveRestoreLibCalls(const MachineFunction &MF) const {
     // We cannot use fixed locations for the callee saved spill slots if the
     // function uses a varargs save area, or is an interrupt handler.
-    return MF.getSubtarget<RISCVSubtarget>().enableSaveRestore() &&
+    return (MF.getSubtarget<RISCVSubtarget>().enableSaveRestore() ||
+            MF.getFunction().hasMinSize()) &&
            VarArgsSaveSize == 0 && !MF.getFrameInfo().hasTailCall() &&
            !MF.getFunction().hasFnAttribute("interrupt");
   }
Index: llvm/test/CodeGen/RISCV/machine-outliner-throw.ll
===================================================================
--- llvm/test/CodeGen/RISCV/machine-outliner-throw.ll
+++ llvm/test/CodeGen/RISCV/machine-outliner-throw.ll
@@ -6,10 +6,8 @@
 define i32 @func1(i32 %x) #0 {
 ; CHECK-LABEL: func1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    call t0, __riscv_save_1
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; CHECK-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    .cfi_offset ra, -8
 ; CHECK-NEXT:    .cfi_offset s0, -16
 ; CHECK-NEXT:    mulw a0, a0, a0
@@ -34,10 +32,8 @@
 define i32 @func2(i32 %x) #0 {
 ; CHECK-LABEL: func2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    call t0, __riscv_save_1
 ; CHECK-NEXT:    .cfi_def_cfa_offset 16
-; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; CHECK-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; CHECK-NEXT:    .cfi_offset ra, -8
 ; CHECK-NEXT:    .cfi_offset s0, -16
 ; CHECK-NEXT:    mulw a0, a0, a0
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===================================================================
--- llvm/test/CodeGen/RISCV/saverestore.ll
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -40,6 +40,37 @@
   ret void
 }
 
+define void @callee_saved0_z() nounwind #0 {
+; RV32I-LABEL: callee_saved0_z:
+; RV32I:     call t0, __riscv_save_5
+; RV32I:     tail __riscv_restore_5
+;
+; RV64I-LABEL: callee_saved0_z:
+; RV64I:     call t0, __riscv_save_5
+; RV64I:     tail __riscv_restore_5
+;
+; RV32I-SR-LABEL: callee_saved0_z:
+; RV32I-SR:         call t0, __riscv_save_5
+; RV32I-SR:         tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0_z:
+; RV64I-SR:         call t0, __riscv_save_5
+; RV64I-SR:         tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0_z:
+; RV32I-FP-SR:         call t0, __riscv_save_5
+; RV32I-FP-SR:         tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0_z:
+; RV64I-FP-SR:         call t0, __riscv_save_5
+; RV64I-FP-SR:         tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+attributes #0 = { minsize }
+
 define void @callee_saved1() nounwind {
 ; RV32I-LABEL: callee_saved1:
 ; RV32I-NOT:     call t0, __riscv_save
Index: llvm/test/CodeGen/RISCV/shifts.ll
===================================================================
--- llvm/test/CodeGen/RISCV/shifts.ll
+++ llvm/test/CodeGen/RISCV/shifts.ll
@@ -39,12 +39,9 @@
 define i64 @lshr64_minsize(i64 %a, i64 %b) minsize nounwind {
 ; RV32I-LABEL: lshr64_minsize:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    call t0, __riscv_save_0
 ; RV32I-NEXT:    call __lshrdi3@plt
-; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
+; RV32I-NEXT:    tail __riscv_restore_0
 ;
 ; RV64I-LABEL: lshr64_minsize:
 ; RV64I:       # %bb.0:
@@ -83,12 +80,9 @@
 define i64 @ashr64_minsize(i64 %a, i64 %b) minsize nounwind {
 ; RV32I-LABEL: ashr64_minsize:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    call t0, __riscv_save_0
 ; RV32I-NEXT:    call __ashrdi3@plt
-; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
+; RV32I-NEXT:    tail __riscv_restore_0
 ;
 ; RV64I-LABEL: ashr64_minsize:
 ; RV64I:       # %bb.0:
@@ -127,12 +121,9 @@
 define i64 @shl64_minsize(i64 %a, i64 %b) minsize nounwind {
 ; RV32I-LABEL: shl64_minsize:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    addi sp, sp, -16
-; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    call t0, __riscv_save_0
 ; RV32I-NEXT:    call __ashldi3@plt
-; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
-; RV32I-NEXT:    addi sp, sp, 16
-; RV32I-NEXT:    ret
+; RV32I-NEXT:    tail __riscv_restore_0
 ;
 ; RV64I-LABEL: shl64_minsize:
 ; RV64I:       # %bb.0: