diff --git a/llvm/test/Transforms/InstCombine/select_and_icmpeq.ll b/llvm/test/Transforms/InstCombine/select_and_icmpeq.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/select_and_icmpeq.ll
@@ -0,0 +1,103 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define i1 @select_and_icmpeq_i32(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpeq_i32(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i32 2, i32 1
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i32 2, i32 1
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[S1]], [[S2]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp eq i32 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i32 2, i32 1
+  %s2 = select i1 %y, i32 2, i32 1
+  %and = and i32 %s1, %s2
+  %icmp = icmp eq i32 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpeq_i9(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpeq_i9(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i9 3, i9 16
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i9 3, i9 16
+; CHECK-NEXT:    [[AND:%.*]] = and i9 [[S2]], [[S1]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp eq i9 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i9 3, i9 16
+  %s2 = select i1 %y, i9 3, i9 16
+  %and = and i9 %s2, %s1
+  %icmp = icmp eq i9 %and, 0
+  ret i1 %icmp
+}
+
+define <5 x i1> @select_and_icmpeq_i1vec(<5 x i1> %x, <5 x i1> %y) {
+; CHECK-LABEL: @select_and_icmpeq_i1vec(
+; CHECK-NEXT:    [[S1:%.*]] = select <5 x i1> [[X:%.*]], <5 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3>, <5 x i32> <i32 8, i32 24, i32 16, i32 256, i32 192>
+; CHECK-NEXT:    [[S2:%.*]] = select <5 x i1> [[Y:%.*]], <5 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3>, <5 x i32> <i32 8, i32 24, i32 16, i32 256, i32 192>
+; CHECK-NEXT:    [[AND:%.*]] = and <5 x i32> [[S2]], [[S1]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp eq <5 x i32> [[AND]], zeroinitializer
+; CHECK-NEXT:    ret <5 x i1> [[ICMP]]
+;
+  %s1 = select <5 x i1> %x, <5 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3>, <5 x i32> <i32 8, i32 24, i32 16, i32 256, i32 192>
+  %s2 = select <5 x i1> %y, <5 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3>, <5 x i32> <i32 8, i32 24, i32 16, i32 256, i32 192>
+  %and = and <5 x i32> %s2, %s1
+  %icmp = icmp eq <5 x i32> %and, <i32 0, i32 0, i32 0, i32 0, i32 0>
+  ret <5 x i1> %icmp
+}
+
+define i1 @select_and_icmpeq_i8_negative_other_pred(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpeq_i8_negative_other_pred(
+; CHECK-NEXT:    ret i1 false
+;
+  %s1 = select i1 %x, i8 1, i8 8
+  %s2 = select i1 %y, i8 1, i8 8
+  %and = and i8 %s1, %s2
+  %icmp = icmp ult i8 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpeq_i4_negative_select_arm_zero(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpeq_i4_negative_select_arm_zero(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i4 2, i4 1
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i4 2, i4 1
+; CHECK-NEXT:    [[AND:%.*]] = and i4 [[S1]], [[S2]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp eq i4 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i4 2, i4 1
+  %s2 = select i1 %y, i4 2, i4 1
+  %and = and i4 %s1, %s2
+  %icmp = icmp eq i4 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpeq_i12_negative_one_select_pair_matching1(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpeq_i12_negative_one_select_pair_matching1(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i12 0, i12 4
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i12 2, i12 4
+; CHECK-NEXT:    [[AND:%.*]] = and i12 [[S1]], [[S2]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp eq i12 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i12 1, i12 4
+  %s2 = select i1 %y, i12 2, i12 4
+  %and = and i12 %s1, %s2
+  %icmp = icmp eq i12 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpeq_i13_negative_one_select_pair_matching2(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpeq_i13_negative_one_select_pair_matching2(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i13 2, i13 0
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i13 2, i13 4
+; CHECK-NEXT:    [[AND:%.*]] = and i13 [[S1]], [[S2]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp eq i13 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i13 2, i13 8
+  %s2 = select i1 %y, i13 2, i13 4
+  %and = and i13 %s1, %s2
+  %icmp = icmp eq i13 %and, 0
+  ret i1 %icmp
+}
diff --git a/llvm/test/Transforms/InstCombine/select_and_icmpne.ll b/llvm/test/Transforms/InstCombine/select_and_icmpne.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/select_and_icmpne.ll
@@ -0,0 +1,107 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define i1 @select_and_icmpne_i32(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpne_i32(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i32 2, i32 1
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i32 2, i32 1
+; CHECK-NEXT:    [[AND:%.*]] = and i32 [[S1]], [[S2]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp ne i32 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i32 2, i32 1
+  %s2 = select i1 %y, i32 2, i32 1
+  %and = and i32 %s1, %s2
+  %icmp = icmp ne i32 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpne_i9(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpne_i9(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i9 3, i9 16
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i9 3, i9 16
+; CHECK-NEXT:    [[AND:%.*]] = and i9 [[S2]], [[S1]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp ne i9 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i9 3, i9 16
+  %s2 = select i1 %y, i9 3, i9 16
+  %and = and i9 %s2, %s1
+  %icmp = icmp ne i9 %and, 0
+  ret i1 %icmp
+}
+
+define <5 x i1> @select_and_icmpne_i1vec(<5 x i1> %x, <5 x i1> %y) {
+; CHECK-LABEL: @select_and_icmpne_i1vec(
+; CHECK-NEXT:    [[S1:%.*]] = select <5 x i1> [[X:%.*]], <5 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3>, <5 x i32> <i32 8, i32 24, i32 16, i32 256, i32 192>
+; CHECK-NEXT:    [[S2:%.*]] = select <5 x i1> [[Y:%.*]], <5 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3>, <5 x i32> <i32 8, i32 24, i32 16, i32 256, i32 192>
+; CHECK-NEXT:    [[AND:%.*]] = and <5 x i32> [[S2]], [[S1]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp ne <5 x i32> [[AND]], zeroinitializer
+; CHECK-NEXT:    ret <5 x i1> [[ICMP]]
+;
+  %s1 = select <5 x i1> %x, <5 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3>, <5 x i32> <i32 8, i32 24, i32 16, i32 256, i32 192>
+  %s2 = select <5 x i1> %y, <5 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3>, <5 x i32> <i32 8, i32 24, i32 16, i32 256, i32 192>
+  %and = and <5 x i32> %s2, %s1
+  %icmp = icmp ne <5 x i32> %and, <i32 0, i32 0, i32 0, i32 0, i32 0>
+  ret <5 x i1> %icmp
+}
+
+define i1 @select_and_icmpne_i8_negative_other_pred(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpne_i8_negative_other_pred(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i8 1, i8 8
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i8 1, i8 8
+; CHECK-NEXT:    [[AND:%.*]] = and i8 [[S1]], [[S2]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp ne i8 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i8 1, i8 8
+  %s2 = select i1 %y, i8 1, i8 8
+  %and = and i8 %s1, %s2
+  %icmp = icmp ugt i8 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpne_i4_negative_select_arm_zero(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpne_i4_negative_select_arm_zero(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i4 2, i4 1
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i4 2, i4 1
+; CHECK-NEXT:    [[AND:%.*]] = and i4 [[S1]], [[S2]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp ne i4 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i4 2, i4 1
+  %s2 = select i1 %y, i4 2, i4 1
+  %and = and i4 %s1, %s2
+  %icmp = icmp ne i4 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpne_i12_negative_one_select_pair_matching1(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpne_i12_negative_one_select_pair_matching1(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i12 0, i12 4
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i12 2, i12 4
+; CHECK-NEXT:    [[AND:%.*]] = and i12 [[S1]], [[S2]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp ne i12 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i12 1, i12 4
+  %s2 = select i1 %y, i12 2, i12 4
+  %and = and i12 %s1, %s2
+  %icmp = icmp ne i12 %and, 0
+  ret i1 %icmp
+}
+
+define i1 @select_and_icmpne_i13_negative_one_select_pair_matching2(i1 %x, i1 %y) {
+; CHECK-LABEL: @select_and_icmpne_i13_negative_one_select_pair_matching2(
+; CHECK-NEXT:    [[S1:%.*]] = select i1 [[X:%.*]], i13 2, i13 0
+; CHECK-NEXT:    [[S2:%.*]] = select i1 [[Y:%.*]], i13 2, i13 4
+; CHECK-NEXT:    [[AND:%.*]] = and i13 [[S1]], [[S2]]
+; CHECK-NEXT:    [[ICMP:%.*]] = icmp ne i13 [[AND]], 0
+; CHECK-NEXT:    ret i1 [[ICMP]]
+;
+  %s1 = select i1 %x, i13 2, i13 8
+  %s2 = select i1 %y, i13 2, i13 4
+  %and = and i13 %s1, %s2
+  %icmp = icmp ne i13 %and, 0
+  ret i1 %icmp
+}