Index: llvm/test/CodeGen/AArch64/pr57502.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/pr57502.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -o - %s | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+
+define void @trunc(ptr %addr, <4 x i64> %input) {
+; CHECK-LABEL: trunc:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    xtn v1.2s, v1.2d
+; CHECK-NEXT:    xtn v0.2s, v0.2d
+; CHECK-NEXT:    uzp1 v0.4h, v0.4h, v1.4h
+; CHECK-NEXT:    addv h0, v0.4h
+; CHECK-NEXT:    fmov w8, s0
+; CHECK-NEXT:    strb w8, [x0]
+; CHECK-NEXT:    ret
+  %var = trunc <4 x i64> %input to <4 x i8>
+  %res = call i8 @llvm.vector.reduce.add.v4i8(<4 x i8> %var)
+  store i8 %res, ptr %addr
+  ret void
+}
+
+declare i8 @llvm.vector.reduce.add.v4i8(<4 x i8>)