Index: llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td +++ llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td @@ -10,12 +10,13 @@ class MMDSPInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl { let InsnPredicates = [HasDSP]; + let AdditionalPredicates = [InMicroMips]; string BaseOpcode = opstr; string Arch = "mmdsp"; let DecoderNamespace = "MicroMips"; } -class POOL32A_3R_FMT op> : MMDSPInst { +class POOL32A_3R_FMT op> : MMDSPInst { bits<5> rd; bits<5> rs; bits<5> rt; @@ -26,3 +27,16 @@ let Inst{15-11} = rd; let Inst{10-0} = op; } + +class POOL32A_AC2R_FMT funct> : MMDSPInst { + bits<2> ac; + bits<5> rs; + bits<5> rt; + + let Inst{31-26} = 0; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-14} = ac; + let Inst{13-6} = funct; + let Inst{5-0} = 0b111100; +} Index: llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td @@ -12,8 +12,27 @@ //===----------------------------------------------------------------------===// // Instruction encoding. -class ADDU_QB_MM_ENC : POOL32A_3R_FMT<0b00011001101>; +class ADDU_QB_MM_ENC : POOL32A_3R_FMT<"addu.qb", 0b00011001101>; +class DPA_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpa.w.ph", 0b00000010>; +class DPAQ_S_W_PH_MM_ENC : POOL32A_AC2R_FMT<"dpaq_s.w.ph", 0b00001010>; +class DPAQ_SA_L_W_MM_ENC : POOL32A_AC2R_FMT<"dpaq_sa.l.w", 0b01001010>; +class DPAQX_S_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpaqx_s.w.ph", 0b10001010>; +class DPAQX_SA_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpaqx_sa.w.ph", 0b11001010>; +class DPAU_H_QBL_MM_ENC : POOL32A_AC2R_FMT<"dpau.h.qbl", 0b10000010>; +class DPAU_H_QBR_MM_ENC : POOL32A_AC2R_FMT<"dpau.h.qbr", 0b11000010>; +class DPAX_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpax.w.ph", 0b01000010>; // Instruction defs. -// MIPS DSP Rev 1 -def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC, ISA_MICROMIPS; +// microMIPS DSP Rev 1 +def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC; +def DPAQ_S_W_PH_MM : DspMMRel, DPAQ_S_W_PH_MM_ENC, DPAQ_S_W_PH_DESC; +def DPAQ_SA_L_W_MM : DspMMRel, DPAQ_SA_L_W_MM_ENC, DPAQ_SA_L_W_DESC; +def DPAU_H_QBL_MM : DspMMRel, DPAU_H_QBL_MM_ENC, DPAU_H_QBL_DESC; +def DPAU_H_QBR_MM : DspMMRel, DPAU_H_QBR_MM_ENC, DPAU_H_QBR_DESC; +// microMIPS DSP Rev 2 +def DPA_W_PH_MMR2 : DspMMRel, DPA_W_PH_MMR2_ENC, DPA_W_PH_DESC, ISA_DSPR2; +def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC, + ISA_DSPR2; +def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC, + ISA_DSPR2; +def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2; Index: llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td +++ llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td @@ -28,6 +28,10 @@ def HasDSPR3 : Predicate<"Subtarget->hasDSPR3()">, AssemblerPredicate<"FeatureDSPR3">; +class ISA_DSPR2 { + list InsnPredicates = [HasDSPR2]; +} + // Fields. class Field6 val> { bits<6> V = val; Index: llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td +++ llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td @@ -263,6 +263,7 @@ string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); list Pattern = [(set ROD:$rd, (OpNode ROS:$rs, ROT:$rt))]; InstrItinClass Itinerary = itin; + string BaseOpcode = instr_asm; } class RADDU_W_QB_DESC_BASE Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))]; string Constraints = "$acin = $ac"; + string BaseOpcode = instr_asm; } class MULT_DESC_BASE