Index: llvm/lib/Target/M68k/M68kRegisterInfo.td =================================================================== --- llvm/lib/Target/M68k/M68kRegisterInfo.td +++ llvm/lib/Target/M68k/M68kRegisterInfo.td @@ -83,10 +83,15 @@ //===----------------------------------------------------------------------===// class MxRegClass regTypes, int alignment, dag regList> - : RegisterClass<"M68k", regTypes, alignment, regList>; + : RegisterClass<"M68k", regTypes, alignment, regList> { + let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo]>; +} // Data Registers -def DR8 : MxRegClass<[i8], 16, (sequence "BD%u", 0, 7)>; +def DR8 : MxRegClass<[i8], 16, (sequence "BD%u", 0, 7)> { + let RegInfos = RegInfoByHwMode<[DefaultMode], [RegInfo<8, 32, 16>]>; +} + def DR16 : MxRegClass<[i16], 16, (sequence "WD%u", 0, 7)>; def DR32 : MxRegClass<[i32], 32, (sequence "D%u", 0, 7)>; Index: llvm/test/CodeGen/M68k/fast-regalloc.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/M68k/fast-regalloc.ll @@ -0,0 +1,82 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=m68k-linux-gnu --regalloc=fast -o - %s | FileCheck %s + +define dso_local void @foo1() { +; CHECK-LABEL: foo1: +; CHECK: .cfi_startproc +; CHECK-NEXT: ; %bb.0: ; %entry +; CHECK-NEXT: suba.l #4, %sp +; CHECK-NEXT: .cfi_def_cfa_offset -8 +; CHECK-NEXT: move.b #0, %d0 +; CHECK-NEXT: movem.l %d0, (0,%sp) +; CHECK-NEXT: .LBB0_1: ; %do.body +; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: movem.l (0,%sp), %d0 +; CHECK-NEXT: cmpi.b #0, %d0 +; CHECK-NEXT: bne .LBB0_1 +; CHECK-NEXT: ; %bb.2: ; %do.end +; CHECK-NEXT: adda.l #4, %sp +; CHECK-NEXT: rts +entry: + br label %do.body + +do.body: ; preds = %land.end, %entry + %cmp5 = icmp eq i32 0, 4 + br label %land.end + +land.end: ; preds = %do.body + br i1 %cmp5, label %do.body, label %do.end + +do.end: ; preds = %land.end + ret void +} + +define dso_local i32 @foo2(ptr noundef %0) { +; CHECK-LABEL: foo2: +; CHECK: .cfi_startproc +; CHECK-NEXT: ; %bb.0: ; %entry +; CHECK-NEXT: suba.l #8, %sp +; CHECK-NEXT: .cfi_def_cfa_offset -12 +; CHECK-NEXT: move.l (12,%sp), %a0 +; CHECK-NEXT: move.b (%a0), %d0 +; CHECK-NEXT: movem.l %d0, (0,%sp) +; CHECK-NEXT: and.b #1, %d0 +; CHECK-NEXT: movem.l %d0, (4,%sp) +; CHECK-NEXT: sub.b #1, %d0 +; CHECK-NEXT: bgt .LBB1_2 +; CHECK-NEXT: ; %bb.1: ; %if +; CHECK-NEXT: movem.l (4,%sp), %d0 +; CHECK-NEXT: movem.l (0,%sp), %d1 +; CHECK-NEXT: add.b %d1, %d0 +; CHECK-NEXT: bra .LBB1_3 +; CHECK-NEXT: .LBB1_2: ; %else +; CHECK-NEXT: movem.l (0,%sp), %d0-%d1 +; CHECK-NEXT: sub.b %d1, %d0 +; CHECK-NEXT: movem.l %d0, (0,%sp) +; CHECK-NEXT: .LBB1_3: ; %cont +; CHECK-NEXT: movem.l %d0, (4,%sp) +; CHECK-NEXT: movem.l (4,%sp), %d0 +; CHECK-NEXT: ext.w %d0 +; CHECK-NEXT: ext.l %d0 +; CHECK-NEXT: adda.l #8, %sp +; CHECK-NEXT: rts +entry: + %1 = getelementptr i8, ptr %0, i32 0 + %2 = load i8, ptr %1 + %3 = and i8 %2, 1 + %4 = icmp sle i8 %3, 1 + br i1 %4, label %if, label %else + +if: + %5 = add i8 %3, %2 + br label %cont + +else: + %6 = sub i8 %2, %3 + br label %cont + +cont: + %7 = phi i8 [%5, %if], [%6, %else] + %8 = sext i8 %7 to i32 + ret i32 %8 +}