diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -113,7 +113,7 @@
 defm : FPFMADynFrmAlias_m<FNMSUB_D, "fnmsub.d", DINX>;
 defm : FPFMADynFrmAlias_m<FNMADD_D, "fnmadd.d", DINX>;
 
-let SchedRW = [WriteFALU64, ReadFALU64, ReadFALU64] in {
+let SchedRW = [WriteFAdd64, ReadFAdd64, ReadFAdd64] in {
 defm FADD_D : FPALU_rr_frm_m<0b0000001, "fadd.d", DINX, /*Commutable*/1>;
 defm FSUB_D : FPALU_rr_frm_m<0b0000101, "fsub.d", DINX>;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -314,7 +314,7 @@
 defm : FPFMADynFrmAlias_m<FNMSUB_S, "fnmsub.s", FINX>;
 defm : FPFMADynFrmAlias_m<FNMADD_S, "fnmadd.s", FINX>;
 
-let SchedRW = [WriteFALU32, ReadFALU32, ReadFALU32] in {
+let SchedRW = [WriteFAdd32, ReadFAdd32, ReadFAdd32] in {
 defm FADD_S : FPALU_rr_frm_m<0b0000000, "fadd.s", FINX, /*Commutable*/1>;
 defm FSUB_S : FPALU_rr_frm_m<0b0000100, "fsub.s", FINX>;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -108,7 +108,7 @@
 defm : FPFMADynFrmAlias_m<FNMSUB_H, "fnmsub.h", HINX>;
 defm : FPFMADynFrmAlias_m<FNMADD_H, "fnmadd.h", HINX>;
 
-let SchedRW = [WriteFALU16, ReadFALU16, ReadFALU16] in {
+let SchedRW = [WriteFAdd16, ReadFAdd16, ReadFAdd16] in {
 defm FADD_H : FPALU_rr_frm_m<0b0000010, "fadd.h", HINX, /*Commutable*/1>;
 defm FSUB_H : FPALU_rr_frm_m<0b0000110, "fsub.h", HINX>;
 }
diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket.td b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket.td
@@ -111,14 +111,14 @@
 
 // Single precision.
 let Latency = 4 in {
-def : WriteRes<WriteFALU32, [RocketUnitFPALU]>;
+def : WriteRes<WriteFAdd32, [RocketUnitFPALU]>;
 def : WriteRes<WriteFSGNJ32, [RocketUnitFPALU]>;
 def : WriteRes<WriteFMinMax32, [RocketUnitFPALU]>;
 }
 
 // Double precision
 let Latency = 6 in {
-def : WriteRes<WriteFALU64, [RocketUnitFPALU]>;
+def : WriteRes<WriteFAdd64, [RocketUnitFPALU]>;
 def : WriteRes<WriteFSGNJ64, [RocketUnitFPALU]>;
 def : WriteRes<WriteFMinMax64, [RocketUnitFPALU]>;
 }
@@ -203,11 +203,11 @@
 def : ReadAdvance<ReadAtomicSTD, 0>;
 def : ReadAdvance<ReadFStoreData, 0>;
 def : ReadAdvance<ReadFMemBase, 0>;
-def : ReadAdvance<ReadFALU32, 0>;
-def : ReadAdvance<ReadFALU64, 0>;
+def : ReadAdvance<ReadFAdd32, 0>;
+def : ReadAdvance<ReadFAdd64, 0>;
 def : ReadAdvance<ReadFMul32, 0>;
-def : ReadAdvance<ReadFMA32, 0>;
 def : ReadAdvance<ReadFMul64, 0>;
+def : ReadAdvance<ReadFMA32, 0>;
 def : ReadAdvance<ReadFMA64, 0>;
 def : ReadAdvance<ReadFDiv32, 0>;
 def : ReadAdvance<ReadFDiv64, 0>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -104,7 +104,7 @@
 
 // Single precision.
 let Latency = 5 in {
-def : WriteRes<WriteFALU32, [SiFive7PipeB]>;
+def : WriteRes<WriteFAdd32, [SiFive7PipeB]>;
 def : WriteRes<WriteFMul32, [SiFive7PipeB]>;
 def : WriteRes<WriteFMA32, [SiFive7PipeB]>;
 }
@@ -120,7 +120,7 @@
 
 // Double precision
 let Latency = 7 in {
-def : WriteRes<WriteFALU64, [SiFive7PipeB]>;
+def : WriteRes<WriteFAdd64, [SiFive7PipeB]>;
 def : WriteRes<WriteFMul64, [SiFive7PipeB]>;
 def : WriteRes<WriteFMA64, [SiFive7PipeB]>;
 }
@@ -190,11 +190,11 @@
 def : ReadAdvance<ReadAtomicSTD, 0>;
 def : ReadAdvance<ReadFStoreData, 0>;
 def : ReadAdvance<ReadFMemBase, 0>;
-def : ReadAdvance<ReadFALU32, 0>;
-def : ReadAdvance<ReadFALU64, 0>;
+def : ReadAdvance<ReadFAdd32, 0>;
+def : ReadAdvance<ReadFAdd64, 0>;
 def : ReadAdvance<ReadFMul32, 0>;
-def : ReadAdvance<ReadFMA32, 0>;
 def : ReadAdvance<ReadFMul64, 0>;
+def : ReadAdvance<ReadFMA32, 0>;
 def : ReadAdvance<ReadFMA64, 0>;
 def : ReadAdvance<ReadFDiv32, 0>;
 def : ReadAdvance<ReadFDiv64, 0>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedule.td b/llvm/lib/Target/RISCV/RISCVSchedule.td
--- a/llvm/lib/Target/RISCV/RISCVSchedule.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedule.td
@@ -38,14 +38,14 @@
 def WriteAtomicLDD  : SchedWrite;    // Atomic load double word
 def WriteAtomicSTW  : SchedWrite;    // Atomic store word
 def WriteAtomicSTD  : SchedWrite;    // Atomic store double word
-def WriteFALU16     : SchedWrite;    // FP 16-bit computation
-def WriteFALU32     : SchedWrite;    // FP 32-bit computation
-def WriteFALU64     : SchedWrite;    // FP 64-bit computation
+def WriteFAdd16     : SchedWrite;    // 16-bit floating point addition/subtraction
+def WriteFAdd32     : SchedWrite;    // 32-bit floating point addition/subtraction
+def WriteFAdd64     : SchedWrite;    // 64-bit floating point addition/subtraction
 def WriteFMul16     : SchedWrite;    // 16-bit floating point multiply
-def WriteFMA16      : SchedWrite;    // 16-bit floating point fused multiply-add
 def WriteFMul32     : SchedWrite;    // 32-bit floating point multiply
-def WriteFMA32      : SchedWrite;    // 32-bit floating point fused multiply-add
 def WriteFMul64     : SchedWrite;    // 64-bit floating point multiply
+def WriteFMA16      : SchedWrite;    // 16-bit floating point fused multiply-add
+def WriteFMA32      : SchedWrite;    // 32-bit floating point fused multiply-add
 def WriteFMA64      : SchedWrite;    // 64-bit floating point fused multiply-add
 def WriteFDiv16     : SchedWrite;    // 16-bit floating point divide
 def WriteFDiv32     : SchedWrite;    // 32-bit floating point divide
@@ -131,14 +131,14 @@
 def ReadAtomicLDD   : SchedRead;    // Atomic load double word
 def ReadAtomicSTW   : SchedRead;    // Atomic store word
 def ReadAtomicSTD   : SchedRead;    // Atomic store double word
-def ReadFALU16      : SchedRead;    // FP 16-bit computation
-def ReadFALU32      : SchedRead;    // FP 32-bit computation
-def ReadFALU64      : SchedRead;    // FP 64-bit computation
+def ReadFAdd16      : SchedRead;    // 16-bit floating point addition/subtraction
+def ReadFAdd32      : SchedRead;    // 32-bit floating point addition/subtraction
+def ReadFAdd64      : SchedRead;    // 64-bit floating point addition/subtraction
 def ReadFMul16      : SchedRead;    // 16-bit floating point multiply
-def ReadFMA16       : SchedRead;    // 16-bit floating point fused multiply-add
 def ReadFMul32      : SchedRead;    // 32-bit floating point multiply
-def ReadFMA32       : SchedRead;    // 32-bit floating point fused multiply-add
 def ReadFMul64      : SchedRead;    // 64-bit floating point multiply
+def ReadFMA16       : SchedRead;    // 16-bit floating point fused multiply-add
+def ReadFMA32       : SchedRead;    // 32-bit floating point fused multiply-add
 def ReadFMA64       : SchedRead;    // 64-bit floating point fused multiply-add
 def ReadFDiv16      : SchedRead;    // 16-bit floating point divide
 def ReadFDiv32      : SchedRead;    // 32-bit floating point divide
@@ -185,7 +185,7 @@
 
 multiclass UnsupportedSchedZfh {
 let Unsupported = true in {
-def : WriteRes<WriteFALU16, []>;
+def : WriteRes<WriteFAdd16, []>;
 def : WriteRes<WriteFClass16, []>;
 def : WriteRes<WriteFCvtF16ToF64, []>;
 def : WriteRes<WriteFCvtF64ToF16, []>;
@@ -207,7 +207,7 @@
 def : WriteRes<WriteFST16, []>;
 def : WriteRes<WriteFSqrt16, []>;
 
-def : ReadAdvance<ReadFALU16, 0>;
+def : ReadAdvance<ReadFAdd16, 0>;
 def : ReadAdvance<ReadFClass16, 0>;
 def : ReadAdvance<ReadFCvtF16ToF64, 0>;
 def : ReadAdvance<ReadFCvtF64ToF16, 0>;