diff --git a/llvm/lib/Target/PowerPC/PPCCallingConv.td b/llvm/lib/Target/PowerPC/PPCCallingConv.td
--- a/llvm/lib/Target/PowerPC/PPCCallingConv.td
+++ b/llvm/lib/Target/PowerPC/PPCCallingConv.td
@@ -386,3 +386,12 @@
 
 def CSR_64_AllRegs_VSRP :
   CalleeSavedRegs<(add CSR_64_AllRegs_VSX, CSR_ALL_VSRP)>;
+
+def CSR_64_AllRegs_AIX_Dflt_VSRP :
+  CalleeSavedRegs<(add CSR_64_AllRegs_AIX_Dflt_VSX, (sequence "VSRp%u", 0, 25))>;
+
+def CSR_AIX64_VSRP : CalleeSavedRegs<(add CSR_PPC64_Altivec, CSR_VSRP)>;
+
+def CSR_AIX64_R2_VSRP : CalleeSavedRegs<(add CSR_AIX64_VSRP, X2)>;
+
+def CSR_AIX32_VSRP : CalleeSavedRegs<(add CSR_AIX32_Altivec, CSR_VSRP)>;
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -188,8 +188,11 @@
     if (!TM.isPPC64() && Subtarget.isAIXABI())
       report_fatal_error("AnyReg unimplemented on 32-bit AIX.");
     if (Subtarget.hasVSX()) {
-      if (Subtarget.pairedVectorMemops())
+      if (Subtarget.pairedVectorMemops()) {
+        if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
+          return CSR_64_AllRegs_AIX_Dflt_VSRP_SaveList;
         return CSR_64_AllRegs_VSRP_SaveList;
+      }
       if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
         return CSR_64_AllRegs_AIX_Dflt_VSX_SaveList;
       return CSR_64_AllRegs_VSX_SaveList;
@@ -237,8 +240,14 @@
   }
   // Standard calling convention CSRs.
   if (TM.isPPC64()) {
-    if (Subtarget.pairedVectorMemops())
+    if (Subtarget.pairedVectorMemops()) {
+      if (Subtarget.isAIXABI()) {
+        if (!TM.getAIXExtendedAltivecABI())
+          return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
+        return SaveR2 ? CSR_AIX64_R2_VSRP_SaveList : CSR_AIX64_VSRP_SaveList;
+      }
       return SaveR2 ? CSR_SVR464_R2_VSRP_SaveList : CSR_SVR464_VSRP_SaveList;
+    }
     if (Subtarget.hasAltivec() &&
         (!Subtarget.isAIXABI() || TM.getAIXExtendedAltivecABI())) {
       return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
@@ -248,6 +257,9 @@
   }
   // 32-bit targets.
   if (Subtarget.isAIXABI()) {
+    if (Subtarget.pairedVectorMemops())
+      return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_VSRP_SaveList
+                                           : CSR_AIX32_SaveList;
     if (Subtarget.hasAltivec())
       return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList
                                            : CSR_AIX32_SaveList;
@@ -271,8 +283,11 @@
   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
   if (CC == CallingConv::AnyReg) {
     if (Subtarget.hasVSX()) {
-      if (Subtarget.pairedVectorMemops())
+      if (Subtarget.pairedVectorMemops()) {
+        if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
+          return CSR_64_AllRegs_AIX_Dflt_VSRP_RegMask;
         return CSR_64_AllRegs_VSRP_RegMask;
+      }
       if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
         return CSR_64_AllRegs_AIX_Dflt_VSX_RegMask;
       return CSR_64_AllRegs_VSX_RegMask;
@@ -286,6 +301,11 @@
   }
 
   if (Subtarget.isAIXABI()) {
+    if (Subtarget.pairedVectorMemops()) {
+      if (!TM.getAIXExtendedAltivecABI())
+        return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask;
+      return TM.isPPC64() ? CSR_AIX64_VSRP_RegMask : CSR_AIX32_VSRP_RegMask;
+    }
     return TM.isPPC64()
                ? ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI())
                       ? CSR_PPC64_Altivec_RegMask
diff --git a/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll b/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
--- a/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
+++ b/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
@@ -3,32 +3,20 @@
 ; RUN: llc -O0 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr10 -vec-extabi -stop-after=prologepilog -verify-machineinstrs < %s | \
 ; RUN: FileCheck --check-prefix=CHECK-VEXT %s
 
-; Error pattern will be fixed in https://reviews.llvm.org/D133466
 ; CHECK: name: foo
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v31'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v30'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v29'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v28'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v27'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v26'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v25'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v24'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v23'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v22'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v21'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v20'
+; CHECK-NOT: spill-slot
+; CHECK-NOT: callee-saved-register: '$v31'
+; CHECK-NOT: callee-saved-register: '$v30'
+; CHECK-NOT: callee-saved-register: '$v29'
+; CHECK-NOT: callee-saved-register: '$v28'
+; CHECK-NOT: callee-saved-register: '$v27'
+; CHECK-NOT: callee-saved-register: '$v26'
+; CHECK-NOT: callee-saved-register: '$v25'
+; CHECK-NOT: callee-saved-register: '$v24'
+; CHECK-NOT: callee-saved-register: '$v23'
+; CHECK-NOT: callee-saved-register: '$v22'
+; CHECK-NOT: callee-saved-register: '$v21'
+; CHECK-NOT: callee-saved-register: '$v20'
 
 ; CHECK-VEXT: name: foo
 ; CHECK-VEXT-NOT: spill-slot
@@ -50,32 +38,20 @@
   ret void
 }
 
-; Error pattern will be fixed in https://reviews.llvm.org/D133466
 ; CHECK: name: spill
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v31'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v30'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v29'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v28'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v27'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v26'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v25'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v24'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v23'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v22'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v21'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v20'
+; CHECK-NOT: spill-slot
+; CHECK-NOT: callee-saved-register: '$v31'
+; CHECK-NOT: callee-saved-register: '$v30'
+; CHECK-NOT: callee-saved-register: '$v29'
+; CHECK-NOT: callee-saved-register: '$v28'
+; CHECK-NOT: callee-saved-register: '$v27'
+; CHECK-NOT: callee-saved-register: '$v26'
+; CHECK-NOT: callee-saved-register: '$v25'
+; CHECK-NOT: callee-saved-register: '$v24'
+; CHECK-NOT: callee-saved-register: '$v23'
+; CHECK-NOT: callee-saved-register: '$v22'
+; CHECK-NOT: callee-saved-register: '$v21'
+; CHECK-NOT: callee-saved-register: '$v20'
 
 ; CHECK-VEXT: name: spill
 ; CHECK-VEXT: spill-slot
@@ -109,32 +85,20 @@
   ret void
 }
 
-; Error pattern will be fixed in https://reviews.llvm.org/D133466
 ; CHECK: name: spill2
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v31'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v30'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v29'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v28'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v27'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v26'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v25'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v24'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v23'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v22'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v21'
-; CHECK: spill-slot
-; CHECK-NEXT: callee-saved-register: '$v20'
+; CHECK-NOT: spill-slot
+; CHECK-NOT: callee-saved-register: '$v31'
+; CHECK-NOT: callee-saved-register: '$v30'
+; CHECK-NOT: callee-saved-register: '$v29'
+; CHECK-NOT: callee-saved-register: '$v28'
+; CHECK-NOT: callee-saved-register: '$v27'
+; CHECK-NOT: callee-saved-register: '$v26'
+; CHECK-NOT: callee-saved-register: '$v25'
+; CHECK-NOT: callee-saved-register: '$v24'
+; CHECK-NOT: callee-saved-register: '$v23'
+; CHECK-NOT: callee-saved-register: '$v22'
+; CHECK-NOT: callee-saved-register: '$v21'
+; CHECK-NOT: callee-saved-register: '$v20'
 
 ; CHECK-VEXT: name: spill2
 ; CHECK-VEXT: spill-slot