diff --git a/llvm/lib/Target/PowerPC/PPCCallingConv.td b/llvm/lib/Target/PowerPC/PPCCallingConv.td
--- a/llvm/lib/Target/PowerPC/PPCCallingConv.td
+++ b/llvm/lib/Target/PowerPC/PPCCallingConv.td
@@ -386,3 +386,12 @@
 
 def CSR_64_AllRegs_VSRP :
   CalleeSavedRegs<(add CSR_64_AllRegs_VSX, CSR_ALL_VSRP)>;
+
+def CSR_64_AllRegs_AIX_Dflt_VSRP :
+  CalleeSavedRegs<(add CSR_64_AllRegs_AIX_Dflt_VSX, (sequence "VSRp%u", 0, 25))>;
+
+def CSR_AIX64_VSRP : CalleeSavedRegs<(add CSR_PPC64_Altivec, CSR_VSRP)>;
+
+def CSR_AIX64_R2_VSRP : CalleeSavedRegs<(add CSR_AIX64_VSRP, X2)>;
+
+def CSR_AIX32_VSRP : CalleeSavedRegs<(add CSR_AIX32_Altivec, CSR_VSRP)>;
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -188,8 +188,11 @@
     if (!TM.isPPC64() && Subtarget.isAIXABI())
       report_fatal_error("AnyReg unimplemented on 32-bit AIX.");
     if (Subtarget.hasVSX()) {
-      if (Subtarget.pairedVectorMemops())
+      if (Subtarget.pairedVectorMemops()) {
+        if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
+          return CSR_64_AllRegs_AIX_Dflt_VSRP_SaveList;
         return CSR_64_AllRegs_VSRP_SaveList;
+      }
       if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
         return CSR_64_AllRegs_AIX_Dflt_VSX_SaveList;
       return CSR_64_AllRegs_VSX_SaveList;
@@ -237,8 +240,14 @@
   }
   // Standard calling convention CSRs.
   if (TM.isPPC64()) {
-    if (Subtarget.pairedVectorMemops())
+    if (Subtarget.pairedVectorMemops()) {
+      if (Subtarget.isAIXABI()) {
+        if (!TM.getAIXExtendedAltivecABI())
+          return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
+        return SaveR2 ? CSR_AIX64_R2_VSRP_SaveList : CSR_AIX64_VSRP_SaveList;
+      }
       return SaveR2 ? CSR_SVR464_R2_VSRP_SaveList : CSR_SVR464_VSRP_SaveList;
+    }
     if (Subtarget.hasAltivec() &&
         (!Subtarget.isAIXABI() || TM.getAIXExtendedAltivecABI())) {
       return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
@@ -248,6 +257,9 @@
   }
   // 32-bit targets.
   if (Subtarget.isAIXABI()) {
+    if (Subtarget.pairedVectorMemops())
+      return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_VSRP_SaveList
+                                           : CSR_AIX32_SaveList;
     if (Subtarget.hasAltivec())
       return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList
                                            : CSR_AIX32_SaveList;
@@ -271,8 +283,11 @@
   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
   if (CC == CallingConv::AnyReg) {
     if (Subtarget.hasVSX()) {
-      if (Subtarget.pairedVectorMemops())
+      if (Subtarget.pairedVectorMemops()) {
+        if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
+          return CSR_64_AllRegs_AIX_Dflt_VSRP_RegMask;
         return CSR_64_AllRegs_VSRP_RegMask;
+      }
       if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI())
         return CSR_64_AllRegs_AIX_Dflt_VSX_RegMask;
       return CSR_64_AllRegs_VSX_RegMask;
@@ -286,6 +301,11 @@
   }
 
   if (Subtarget.isAIXABI()) {
+    if (Subtarget.pairedVectorMemops()) {
+      if (!TM.getAIXExtendedAltivecABI())
+        return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask;
+      return TM.isPPC64() ? CSR_AIX64_VSRP_RegMask : CSR_AIX32_VSRP_RegMask;
+    }
     return TM.isPPC64()
                ? ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI())
                       ? CSR_PPC64_Altivec_RegMask
diff --git a/llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll b/llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/aix32-vector-pair-cc-spills.ll
@@ -0,0 +1,27 @@
+; RUN: llc -O0 -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr10 -stop-after=prologepilog -verify-machineinstrs < %s | \
+; RUN: FileCheck --check-prefix=CHECK %s
+; RUN: llc -O0 -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr10 -vec-extabi -stop-after=prologepilog -verify-machineinstrs < %s | \
+; RUN: FileCheck --check-prefix=CHECK-VEXT %s
+
+; CHECK: name: foo
+; CHECK-NOT: spill-slot
+; CHECK-VEXT: name: foo
+; CHECK-VEXT-NOT: spill-slot
+define void @foo() {
+entry:
+  call void @bar(i32 0)
+  ret void
+}
+
+; CHECK: name: spill
+; CHECK-NOT: spill-slot
+; CHECK-VEXT: name: spill
+; CHECK-VEXT: spill-slot
+define void @spill() {
+entry:
+  call void asm sideeffect "nop", "~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
+  call void @bar(i32 0)
+  ret void
+}
+
+declare void @bar(i32)
diff --git a/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll b/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
--- a/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
+++ b/llvm/test/CodeGen/PowerPC/aix64-vector-pair-cc-spills.ll
@@ -4,7 +4,7 @@
 ; RUN: FileCheck --check-prefix=CHECK-VEXT %s
 
 ; CHECK: name: foo
-; CHECK: spill-slot
+; CHECK-NOT: spill-slot
 ; CHECK-VEXT: name: foo
 ; CHECK-VEXT-NOT: spill-slot
 define void @foo() {
@@ -14,7 +14,7 @@
 }
 
 ; CHECK: name: spill
-; CHECK: spill-slot
+; CHECK-NOT: spill-slot
 ; CHECK-VEXT: name: spill
 ; CHECK-VEXT: spill-slot
 define void @spill() {
@@ -25,7 +25,7 @@
 }
 
 ; CHECK: name: spill2
-; CHECK: spill-slot
+; CHECK-NOT: spill-slot
 ; CHECK-VEXT: name: spill2
 ; CHECK-VEXT: spill-slot
 define void @spill2(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {