Index: llvm/docs/RISCVUsage.rst
===================================================================
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -56,7 +56,20 @@
      ``Zba``        Supported
      ``Zbb``        Supported
      ``Zbc``        Supported
+     ``Zbkb``       Supported (See note)
+     ``Zbkc``       Supported
+     ``Zbkx``       Supported (See note)
      ``Zbs``        Supported
+     ``Zknd``       Supported (See note)
+     ``Zkne``       Supported (See note)
+     ``Zknh``       Supported (See note)
+     ``Zksed``      Supported (See note)
+     ``Zksh``       Supported (See note)
+     ``Zkn``        Supported
+     ``Zk``         Supported
+     ``Zkr``        Supported
+     ``Zks``        Supported
+     ``Zkt``        Supported
      ``Zve32x``     Partially Supported
      ``Zve32f``     Partially Supported
      ``Zve64x``     Supported
@@ -79,6 +92,12 @@
 ``Zve32x``, ``Zve32f``, ``Zvl32b``
   LLVM currently assumes a minimum VLEN (vector register width) of 64 bits during compilation, and as a result ``Zve32x`` and ``Zve32f`` are supported only for VLEN>=64.  Assembly tools (e.g. assembler, disassembler, llvm-objdump, etc..) don't have this restriction.
 
+``Zbkb``, ``Zbkx``
+  Pattern matching support for these instructions is incomplete.
+
+``Zknd``, ``Zkne``, ``Zknh``, ``Zksed``, ``Zksh``
+  No pattern matching exists.  As a result, these instructions can only be used from assembler or via intrinsic calls.
+
 Specification Documents
 =======================
 For ratified specifications, please refer to the `official RISC-V International