diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
@@ -1422,6 +1422,16 @@
     return &I;
   }
 
+  // (add A (or A, -A)) --> (and (add A, -1) A)
+  // (add A (or -A, A)) --> (and (add A, -1) A)
+  // (add (or A, -A) A) --> (and (add A, -1) A)
+  // (add (or -A, A) A) --> (and (add A, -1) A)
+  if (match(&I,
+            m_c_BinOp(m_Value(A), m_Or(m_Neg(m_Deferred(A)), m_Deferred(A))))) {
+    Value *Add = Builder.CreateAdd(A, Constant::getAllOnesValue(A->getType()));
+    return BinaryOperator::CreateAnd(Add, A);
+  }
+
   // Canonicalize ((A & -A) - 1) --> ((A - 1) & ~A)
   // Forms all commutable operations, and simplifies ctpop -> cttz folds.
   if (match(&I,
diff --git a/llvm/test/Transforms/InstCombine/add_or_sub.ll b/llvm/test/Transforms/InstCombine/add_or_sub.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/add_or_sub.ll
@@ -0,0 +1,81 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+declare void @use19(i19)
+
+define i32 @add_or_sub_comb_i32(i32 %x) {
+; CHECK-LABEL: @add_or_sub_comb_i32(
+; CHECK-NEXT:    [[TMP1:%.*]] = add i32 [[X:%.*]], -1
+; CHECK-NEXT:    [[ADD:%.*]] = and i32 [[TMP1]], [[X]]
+; CHECK-NEXT:    ret i32 [[ADD]]
+;
+  %sub = sub i32 0, %x
+  %or = or i32 %sub, %x
+  %add = add i32 %or, %x
+  ret i32 %add
+}
+
+define i8 @add_or_sub_comb_i8(i8 %x) {
+; CHECK-LABEL: @add_or_sub_comb_i8(
+; CHECK-NEXT:    [[TMP1:%.*]] = add i8 [[X:%.*]], -1
+; CHECK-NEXT:    [[ADD:%.*]] = and i8 [[TMP1]], [[X]]
+; CHECK-NEXT:    ret i8 [[ADD]]
+;
+  %sub = sub i8 0, %x
+  %or = or i8 %sub, %x
+  %add = add i8 %or, %x
+  ret i8 %add
+}
+
+define <3 x i32> @add_or_sub_comb_i32vec(<3 x i32> %x) {
+; CHECK-LABEL: @add_or_sub_comb_i32vec(
+; CHECK-NEXT:    [[TMP1:%.*]] = add <3 x i32> [[X:%.*]], <i32 -1, i32 -1, i32 -1>
+; CHECK-NEXT:    [[ADD:%.*]] = and <3 x i32> [[TMP1]], [[X]]
+; CHECK-NEXT:    ret <3 x i32> [[ADD]]
+;
+  %sub = sub <3 x i32> <i32 0, i32 0, i32 0>, %x
+  %or = or <3 x i32> %sub, %x
+  %add = add <3 x i32> %or, %x
+  ret <3 x i32> %add
+}
+
+define <4 x i16> @add_or_sub_comb_i32vec_undef(<4 x i16> %x) {
+; CHECK-LABEL: @add_or_sub_comb_i32vec_undef(
+; CHECK-NEXT:    [[ADD:%.*]] = add <4 x i16> [[X:%.*]], <i16 -1, i16 -1, i16 -1, i16 -1>
+; CHECK-NEXT:    ret <4 x i16> [[ADD]]
+;
+  %sub = sub <4 x i16> <i16 -1, i16 undef, i16 undef, i16 -1>, %x
+  %or = or <4 x i16> %sub, %x
+  %add = add <4 x i16> %or, %x
+  ret <4 x i16> %add
+}
+
+define i19 @add_or_sub_comb_i19_multiuse(i19 %x) {
+; CHECK-LABEL: @add_or_sub_comb_i19_multiuse(
+; CHECK-NEXT:    [[SUB:%.*]] = sub i19 0, [[X:%.*]]
+; CHECK-NEXT:    call void @use19(i19 [[SUB]])
+; CHECK-NEXT:    [[OR:%.*]] = or i19 [[SUB]], [[X]]
+; CHECK-NEXT:    call void @use19(i19 [[OR]])
+; CHECK-NEXT:    [[TMP1:%.*]] = add i19 [[X]], -1
+; CHECK-NEXT:    [[ADD:%.*]] = and i19 [[TMP1]], [[X]]
+; CHECK-NEXT:    ret i19 [[ADD]]
+;
+  %sub = sub i19 0, %x
+  call void @use19(i19 %sub) ; extra use of sub
+  %or = or i19 %sub, %x
+  call void @use19(i19 %or) ; extra use of or
+  %add = add i19 %or, %x
+  ret i19 %add
+}
+
+define i10 @add_or_sub_comb_i10_nsw_nuw(i10 %x) {
+; CHECK-LABEL: @add_or_sub_comb_i10_nsw_nuw(
+; CHECK-NEXT:    [[TMP1:%.*]] = add i10 [[X:%.*]], -1
+; CHECK-NEXT:    [[ADD:%.*]] = and i10 [[TMP1]], [[X]]
+; CHECK-NEXT:    ret i10 [[ADD]]
+;
+  %sub = sub i10 0, %x
+  %or = or i10 %sub, %x
+  %add = add nsw nuw i10 %or, %x
+  ret i10 %add
+}