diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
--- a/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-fp-reduce.ll
@@ -10,7 +10,7 @@
 ;
 
 ; No single instruction NEON support. Use SVE.
-define half @fadda_v4f16(half %start, <4 x half> %a) vscale_range(1,0) #0 {
+define half @fadda_v4f16(half %start, <4 x half> %a) vscale_range(2,0) #0 {
 ; CHECK-LABEL: fadda_v4f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
@@ -24,7 +24,7 @@
 }
 
 ; No single instruction NEON support. Use SVE.
-define half @fadda_v8f16(half %start, <8 x half> %a) vscale_range(1,0) #0 {
+define half @fadda_v8f16(half %start, <8 x half> %a) vscale_range(2,0) #0 {
 ; CHECK-LABEL: fadda_v8f16:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $h0 killed $h0 def $z0
@@ -106,7 +106,7 @@
 }
 
 ; No single instruction NEON support. Use SVE.
-define float @fadda_v2f32(float %start, <2 x float> %a) vscale_range(1,0) #0 {
+define float @fadda_v2f32(float %start, <2 x float> %a) vscale_range(2,0) #0 {
 ; CHECK-LABEL: fadda_v2f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 def $z0
@@ -120,7 +120,7 @@
 }
 
 ; No single instruction NEON support. Use SVE.
-define float @fadda_v4f32(float %start, <4 x float> %a) vscale_range(1,0) #0 {
+define float @fadda_v4f32(float %start, <4 x float> %a) vscale_range(2,0) #0 {
 ; CHECK-LABEL: fadda_v4f32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $s0 killed $s0 def $z0
@@ -202,7 +202,7 @@
 }
 
 ; No single instruction NEON support. Use SVE.
-define double @fadda_v1f64(double %start, <1 x double> %a) vscale_range(1,0) #0 {
+define double @fadda_v1f64(double %start, <1 x double> %a) vscale_range(2,0) #0 {
 ; CHECK-LABEL: fadda_v1f64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fadd d0, d0, d1