diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -259,14 +259,19 @@ MCSymbol *HwasanTagMismatchV2Sym = OutContext.getOrCreateSymbol("__hwasan_tag_mismatch_v2"); + // Annotate symbol as one having incompatible calling convention, so + // run-time linkers can instead eagerly bind this function + cast(HwasanTagMismatchV2Sym) + ->setOther(ELF::STO_RISCV_VARIANT_CC); const MCSymbolRefExpr *HwasanTagMismatchV2Ref = MCSymbolRefExpr::create(HwasanTagMismatchV2Sym, OutContext); + auto Expr = RISCVMCExpr::create(HwasanTagMismatchV2Ref, + RISCVMCExpr::VK_RISCV_CALL, OutContext); for (auto &P : HwasanMemaccessSymbols) { unsigned Reg = std::get<0>(P.first); uint32_t AccessInfo = std::get<1>(P.first); - const MCSymbolRefExpr *HwasanTagMismatchRef = HwasanTagMismatchV2Ref; MCSymbol *Sym = P.second; unsigned Size = @@ -443,39 +448,7 @@ .addImm(AccessInfo & HWASanAccessInfo::RuntimeMask), *STI); - // Intentionally load the GOT entry and branch to it, rather than possibly - // late binding the function, which may clobber the registers before we have - // a chance to save them. - RISCVMCExpr::VariantKind VKHi; - unsigned SecondOpcode; - if (OutContext.getObjectFileInfo()->isPositionIndependent()) { - SecondOpcode = RISCV::LD; - VKHi = RISCVMCExpr::VK_RISCV_GOT_HI; - } else { - SecondOpcode = RISCV::ADDI; - VKHi = RISCVMCExpr::VK_RISCV_PCREL_HI; - } - auto ExprHi = RISCVMCExpr::create(HwasanTagMismatchRef, VKHi, OutContext); - - MCSymbol *TmpLabel = - OutContext.createTempSymbol("pcrel_hi", /* AlwaysAddSuffix */ true); - OutStreamer->emitLabel(TmpLabel); - const MCExpr *ExprLo = - RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, OutContext), - RISCVMCExpr::VK_RISCV_PCREL_LO, OutContext); - - OutStreamer->emitInstruction( - MCInstBuilder(RISCV::AUIPC).addReg(RISCV::X6).addExpr(ExprHi), *STI); - OutStreamer->emitInstruction(MCInstBuilder(SecondOpcode) - .addReg(RISCV::X6) - .addReg(RISCV::X6) - .addExpr(ExprLo), - *STI); - - OutStreamer->emitInstruction(MCInstBuilder(RISCV::JALR) - .addReg(RISCV::X0) - .addReg(RISCV::X6) - .addImm(0), + OutStreamer->emitInstruction(MCInstBuilder(RISCV::PseudoCALL).addExpr(Expr), *STI); } } diff --git a/llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll b/llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll --- a/llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll +++ b/llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv64 < %s | FileCheck --check-prefixes=CHECK,NOPIC %s -; RUN: llc -mtriple=riscv64 --relocation-model=pic < %s | FileCheck --check-prefixes=CHECK,PIC %s +; RUN: llc -mtriple=riscv64 < %s | FileCheck %s +; RUN: llc -mtriple=riscv64 --relocation-model=pic < %s | FileCheck %s define i8* @f2(i8* %x0, i8* %x1) { ; CHECK-LABEL: f2: @@ -49,12 +49,4 @@ ; CHECK-NEXT: sd s0, 64(sp) ; CHECK-NEXT: sd ra, 8(sp) ; CHECK-NEXT: li a1, 2 -; CHECK-NEXT: .Lpcrel_hi0: -; NOPIC-NEXT: auipc t1, %pcrel_hi(__hwasan_tag_mismatch_v2) -; NOPIC-NEXT: addi t1, t1, %pcrel_lo(.Lpcrel_hi0) -; PIC-NEXT: auipc t1, %got_pcrel_hi(__hwasan_tag_mismatch_v2) -; PIC-NEXT: ld t1, %pcrel_lo(.Lpcrel_hi0)(t1) -; CHECK-NEXT: jr t1 -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; NOPIC: {{.*}} -; PIC: {{.*}} +; CHECK-NEXT: call __hwasan_tag_mismatch_v2