diff --git a/llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll b/llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
--- a/llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
+++ b/llvm/test/CodeGen/RISCV/hwasan-check-memaccess.ll
@@ -1,6 +1,6 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 < %s | FileCheck --check-prefixes=CHECK,NOPIC %s
-; RUN: llc -mtriple=riscv64 --relocation-model=pic < %s | FileCheck --check-prefixes=CHECK,PIC %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --no-generate-body-for-unused-prefixes
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 --relocation-model=pic < %s | FileCheck %s
 
 define i8* @f2(i8* %x0, i8* %x1) {
 ; CHECK-LABEL: f2:
@@ -20,6 +20,8 @@
 
 declare void @llvm.hwasan.check.memaccess.shortgranules(i8*, i8*, i32)
 
+; Below is a manually written checks
+; UTC_ARGS: --disable
 ; CHECK: .section        .text.hot,"axG",@progbits,__hwasan_check_x10_2_short,comdat
 ; CHECK-NEXT: .type   __hwasan_check_x10_2_short,@function
 ; CHECK-NEXT: .weak   __hwasan_check_x10_2_short
@@ -49,12 +51,4 @@
 ; CHECK-NEXT: sd      s0, 64(sp)
 ; CHECK-NEXT: sd      ra, 8(sp)
 ; CHECK-NEXT: li      a1, 2
-; CHECK-NEXT: .Lpcrel_hi0:
-; NOPIC-NEXT: auipc   t1, %pcrel_hi(__hwasan_tag_mismatch_v2)
-; NOPIC-NEXT: addi    t1, t1, %pcrel_lo(.Lpcrel_hi0)
-; PIC-NEXT: auipc   t1, %got_pcrel_hi(__hwasan_tag_mismatch_v2)
-; PIC-NEXT: ld      t1, %pcrel_lo(.Lpcrel_hi0)(t1)
-; CHECK-NEXT: jr      t1
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; NOPIC: {{.*}}
-; PIC: {{.*}}
+; CHECK-NEXT: call    __hwasan_tag_mismatch_v2