diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -2352,7 +2352,7 @@
   LLT EltTy = VecTy.getElementType();
   assert(EltTy == MRI.getType(Dst));
 
-  if (IdxVal < VecTy.getNumElements()) {
+  if (IdxVal >= 0 && IdxVal < VecTy.getNumElements()) {
     auto Unmerge = B.buildUnmerge(EltTy, Vec);
     B.buildCopy(Dst, Unmerge.getReg(IdxVal));
   } else {
@@ -2389,7 +2389,7 @@
   (void)Ins;
 
   unsigned NumElts = VecTy.getNumElements();
-  if (IdxVal < NumElts) {
+  if (IdxVal >= 0 && IdxVal < NumElts) {
     SmallVector<Register, 8> SrcRegs;
     for (unsigned i = 0; i < NumElts; ++i)
       SrcRegs.push_back(MRI.createGenericVirtualRegister(EltTy));
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.ll
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn -global-isel < %s | FileCheck %s
+
+define void @f() {
+; CHECK-LABEL: f:
+; CHECK:       ; %bb.0: ; %BB
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+BB:
+  br label %BB2
+
+BB2:                                              ; preds = %BB
+  br label %BB1
+
+BB1:                                              ; preds = %BB2
+  %B1 = sub <2 x i8> <i8 16, i8 16>, <i8 16, i8 16>
+  %A = alloca i8, align 4, addrspace(5)
+  %L1 = load i8, i8 addrspace(5)* %A, align 1
+  %I = insertelement <2 x i8> %B1, i8 -128, i8 %L1
+  %E1 = extractelement <2 x i8> %I, i1 true
+  store i8 %E1, i8 addrspace(5)* %A, align 1
+  ret void
+}