diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -445,130 +445,6 @@
     {Intrinsic::ctpop, MVT::nxv2i64, 21},
     {Intrinsic::ctpop, MVT::nxv4i64, 21},
     {Intrinsic::ctpop, MVT::nxv8i64, 21},
-    {Intrinsic::sadd_sat, MVT::v2i8, 1},
-    {Intrinsic::sadd_sat, MVT::v4i8, 1},
-    {Intrinsic::sadd_sat, MVT::v8i8, 1},
-    {Intrinsic::sadd_sat, MVT::v16i8, 1},
-    {Intrinsic::sadd_sat, MVT::nxv2i8, 1},
-    {Intrinsic::sadd_sat, MVT::nxv4i8, 1},
-    {Intrinsic::sadd_sat, MVT::nxv8i8, 1},
-    {Intrinsic::sadd_sat, MVT::nxv16i8, 1},
-    {Intrinsic::sadd_sat, MVT::v2i16, 1},
-    {Intrinsic::sadd_sat, MVT::v4i16, 1},
-    {Intrinsic::sadd_sat, MVT::v8i16, 1},
-    {Intrinsic::sadd_sat, MVT::v16i16, 1},
-    {Intrinsic::sadd_sat, MVT::nxv2i16, 1},
-    {Intrinsic::sadd_sat, MVT::nxv4i16, 1},
-    {Intrinsic::sadd_sat, MVT::nxv8i16, 1},
-    {Intrinsic::sadd_sat, MVT::nxv16i16, 1},
-    {Intrinsic::sadd_sat, MVT::v2i32, 1},
-    {Intrinsic::sadd_sat, MVT::v4i32, 1},
-    {Intrinsic::sadd_sat, MVT::v8i32, 1},
-    {Intrinsic::sadd_sat, MVT::v16i32, 1},
-    {Intrinsic::sadd_sat, MVT::nxv2i32, 1},
-    {Intrinsic::sadd_sat, MVT::nxv4i32, 1},
-    {Intrinsic::sadd_sat, MVT::nxv8i32, 1},
-    {Intrinsic::sadd_sat, MVT::nxv16i32, 1},
-    {Intrinsic::sadd_sat, MVT::v2i64, 1},
-    {Intrinsic::sadd_sat, MVT::v4i64, 1},
-    {Intrinsic::sadd_sat, MVT::v8i64, 1},
-    {Intrinsic::sadd_sat, MVT::v16i64, 1},
-    {Intrinsic::sadd_sat, MVT::nxv2i64, 1},
-    {Intrinsic::sadd_sat, MVT::nxv4i64, 1},
-    {Intrinsic::sadd_sat, MVT::nxv8i64, 1},
-    {Intrinsic::uadd_sat, MVT::v2i8, 1},
-    {Intrinsic::uadd_sat, MVT::v4i8, 1},
-    {Intrinsic::uadd_sat, MVT::v8i8, 1},
-    {Intrinsic::uadd_sat, MVT::v16i8, 1},
-    {Intrinsic::uadd_sat, MVT::nxv2i8, 1},
-    {Intrinsic::uadd_sat, MVT::nxv4i8, 1},
-    {Intrinsic::uadd_sat, MVT::nxv8i8, 1},
-    {Intrinsic::uadd_sat, MVT::nxv16i8, 1},
-    {Intrinsic::uadd_sat, MVT::v2i16, 1},
-    {Intrinsic::uadd_sat, MVT::v4i16, 1},
-    {Intrinsic::uadd_sat, MVT::v8i16, 1},
-    {Intrinsic::uadd_sat, MVT::v16i16, 1},
-    {Intrinsic::uadd_sat, MVT::nxv2i16, 1},
-    {Intrinsic::uadd_sat, MVT::nxv4i16, 1},
-    {Intrinsic::uadd_sat, MVT::nxv8i16, 1},
-    {Intrinsic::uadd_sat, MVT::nxv16i16, 1},
-    {Intrinsic::uadd_sat, MVT::v2i32, 1},
-    {Intrinsic::uadd_sat, MVT::v4i32, 1},
-    {Intrinsic::uadd_sat, MVT::v8i32, 1},
-    {Intrinsic::uadd_sat, MVT::v16i32, 1},
-    {Intrinsic::uadd_sat, MVT::nxv2i32, 1},
-    {Intrinsic::uadd_sat, MVT::nxv4i32, 1},
-    {Intrinsic::uadd_sat, MVT::nxv8i32, 1},
-    {Intrinsic::uadd_sat, MVT::nxv16i32, 1},
-    {Intrinsic::uadd_sat, MVT::v2i64, 1},
-    {Intrinsic::uadd_sat, MVT::v4i64, 1},
-    {Intrinsic::uadd_sat, MVT::v8i64, 1},
-    {Intrinsic::uadd_sat, MVT::v16i64, 1},
-    {Intrinsic::uadd_sat, MVT::nxv2i64, 1},
-    {Intrinsic::uadd_sat, MVT::nxv4i64, 1},
-    {Intrinsic::uadd_sat, MVT::nxv8i64, 1},
-    {Intrinsic::usub_sat, MVT::v2i8, 1},
-    {Intrinsic::usub_sat, MVT::v4i8, 1},
-    {Intrinsic::usub_sat, MVT::v8i8, 1},
-    {Intrinsic::usub_sat, MVT::v16i8, 1},
-    {Intrinsic::usub_sat, MVT::nxv2i8, 1},
-    {Intrinsic::usub_sat, MVT::nxv4i8, 1},
-    {Intrinsic::usub_sat, MVT::nxv8i8, 1},
-    {Intrinsic::usub_sat, MVT::nxv16i8, 1},
-    {Intrinsic::usub_sat, MVT::v2i16, 1},
-    {Intrinsic::usub_sat, MVT::v4i16, 1},
-    {Intrinsic::usub_sat, MVT::v8i16, 1},
-    {Intrinsic::usub_sat, MVT::v16i16, 1},
-    {Intrinsic::usub_sat, MVT::nxv2i16, 1},
-    {Intrinsic::usub_sat, MVT::nxv4i16, 1},
-    {Intrinsic::usub_sat, MVT::nxv8i16, 1},
-    {Intrinsic::usub_sat, MVT::nxv16i16, 1},
-    {Intrinsic::usub_sat, MVT::v2i32, 1},
-    {Intrinsic::usub_sat, MVT::v4i32, 1},
-    {Intrinsic::usub_sat, MVT::v8i32, 1},
-    {Intrinsic::usub_sat, MVT::v16i32, 1},
-    {Intrinsic::usub_sat, MVT::nxv2i32, 1},
-    {Intrinsic::usub_sat, MVT::nxv4i32, 1},
-    {Intrinsic::usub_sat, MVT::nxv8i32, 1},
-    {Intrinsic::usub_sat, MVT::nxv16i32, 1},
-    {Intrinsic::usub_sat, MVT::v2i64, 1},
-    {Intrinsic::usub_sat, MVT::v4i64, 1},
-    {Intrinsic::usub_sat, MVT::v8i64, 1},
-    {Intrinsic::usub_sat, MVT::v16i64, 1},
-    {Intrinsic::usub_sat, MVT::nxv2i64, 1},
-    {Intrinsic::usub_sat, MVT::nxv4i64, 1},
-    {Intrinsic::usub_sat, MVT::nxv8i64, 1},
-    {Intrinsic::ssub_sat, MVT::v2i8, 1},
-    {Intrinsic::ssub_sat, MVT::v4i8, 1},
-    {Intrinsic::ssub_sat, MVT::v8i8, 1},
-    {Intrinsic::ssub_sat, MVT::v16i8, 1},
-    {Intrinsic::ssub_sat, MVT::nxv2i8, 1},
-    {Intrinsic::ssub_sat, MVT::nxv4i8, 1},
-    {Intrinsic::ssub_sat, MVT::nxv8i8, 1},
-    {Intrinsic::ssub_sat, MVT::nxv16i8, 1},
-    {Intrinsic::ssub_sat, MVT::v2i16, 1},
-    {Intrinsic::ssub_sat, MVT::v4i16, 1},
-    {Intrinsic::ssub_sat, MVT::v8i16, 1},
-    {Intrinsic::ssub_sat, MVT::v16i16, 1},
-    {Intrinsic::ssub_sat, MVT::nxv2i16, 1},
-    {Intrinsic::ssub_sat, MVT::nxv4i16, 1},
-    {Intrinsic::ssub_sat, MVT::nxv8i16, 1},
-    {Intrinsic::ssub_sat, MVT::nxv16i16, 1},
-    {Intrinsic::ssub_sat, MVT::v2i32, 1},
-    {Intrinsic::ssub_sat, MVT::v4i32, 1},
-    {Intrinsic::ssub_sat, MVT::v8i32, 1},
-    {Intrinsic::ssub_sat, MVT::v16i32, 1},
-    {Intrinsic::ssub_sat, MVT::nxv2i32, 1},
-    {Intrinsic::ssub_sat, MVT::nxv4i32, 1},
-    {Intrinsic::ssub_sat, MVT::nxv8i32, 1},
-    {Intrinsic::ssub_sat, MVT::nxv16i32, 1},
-    {Intrinsic::ssub_sat, MVT::v2i64, 1},
-    {Intrinsic::ssub_sat, MVT::v4i64, 1},
-    {Intrinsic::ssub_sat, MVT::v8i64, 1},
-    {Intrinsic::ssub_sat, MVT::v16i64, 1},
-    {Intrinsic::ssub_sat, MVT::nxv2i64, 1},
-    {Intrinsic::ssub_sat, MVT::nxv4i64, 1},
-    {Intrinsic::ssub_sat, MVT::nxv8i64, 1},
 };
 
 InstructionCost
@@ -586,6 +462,15 @@
       return LT.first;
     break;
   }
+  case Intrinsic::sadd_sat:
+  case Intrinsic::ssub_sat:
+  case Intrinsic::uadd_sat:
+  case Intrinsic::usub_sat: {
+    auto LT = getTypeLegalizationCost(RetTy);
+    if (ST->hasVInstructions() && LT.second.isVector())
+      return LT.first;
+    break;
+  }
   // TODO: add more intrinsic
   case Intrinsic::experimental_stepvector: {
     unsigned Cost = 1; // vid