diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -163,6 +163,8 @@ Other Changes ------------- +* -O0 and -O1 no longer generate tail calls unless required. + External Open Source Projects Using LLVM 15 =========================================== diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h --- a/llvm/include/llvm/CodeGen/Passes.h +++ b/llvm/include/llvm/CodeGen/Passes.h @@ -79,6 +79,9 @@ /// matching during instruction selection. FunctionPass *createCodeGenPreparePass(); + /// Pass to add the "disable-tail-calls" function attribute to all functions. + FunctionPass *createAddDisableTailCallsPass(); + /// AtomicExpandID -- Lowers atomic operations in terms of either cmpxchg /// load-linked/store-conditional loops. extern char &AtomicExpandID; diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -60,6 +60,7 @@ void initializeAAEvalLegacyPassPass(PassRegistry&); void initializeAAResultsWrapperPassPass(PassRegistry&); void initializeADCELegacyPassPass(PassRegistry&); +void initializeAddDisableTailCallsPassPass(PassRegistry &); void initializeAddDiscriminatorsLegacyPassPass(PassRegistry&); void initializeAddFSDiscriminatorsPass(PassRegistry &); void initializeAggressiveInstCombinerLegacyPassPass(PassRegistry&); diff --git a/llvm/include/llvm/LinkAllPasses.h b/llvm/include/llvm/LinkAllPasses.h --- a/llvm/include/llvm/LinkAllPasses.h +++ b/llvm/include/llvm/LinkAllPasses.h @@ -227,6 +227,7 @@ (void) llvm::createFixIrreduciblePass(); (void)llvm::createFunctionSpecializationPass(); (void)llvm::createSelectOptimizePass(); + (void)llvm::createAddDisableTailCallsPass(); (void)new llvm::IntervalPartition(); (void)new llvm::ScalarEvolutionWrapperPass(); diff --git a/llvm/lib/CodeGen/AddDisableTailCalls.cpp b/llvm/lib/CodeGen/AddDisableTailCalls.cpp new file mode 100644 --- /dev/null +++ b/llvm/lib/CodeGen/AddDisableTailCalls.cpp @@ -0,0 +1,58 @@ +//===- AddDisableTailCalls.cpp --------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Pass to add the "disable-tail-calls" attribute to all functions to prevent +// the backend from emitting tail calls unless required. +// +//===----------------------------------------------------------------------===// + +#include "llvm/CodeGen/Passes.h" +#include "llvm/IR/Function.h" +#include "llvm/InitializePasses.h" +#include "llvm/Pass.h" + +#define DEBUG_TYPE "add-disable-tail-calls" + +using namespace llvm; + +namespace { + +class AddDisableTailCallsPass : public FunctionPass { +public: + static char ID; // Pass identification, replacement for typeid + + AddDisableTailCallsPass() : FunctionPass(ID) { + initializeAddDisableTailCallsPassPass(*PassRegistry::getPassRegistry()); + } + + bool runOnFunction(Function &F) override { + if (!F.hasFnAttribute("disable-tail-calls")) { + F.addFnAttr("disable-tail-calls", "true"); + return true; + } + return false; + } + + void getAnalysisUsage(AnalysisUsage &AU) const override { + // This pass doesn't affect any IR analyses. + AU.setPreservesAll(); + } +}; +} // namespace + +FunctionPass *llvm::createAddDisableTailCallsPass() { + return new AddDisableTailCallsPass(); +} + +char AddDisableTailCallsPass::ID = 0; +INITIALIZE_PASS_BEGIN(AddDisableTailCallsPass, DEBUG_TYPE, + "Add \"disable-tail-calls\" attribute to functions", + false, false) +INITIALIZE_PASS_END(AddDisableTailCallsPass, DEBUG_TYPE, + "Add \"disable-tail-calls\" attribute to functions", false, + false) diff --git a/llvm/lib/CodeGen/CMakeLists.txt b/llvm/lib/CodeGen/CMakeLists.txt --- a/llvm/lib/CodeGen/CMakeLists.txt +++ b/llvm/lib/CodeGen/CMakeLists.txt @@ -23,6 +23,7 @@ endif() add_llvm_component_library(LLVMCodeGen + AddDisableTailCalls.cpp AggressiveAntiDepBreaker.cpp AllocationOrder.cpp Analysis.cpp diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp --- a/llvm/lib/CodeGen/CodeGen.cpp +++ b/llvm/lib/CodeGen/CodeGen.cpp @@ -19,6 +19,7 @@ /// initializeCodeGen - Initialize all passes linked into the CodeGen library. void llvm::initializeCodeGen(PassRegistry &Registry) { + initializeAddDisableTailCallsPassPass(Registry); initializeAtomicExpandPass(Registry); initializeBasicBlockSectionsPass(Registry); initializeBranchFolderPassPass(Registry); diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -96,6 +96,9 @@ cl::Hidden, cl::desc("Disable ConstantHoisting")); static cl::opt DisableCGP("disable-cgp", cl::Hidden, cl::desc("Disable Codegen Prepare")); +static cl::opt + DisableAddDisableTailCalls("disable-add-disable-tail-calls", cl::Hidden, + cl::desc("Disable AddDisableTailCalls")); static cl::opt DisableCopyProp("disable-copyprop", cl::Hidden, cl::desc("Disable Copy Propagation pass")); static cl::opt DisablePartialLibcallInlining("disable-partial-libcall-inlining", @@ -1011,6 +1014,9 @@ addPass(createSafeStackPass()); addPass(createStackProtectorPass()); + if (getOptLevel() <= CodeGenOpt::Less && !DisableAddDisableTailCalls) + addPass(createAddDisableTailCallsPass()); + if (PrintISelInput) addPass(createPrintFunctionPass( dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n")); diff --git a/llvm/test/CodeGen/AArch64/O0-pipeline.ll b/llvm/test/CodeGen/AArch64/O0-pipeline.ll --- a/llvm/test/CodeGen/AArch64/O0-pipeline.ll +++ b/llvm/test/CodeGen/AArch64/O0-pipeline.ll @@ -28,6 +28,7 @@ ; CHECK-NEXT: Exception handling preparation ; CHECK-NEXT: Safe Stack instrumentation pass ; CHECK-NEXT: Insert stack protectors +; CHECK-NEXT: Add "disable-tail-calls" attribute to functions ; CHECK-NEXT: Module Verifier ; CHECK-NEXT: Analysis containing CSE Info ; CHECK-NEXT: IRTranslator diff --git a/llvm/test/CodeGen/AArch64/arm64-abi_align.ll b/llvm/test/CodeGen/AArch64/arm64-abi_align.ll --- a/llvm/test/CodeGen/AArch64/arm64-abi_align.ll +++ b/llvm/test/CodeGen/AArch64/arm64-abi_align.ll @@ -1,5 +1,5 @@ ; RUN: llc -aarch64-load-store-renaming=true < %s -mtriple=arm64-apple-darwin -mcpu=cyclone -enable-misched=false -frame-pointer=all | FileCheck %s -; RUN: llc -aarch64-load-store-renaming=true < %s -mtriple=arm64-apple-darwin -O0 -frame-pointer=all -fast-isel | FileCheck -check-prefix=FAST %s +; RUN: llc -aarch64-load-store-renaming=true < %s -mtriple=arm64-apple-darwin -O0 -disable-add-disable-tail-calls -frame-pointer=all -fast-isel | FileCheck -check-prefix=FAST %s ; rdar://12648441 ; Generated from arm64-arguments.c with -O2. diff --git a/llvm/test/CodeGen/AArch64/dllimport.ll b/llvm/test/CodeGen/AArch64/dllimport.ll --- a/llvm/test/CodeGen/AArch64/dllimport.ll +++ b/llvm/test/CodeGen/AArch64/dllimport.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple aarch64-unknown-windows-msvc -filetype asm -o - %s | FileCheck %s -check-prefixes=CHECK,DAG-ISEL ; RUN: llc -mtriple aarch64-unknown-windows-msvc -fast-isel -filetype asm -o - %s | FileCheck %s -check-prefixes=CHECK,FAST-ISEL -; RUN: llc -mtriple aarch64-unknown-windows-msvc -verify-machineinstrs -O0 -filetype asm -o - %s | FileCheck %s -check-prefixes=CHECK,GLOBAL-ISEL,GLOBAL-ISEL-FALLBACK +; RUN: llc -mtriple aarch64-unknown-windows-msvc -verify-machineinstrs -O0 -disable-add-disable-tail-calls -filetype asm -o - %s | FileCheck %s -check-prefixes=CHECK,GLOBAL-ISEL,GLOBAL-ISEL-FALLBACK @var = external dllimport global i32 @ext = external global i32 diff --git a/llvm/test/CodeGen/AArch64/tailcall-fastisel.ll b/llvm/test/CodeGen/AArch64/tailcall-fastisel.ll --- a/llvm/test/CodeGen/AArch64/tailcall-fastisel.ll +++ b/llvm/test/CodeGen/AArch64/tailcall-fastisel.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=arm64-apple-darwin -O0 -fast-isel | FileCheck %s +; RUN: llc < %s -mtriple=arm64-apple-darwin -O0 -disable-add-disable-tail-calls -fast-isel | FileCheck %s ; CHECK: b _foo0 diff --git a/llvm/test/CodeGen/AArch64/win64_vararg_float.ll b/llvm/test/CodeGen/AArch64/win64_vararg_float.ll --- a/llvm/test/CodeGen/AArch64/win64_vararg_float.ll +++ b/llvm/test/CodeGen/AArch64/win64_vararg_float.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=aarch64-windows -verify-machineinstrs | FileCheck %s --check-prefixes=DAGISEL -; RUN: llc < %s -mtriple=aarch64-windows -verify-machineinstrs -O0 -fast-isel | FileCheck %s --check-prefixes=O0,FASTISEL -; RUN: llc < %s -mtriple=aarch64-windows -verify-machineinstrs -O0 -global-isel | FileCheck %s --check-prefixes=O0,GISEL +; RUN: llc < %s -mtriple=aarch64-windows -verify-machineinstrs -O0 -disable-add-disable-tail-calls -fast-isel | FileCheck %s --check-prefixes=O0,FASTISEL +; RUN: llc < %s -mtriple=aarch64-windows -verify-machineinstrs -O0 -disable-add-disable-tail-calls -global-isel | FileCheck %s --check-prefixes=O0,GISEL define void @float_va_fn(float %a, i32 %b, ...) nounwind { ; DAGISEL-LABEL: float_va_fn: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -; RUN: llc -march=amdgcn -mcpu=fiji -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs -o - %s | FileCheck %s +; RUN: llc -march=amdgcn -mcpu=fiji -O0 -disable-add-disable-tail-calls -stop-after=irtranslator -global-isel -verify-machineinstrs -o - %s | FileCheck %s ; TODO: Could potentially insert it here define void @arg_align_8(i8 addrspace(1)* align 8 %arg0) { diff --git a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll --- a/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll +++ b/llvm/test/CodeGen/AMDGPU/llc-pipeline.ll @@ -87,6 +87,7 @@ ; GCN-O0-NEXT: FunctionPass Manager ; GCN-O0-NEXT: Safe Stack instrumentation pass ; GCN-O0-NEXT: Insert stack protectors +; GCN-O0-NEXT: Add "disable-tail-calls" attribute to functions ; GCN-O0-NEXT: Dominator Tree Construction ; GCN-O0-NEXT: Post-Dominator Tree Construction ; GCN-O0-NEXT: Natural Loop Information @@ -265,6 +266,7 @@ ; GCN-O1-NEXT: FunctionPass Manager ; GCN-O1-NEXT: Safe Stack instrumentation pass ; GCN-O1-NEXT: Insert stack protectors +; GCN-O1-NEXT: Add "disable-tail-calls" attribute to functions ; GCN-O1-NEXT: Dominator Tree Construction ; GCN-O1-NEXT: Post-Dominator Tree Construction ; GCN-O1-NEXT: Natural Loop Information @@ -546,6 +548,7 @@ ; GCN-O1-OPTS-NEXT: FunctionPass Manager ; GCN-O1-OPTS-NEXT: Safe Stack instrumentation pass ; GCN-O1-OPTS-NEXT: Insert stack protectors +; GCN-O1-OPTS-NEXT: Add "disable-tail-calls" attribute to functions ; GCN-O1-OPTS-NEXT: Dominator Tree Construction ; GCN-O1-OPTS-NEXT: Post-Dominator Tree Construction ; GCN-O1-OPTS-NEXT: Natural Loop Information diff --git a/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll b/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll --- a/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll +++ b/llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -O0 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -O0 -disable-add-disable-tail-calls -verify-machineinstrs < %s | FileCheck %s ; FP is in CSR range, modified. define hidden fastcc void @callee_has_fp() #1 { diff --git a/llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll b/llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll --- a/llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll +++ b/llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx803 -O0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s +; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx803 -O0 -disable-add-disable-tail-calls -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s define void @child_function() #0 { call void asm sideeffect "", "~{vcc}" () #0 diff --git a/llvm/test/CodeGen/ARM/fast-tail-call.ll b/llvm/test/CodeGen/ARM/fast-tail-call.ll --- a/llvm/test/CodeGen/ARM/fast-tail-call.ll +++ b/llvm/test/CodeGen/ARM/fast-tail-call.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=thumbv7-linux-gnueabi -O0 < %s | FileCheck %s +; RUN: llc -mtriple=thumbv7-linux-gnueabi -disable-add-disable-tail-calls -O0 < %s | FileCheck %s ; RUN: llc -mtriple=thumbv8m.base-arm-none-eabi -filetype=obj < %s ; Primarily a non-crash test: Thumbv7 Linux does not have FastISel support, diff --git a/llvm/test/CodeGen/ARM/none-macho.ll b/llvm/test/CodeGen/ARM/none-macho.ll --- a/llvm/test/CodeGen/ARM/none-macho.ll +++ b/llvm/test/CodeGen/ARM/none-macho.ll @@ -1,5 +1,5 @@ ; RUN: llc -mtriple=thumbv7m-none-macho %s -o - -relocation-model=pic -frame-pointer=all | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-NON-FAST -; RUN: llc -mtriple=thumbv7m-none-macho -O0 %s -o - -relocation-model=pic -frame-pointer=all | FileCheck %s +; RUN: llc -mtriple=thumbv7m-none-macho -O0 -disable-add-disable-tail-calls %s -o - -relocation-model=pic -frame-pointer=all | FileCheck %s ; RUN: llc -mtriple=thumbv7m-none-macho -filetype=obj %s -o /dev/null @var = external global i32 diff --git a/llvm/test/CodeGen/ARM/subtarget-no-movt.ll b/llvm/test/CodeGen/ARM/subtarget-no-movt.ll --- a/llvm/test/CodeGen/ARM/subtarget-no-movt.ll +++ b/llvm/test/CodeGen/ARM/subtarget-no-movt.ll @@ -4,11 +4,11 @@ ; RUN: FileCheck -check-prefixes=CHECK,USE-MOVT,USE-MOVT-COMMON %s ; RUN: llc -mcpu=cortex-a8 -relocation-model=static %s -o - -mattr=+no-movt | \ ; RUN: FileCheck -check-prefixes=CHECK,NO-USE-MOVT,NO-USE-MOVT-COMMON %s -; RUN: llc -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 | \ +; RUN: llc -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -disable-add-disable-tail-calls | \ ; RUN: FileCheck -check-prefixes=CHECK,NO-OPTION-O0,NO-OPTION-COMMON %s -; RUN: llc -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -mattr=-no-movt | \ +; RUN: llc -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -disable-add-disable-tail-calls -mattr=-no-movt | \ ; RUN: FileCheck -check-prefixes=CHECK,USE-MOVT-O0,USE-MOVT-COMMON %s -; RUN: llc -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -mattr=+no-movt | \ +; RUN: llc -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -disable-add-disable-tail-calls -mattr=+no-movt | \ ; RUN: FileCheck -check-prefixes=CHECK,NO-USE-MOVT-O0,NO-USE-MOVT-COMMON %s target triple = "thumb-apple-darwin" diff --git a/llvm/test/CodeGen/ARM/tail-call-float.ll b/llvm/test/CodeGen/ARM/tail-call-float.ll --- a/llvm/test/CodeGen/ARM/tail-call-float.ll +++ b/llvm/test/CodeGen/ARM/tail-call-float.ll @@ -1,6 +1,6 @@ -; RUN: llc -mtriple armv7 -target-abi aapcs -float-abi soft -O0 -o - < %s \ +; RUN: llc -mtriple armv7 -target-abi aapcs -float-abi soft -O0 -disable-add-disable-tail-calls -o - < %s \ ; RUN: | FileCheck %s -check-prefix CHECK-SOFT -check-prefix CHECK -; RUN: llc -mtriple armv7 -target-abi aapcs -float-abi hard -O0 -o - < %s \ +; RUN: llc -mtriple armv7 -target-abi aapcs -float-abi hard -O0 -disable-add-disable-tail-calls -o - < %s \ ; RUN: | FileCheck %s -check-prefix CHECK-HARD -check-prefix CHECK ; Tests for passing floating-point regs. Variadic functions will always use diff --git a/llvm/test/CodeGen/ARM/tail-call.ll b/llvm/test/CodeGen/ARM/tail-call.ll --- a/llvm/test/CodeGen/ARM/tail-call.ll +++ b/llvm/test/CodeGen/ARM/tail-call.ll @@ -1,8 +1,8 @@ -; RUN: llc -mtriple armv7 -target-abi apcs -O0 -o - < %s \ +; RUN: llc -mtriple armv7 -target-abi apcs -O0 -disable-add-disable-tail-calls -o - < %s \ ; RUN: | FileCheck %s -check-prefix CHECK-TAIL -check-prefix CHECK -; RUN: llc -mtriple armv7 -target-abi apcs -O0 -disable-tail-calls -o - < %s \ +; RUN: llc -mtriple armv7 -target-abi apcs -O0 -disable-add-disable-tail-calls -disable-tail-calls -o - < %s \ ; RUN: | FileCheck %s -check-prefix CHECK-NO-TAIL -check-prefix CHECK -; RUN: llc -mtriple armv7 -target-abi aapcs -O0 -o - < %s \ +; RUN: llc -mtriple armv7 -target-abi aapcs -O0 -disable-add-disable-tail-calls -o - < %s \ ; RUN: | FileCheck %s -check-prefix CHECK-TAIL-AAPCS -check-prefix CHECK declare i32 @callee(i32 %i) diff --git a/llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll b/llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll --- a/llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll +++ b/llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll @@ -1,8 +1,8 @@ -; RUN: llc -march=mips -mcpu=mips32 -O0 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck \ +; RUN: llc -march=mips -mcpu=mips32 -O0 -disable-add-disable-tail-calls -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck \ ; RUN: %s -check-prefix=MIPS32 -; RUN: llc -march=mips64 -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \ +; RUN: llc -march=mips64 -mcpu=mips64 -O0 -disable-add-disable-tail-calls -relocation-model=pic -target-abi n64 \ ; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=MIPS64 -; RUN: llc -march=mips64 -mcpu=mips64 -O0 -relocation-model=pic -target-abi n32 \ +; RUN: llc -march=mips64 -mcpu=mips64 -O0 -disable-add-disable-tail-calls -relocation-model=pic -target-abi n32 \ ; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=MIPS64 diff --git a/llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll b/llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll --- a/llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll +++ b/llvm/test/CodeGen/PowerPC/ppc64-sibcall.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-SCO -; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-SCO -; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-SCO -; RUN: llc < %s -relocation-model=static -O1 -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -code-model=small | FileCheck %s -check-prefix=SCM +; RUN: llc < %s -relocation-model=static -O1 -disable-add-disable-tail-calls -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK-SCO +; RUN: llc < %s -relocation-model=static -O1 -disable-add-disable-tail-calls -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-SCO +; RUN: llc < %s -relocation-model=static -O1 -disable-add-disable-tail-calls -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-SCO +; RUN: llc < %s -relocation-model=static -O1 -disable-add-disable-tail-calls -disable-ppc-sco=false -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -code-model=small | FileCheck %s -check-prefix=SCM ; No combination of "powerpc64le-unknown-linux-gnu" + "CHECK-SCO", because ; only Power8 (and later) fully support LE. diff --git a/llvm/test/CodeGen/RISCV/O0-pipeline.ll b/llvm/test/CodeGen/RISCV/O0-pipeline.ll --- a/llvm/test/CodeGen/RISCV/O0-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O0-pipeline.ll @@ -31,6 +31,7 @@ ; CHECK-NEXT: Exception handling preparation ; CHECK-NEXT: Safe Stack instrumentation pass ; CHECK-NEXT: Insert stack protectors +; CHECK-NEXT: Add "disable-tail-calls" attribute to functions ; CHECK-NEXT: Module Verifier ; CHECK-NEXT: RISCV DAG->DAG Pattern Instruction Selection ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions diff --git a/llvm/test/CodeGen/X86/O0-pipeline.ll b/llvm/test/CodeGen/X86/O0-pipeline.ll --- a/llvm/test/CodeGen/X86/O0-pipeline.ll +++ b/llvm/test/CodeGen/X86/O0-pipeline.ll @@ -32,6 +32,7 @@ ; CHECK-NEXT: Exception handling preparation ; CHECK-NEXT: Safe Stack instrumentation pass ; CHECK-NEXT: Insert stack protectors +; CHECK-NEXT: Add "disable-tail-calls" attribute to functions ; CHECK-NEXT: Module Verifier ; CHECK-NEXT: X86 DAG->DAG Instruction Selection ; CHECK-NEXT: X86 PIC Global Base Reg Initialization diff --git a/llvm/test/CodeGen/X86/add-disable-tail-calls.ll b/llvm/test/CodeGen/X86/add-disable-tail-calls.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/X86/add-disable-tail-calls.ll @@ -0,0 +1,14 @@ +; RUN: opt -add-disable-tail-calls < %s -mtriple=x86_64-- -S | FileCheck %s --check-prefix=DISABLE +; RUN: llc -O0 -stop-before=finalize-isel < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=DISABLE +; RUN: llc -O1 -stop-before=finalize-isel < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=DISABLE +; RUN: llc -O0 -disable-add-disable-tail-calls -stop-before=finalize-isel < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=IGNORE +; RUN: llc -O1 -disable-add-disable-tail-calls -stop-before=finalize-isel < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=IGNORE +; RUN: llc -O2 -stop-before=finalize-isel < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=IGNORE +; RUN: llc -O3 -stop-before=finalize-isel < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=IGNORE + +define void @f() { + ret void +} + +; IGNORE-NOT: "disable-tail-calls" +; DISABLE: "disable-tail-calls"="true" diff --git a/llvm/test/CodeGen/X86/atom-pad-short-functions.ll b/llvm/test/CodeGen/X86/atom-pad-short-functions.ll --- a/llvm/test/CodeGen/X86/atom-pad-short-functions.ll +++ b/llvm/test/CodeGen/X86/atom-pad-short-functions.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O1 -mcpu=atom -mtriple=i686-linux | FileCheck %s +; RUN: llc < %s -O1 -disable-add-disable-tail-calls -mcpu=atom -mtriple=i686-linux | FileCheck %s declare void @external_function(...) diff --git a/llvm/test/CodeGen/X86/fold-sext-trunc.ll b/llvm/test/CodeGen/X86/fold-sext-trunc.ll --- a/llvm/test/CodeGen/X86/fold-sext-trunc.ll +++ b/llvm/test/CodeGen/X86/fold-sext-trunc.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s -; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -stop-after livedebugvalues -o - | FileCheck %s -check-prefix=MIR +; RUN: llc < %s -O0 -disable-add-disable-tail-calls -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -stop-after livedebugvalues -o - | FileCheck %s -check-prefix=MIR ; PR4050 %0 = type { i64 } diff --git a/llvm/test/CodeGen/X86/fold-zext-trunc.ll b/llvm/test/CodeGen/X86/fold-zext-trunc.ll --- a/llvm/test/CodeGen/X86/fold-zext-trunc.ll +++ b/llvm/test/CodeGen/X86/fold-zext-trunc.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s | FileCheck %s -check-prefix=ASM -; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -stop-after livedebugvalues -o - | FileCheck %s -check-prefix=MIR +; RUN: llc < %s -O0 -disable-add-disable-tail-calls -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -stop-after livedebugvalues -o - | FileCheck %s -check-prefix=MIR ; PR9055 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" target triple = "i686-pc-linux-gnu" diff --git a/llvm/test/CodeGen/X86/ins_split_regalloc.ll b/llvm/test/CodeGen/X86/ins_split_regalloc.ll --- a/llvm/test/CodeGen/X86/ins_split_regalloc.ll +++ b/llvm/test/CodeGen/X86/ins_split_regalloc.ll @@ -1,4 +1,4 @@ -; RUN: llc -O1 -regalloc=greedy -mtriple=x86_64-apple-macosx < %s -o - | FileCheck %s +; RUN: llc -O1 -disable-add-disable-tail-calls -regalloc=greedy -mtriple=x86_64-apple-macosx < %s -o - | FileCheck %s ; Check that last chance split (RAGreedy::tryInstructonSplit) just split ; when this is beneficial, otherwise we end up with uncoalesced copies. ; diff --git a/llvm/test/CodeGen/X86/lvi-hardening-indirectbr.ll b/llvm/test/CodeGen/X86/lvi-hardening-indirectbr.ll --- a/llvm/test/CodeGen/X86/lvi-hardening-indirectbr.ll +++ b/llvm/test/CodeGen/X86/lvi-hardening-indirectbr.ll @@ -1,5 +1,5 @@ ; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown -mattr=+lvi-cfi < %s | FileCheck %s --check-prefix=X64 -; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown -mattr=+lvi-cfi -O0 < %s | FileCheck %s --check-prefix=X64FAST +; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown -mattr=+lvi-cfi -O0 -disable-add-disable-tail-calls < %s | FileCheck %s --check-prefix=X64FAST ; ; Note that a lot of this code was lifted from retpoline.ll. diff --git a/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll b/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll --- a/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll +++ b/llvm/test/CodeGen/X86/mixed-ptr-sizes-i686.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s | FileCheck %s --check-prefixes=ALL,CHECK -; RUN: llc -O0 < %s | FileCheck %s --check-prefixes=ALL,CHECK-O0 +; RUN: llc -O0 -disable-add-disable-tail-calls < %s | FileCheck %s --check-prefixes=ALL,CHECK-O0 ; Source to regenerate: ; struct Foo { diff --git a/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll b/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll --- a/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll +++ b/llvm/test/CodeGen/X86/mixed-ptr-sizes.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s | FileCheck %s --check-prefixes=ALL,CHECK -; RUN: llc -O0 < %s | FileCheck %s --check-prefixes=ALL,CHECK-O0 +; RUN: llc -O0 -disable-add-disable-tail-calls < %s | FileCheck %s --check-prefixes=ALL,CHECK-O0 ; Source to regenerate: ; struct Foo { diff --git a/llvm/test/CodeGen/X86/opt-pipeline.ll b/llvm/test/CodeGen/X86/opt-pipeline.ll --- a/llvm/test/CodeGen/X86/opt-pipeline.ll +++ b/llvm/test/CodeGen/X86/opt-pipeline.ll @@ -1,7 +1,7 @@ ; When EXPENSIVE_CHECKS are enabled, the machine verifier appears between each ; pass. Ignore it with 'grep -v'. ; RUN: llc -mtriple=x86_64-- -O1 -debug-pass=Structure < %s -o /dev/null 2>&1 \ -; RUN: | grep -v 'Verify generated machine code' | FileCheck %s +; RUN: | grep -v 'Verify generated machine code' | FileCheck %s --check-prefixes=CHECK,O1 ; RUN: llc -mtriple=x86_64-- -O2 -debug-pass=Structure < %s -o /dev/null 2>&1 \ ; RUN: | grep -v 'Verify generated machine code' | FileCheck %s ; RUN: llc -mtriple=x86_64-- -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 \ @@ -71,6 +71,7 @@ ; CHECK-NEXT: Exception handling preparation ; CHECK-NEXT: Safe Stack instrumentation pass ; CHECK-NEXT: Insert stack protectors +; O1-NEXT: Add "disable-tail-calls" attribute to functions ; CHECK-NEXT: Module Verifier ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) ; CHECK-NEXT: Function Alias Analysis Results diff --git a/llvm/test/CodeGen/X86/pr1489.ll b/llvm/test/CodeGen/X86/pr1489.ll --- a/llvm/test/CodeGen/X86/pr1489.ll +++ b/llvm/test/CodeGen/X86/pr1489.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -frame-pointer=all -O0 -mcpu=i486 | FileCheck %s +; RUN: llc < %s -frame-pointer=all -O0 -disable-add-disable-tail-calls -mcpu=i486 | FileCheck %s ;; magic constants are 3.999f and half of 3.999 ; ModuleID = '1489.c' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" diff --git a/llvm/test/CodeGen/X86/pr53243-tail-call-fastisel.ll b/llvm/test/CodeGen/X86/pr53243-tail-call-fastisel.ll --- a/llvm/test/CodeGen/X86/pr53243-tail-call-fastisel.ll +++ b/llvm/test/CodeGen/X86/pr53243-tail-call-fastisel.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -O0 -fast-isel -mtriple=x86_64-- < %s | FileCheck %s +; RUN: llc -O0 -disable-add-disable-tail-calls -fast-isel -mtriple=x86_64-- < %s | FileCheck %s define void @test() { ; CHECK-LABEL: test: diff --git a/llvm/test/CodeGen/X86/retpoline-external.ll b/llvm/test/CodeGen/X86/retpoline-external.ll --- a/llvm/test/CodeGen/X86/retpoline-external.ll +++ b/llvm/test/CodeGen/X86/retpoline-external.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown < %s | FileCheck %s --implicit-check-not="jmp.*\*" --implicit-check-not="call.*\*" --check-prefix=X64 -; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown -O0 < %s | FileCheck %s --implicit-check-not="jmp.*\*" --implicit-check-not="call.*\*" --check-prefix=X64FAST +; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown -O0 -disable-add-disable-tail-calls < %s | FileCheck %s --implicit-check-not="jmp.*\*" --implicit-check-not="call.*\*" --check-prefix=X64FAST ; RUN: llc -verify-machineinstrs -mtriple=i686-unknown < %s | FileCheck %s --implicit-check-not="jmp.*\*" --implicit-check-not="call.*\*" --check-prefix=X86 -; RUN: llc -verify-machineinstrs -mtriple=i686-unknown -O0 < %s | FileCheck %s --implicit-check-not="jmp.*\*" --implicit-check-not="call.*\*" --check-prefix=X86FAST +; RUN: llc -verify-machineinstrs -mtriple=i686-unknown -O0 -disable-add-disable-tail-calls < %s | FileCheck %s --implicit-check-not="jmp.*\*" --implicit-check-not="call.*\*" --check-prefix=X86FAST declare dso_local void @bar(i32) diff --git a/llvm/test/CodeGen/X86/retpoline.ll b/llvm/test/CodeGen/X86/retpoline.ll --- a/llvm/test/CodeGen/X86/retpoline.ll +++ b/llvm/test/CodeGen/X86/retpoline.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown < %s | FileCheck %s --implicit-check-not="jmp.*\*" --implicit-check-not="call.*\*" --check-prefix=X64 -; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown -O0 < %s | FileCheck %s --implicit-check-not="jmp.*\*" --implicit-check-not="call.*\*" --check-prefix=X64FAST +; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown -O0 -disable-add-disable-tail-calls < %s | FileCheck %s --implicit-check-not="jmp.*\*" --implicit-check-not="call.*\*" --check-prefix=X64FAST ; RUN: llc -verify-machineinstrs -mtriple=i686-unknown < %s | FileCheck %s --implicit-check-not="jmp.*\*" --implicit-check-not="call.*\*" --check-prefix=X86 -; RUN: llc -verify-machineinstrs -mtriple=i686-unknown -O0 < %s | FileCheck %s --implicit-check-not="jmp.*\*" --implicit-check-not="call.*\*" --check-prefix=X86FAST +; RUN: llc -verify-machineinstrs -mtriple=i686-unknown -O0 -disable-add-disable-tail-calls < %s | FileCheck %s --implicit-check-not="jmp.*\*" --implicit-check-not="call.*\*" --check-prefix=X86FAST declare void @bar(i32) diff --git a/llvm/test/CodeGen/X86/swiftself-win64.ll b/llvm/test/CodeGen/X86/swiftself-win64.ll --- a/llvm/test/CodeGen/X86/swiftself-win64.ll +++ b/llvm/test/CodeGen/X86/swiftself-win64.ll @@ -1,5 +1,5 @@ ; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown-windows-msvc -o - %s | FileCheck --check-prefix=CHECK --check-prefix=OPT %s -; RUN: llc -O0 -verify-machineinstrs -mtriple=x86_64-unknown-windows-msvc -o - %s | FileCheck %s +; RUN: llc -O0 -disable-add-disable-tail-calls -verify-machineinstrs -mtriple=x86_64-unknown-windows-msvc -o - %s | FileCheck %s ; Parameter with swiftself should be allocated to r13. ; CHECK-LABEL: swiftself_param: diff --git a/llvm/test/CodeGen/X86/swiftself.ll b/llvm/test/CodeGen/X86/swiftself.ll --- a/llvm/test/CodeGen/X86/swiftself.ll +++ b/llvm/test/CodeGen/X86/swiftself.ll @@ -1,5 +1,5 @@ ; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown-unknown -o - %s | FileCheck --check-prefix=CHECK --check-prefix=OPT %s -; RUN: llc -O0 -verify-machineinstrs -mtriple=x86_64-unknown-unknown -o - %s | FileCheck %s +; RUN: llc -O0 -disable-add-disable-tail-calls -verify-machineinstrs -mtriple=x86_64-unknown-unknown -o - %s | FileCheck %s ; Parameter with swiftself should be allocated to r13. ; CHECK-LABEL: swiftself_param: diff --git a/llvm/test/CodeGen/X86/tailcall-msvc-conventions.ll b/llvm/test/CodeGen/X86/tailcall-msvc-conventions.ll --- a/llvm/test/CodeGen/X86/tailcall-msvc-conventions.ll +++ b/llvm/test/CodeGen/X86/tailcall-msvc-conventions.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=i686-unknown-linux-gnu -O1 < %s | FileCheck %s -; RUN: llc -mtriple=i686-unknown-linux-gnu -O0 < %s | FileCheck %s +; RUN: llc -mtriple=i686-unknown-linux-gnu -O1 -disable-add-disable-tail-calls < %s | FileCheck %s +; RUN: llc -mtriple=i686-unknown-linux-gnu -O0 -disable-add-disable-tail-calls < %s | FileCheck %s ; The MSVC family of x86 calling conventions makes tail calls really tricky. ; Tests of all the various combinations should live here. diff --git a/llvm/test/CodeGen/X86/win64_eh_leaf.ll b/llvm/test/CodeGen/X86/win64_eh_leaf.ll --- a/llvm/test/CodeGen/X86/win64_eh_leaf.ll +++ b/llvm/test/CodeGen/X86/win64_eh_leaf.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -O1 -mtriple=x86_64-pc-win32 | FileCheck %s -check-prefix=ASM -; RUN: llc < %s -O1 -mtriple=x86_64-pc-win32 -filetype=obj -o %t +; RUN: llc < %s -O1 -disable-add-disable-tail-calls -mtriple=x86_64-pc-win32 | FileCheck %s -check-prefix=ASM +; RUN: llc < %s -O1 -disable-add-disable-tail-calls -mtriple=x86_64-pc-win32 -filetype=obj -o %t ; RUN: llvm-readobj --unwind %t | FileCheck %s -check-prefix=READOBJ declare void @g(i32) diff --git a/llvm/test/DebugInfo/COFF/tail-call-without-lexical-scopes.ll b/llvm/test/DebugInfo/COFF/tail-call-without-lexical-scopes.ll --- a/llvm/test/DebugInfo/COFF/tail-call-without-lexical-scopes.ll +++ b/llvm/test/DebugInfo/COFF/tail-call-without-lexical-scopes.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=core2 -mtriple=i686-pc-win32 -O0 < %s | FileCheck --check-prefix=X86 %s +; RUN: llc -mcpu=core2 -mtriple=i686-pc-win32 -O0 -disable-add-disable-tail-calls < %s | FileCheck --check-prefix=X86 %s ; This LL file was generated by running clang on the following code: ; D:\test.cpp: diff --git a/llvm/test/DebugInfo/X86/dbg-declare-inalloca.ll b/llvm/test/DebugInfo/X86/dbg-declare-inalloca.ll --- a/llvm/test/DebugInfo/X86/dbg-declare-inalloca.ll +++ b/llvm/test/DebugInfo/X86/dbg-declare-inalloca.ll @@ -1,6 +1,6 @@ -; RUN: llc -O0 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=DEBUG +; RUN: llc -O0 -disable-add-disable-tail-calls < %s | FileCheck %s --check-prefix=CHECK --check-prefix=DEBUG ; RUN: llc < %s | FileCheck %s -; RUN: llc -filetype=obj -O0 < %s | llvm-readobj --codeview - | FileCheck %s --check-prefix=OBJ +; RUN: llc -filetype=obj -O0 -disable-add-disable-tail-calls < %s | llvm-readobj --codeview - | FileCheck %s --check-prefix=OBJ ; IR generated by the following source: ; struct NonTrivial { diff --git a/llvm/test/MC/ARM/arm-thumb-tail-call.ll b/llvm/test/MC/ARM/arm-thumb-tail-call.ll --- a/llvm/test/MC/ARM/arm-thumb-tail-call.ll +++ b/llvm/test/MC/ARM/arm-thumb-tail-call.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 < %s -mtriple armv7-linux-gnueabi -o - \ +; RUN: llc -O0 -disable-add-disable-tail-calls < %s -mtriple armv7-linux-gnueabi -o - \ ; RUN: | llvm-mc -triple armv7-linux-gnueabi -filetype=obj -o - \ ; RUN: | llvm-readobj -r - | FileCheck %s diff --git a/llvm/tools/opt/opt.cpp b/llvm/tools/opt/opt.cpp --- a/llvm/tools/opt/opt.cpp +++ b/llvm/tools/opt/opt.cpp @@ -455,7 +455,7 @@ "replace-with-veclib", "jmc-instrument", "dot-regions", "dot-regions-only", "view-regions", "view-regions-only", - "select-optimize"}; + "select-optimize", "add-disable-tail-calls"}; for (const auto &P : PassNamePrefix) if (Pass.startswith(P)) return true; @@ -504,6 +504,7 @@ initializeTarget(Registry); // For codegen passes, only passes that do IR to IR transformation are // supported. + initializeAddDisableTailCallsPassPass(Registry); initializeExpandMemCmpPassPass(Registry); initializeScalarizeMaskedMemIntrinLegacyPassPass(Registry); initializeSelectOptimizePass(Registry); diff --git a/llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn --- a/llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn @@ -17,6 +17,7 @@ "//llvm/lib/Transforms/Utils", ] sources = [ + "AddDisableTailCalls.cpp", "AggressiveAntiDepBreaker.cpp", "AllocationOrder.cpp", "Analysis.cpp",