diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp
--- a/llvm/lib/MC/MCAsmStreamer.cpp
+++ b/llvm/lib/MC/MCAsmStreamer.cpp
@@ -1428,13 +1428,15 @@
 
     OS << Log2_32(ByteAlignment);
 
-    if (Value || MaxBytesToEmit) {
+    if (Value) {
       OS << ", 0x";
       OS.write_hex(truncateToSize(Value, ValueSize));
-
-      if (MaxBytesToEmit)
-        OS << ", " << MaxBytesToEmit;
+    } else if (MaxBytesToEmit) {
+      OS << ", ";
     }
+
+    if (MaxBytesToEmit)
+      OS << ", " << MaxBytesToEmit;
     EmitEOL();
     return;
   }
diff --git a/llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes-neoverse.ll b/llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes-neoverse.ll
--- a/llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes-neoverse.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes-neoverse.ll
@@ -14,12 +14,12 @@
 
 define i32 @a(i32 %x, i32* nocapture readonly %y, i32* nocapture readonly %z) {
 ; CHECK-DEFAULT:    .p2align 5
-; CHECK-8:          .p2align 4, 0x0, 8
-; CHECK-16:         .p2align 5, 0x0, 16
+; CHECK-8:          .p2align 4, , 8
+; CHECK-16:         .p2align 5, , 16
 ; CHECK-NEXT:       .LBB0_5: // %vector.body
 ; CHECK-DEFAULT:    .p2align 5
-; CHECK-8:          .p2align 4, 0x0, 8
-; CHECK-16:         .p2align 5, 0x0, 16
+; CHECK-8:          .p2align 4, , 8
+; CHECK-16:         .p2align 5, , 16
 ; CHECK-NEXT:       .LBB0_8: // %for.body
 entry:
   %cmp10 = icmp sgt i32 %x, 0
diff --git a/llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes.ll b/llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes.ll
--- a/llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes.ll
@@ -9,10 +9,10 @@
 ; should be the same, at different locations)
 define i32 @a(i32 %x, i32* nocapture readonly %y, i32* nocapture readonly %z) {
 ; CHECK-LABEL: a:
-; CHECK-EXPLICIT:    .p2align 5, 0x0, 8
+; CHECK-EXPLICIT:    .p2align 5, , 8
 ; CHECK-IMPLICIT:    .p2align 5
 ; CHECK-NEXT:  .LBB0_5: // %vector.body
-; CHECK-EXPLICIT:    .p2align 5, 0x0, 8
+; CHECK-EXPLICIT:    .p2align 5, , 8
 ; CHECK-IMPLICIT:    .p2align 5
 ; CHECK-NEXT:  .LBB0_8: // %for.body
 ; CHECK-OBJ;Disassembly of section .text:
diff --git a/llvm/test/CodeGen/AArch64/aarch64-sched-store.ll b/llvm/test/CodeGen/AArch64/aarch64-sched-store.ll
--- a/llvm/test/CodeGen/AArch64/aarch64-sched-store.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-sched-store.ll
@@ -9,7 +9,7 @@
 ; DEFAULT:       // %bb.0: // %entry
 ; DEFAULT-NEXT:    fmov v0.2d, #2.00000000
 ; DEFAULT-NEXT:    add x8, x0, #64
-; DEFAULT-NEXT:    .p2align 4, 0x0, 8
+; DEFAULT-NEXT:    .p2align 4, , 8
 ; DEFAULT-NEXT:  .LBB0_1: // %vector.body
 ; DEFAULT-NEXT:    // =>This Inner Loop Header: Depth=1
 ; DEFAULT-NEXT:    stur q0, [x8, #-64]
@@ -30,7 +30,7 @@
 ; ASCEND:       // %bb.0: // %entry
 ; ASCEND-NEXT:    fmov v0.2d, #2.00000000
 ; ASCEND-NEXT:    add x8, x0, #64
-; ASCEND-NEXT:    .p2align 4, 0x0, 8
+; ASCEND-NEXT:    .p2align 4, , 8
 ; ASCEND-NEXT:  .LBB0_1: // %vector.body
 ; ASCEND-NEXT:    // =>This Inner Loop Header: Depth=1
 ; ASCEND-NEXT:    stur q0, [x8, #-64]
diff --git a/llvm/test/CodeGen/AArch64/merge-store-dependency.ll b/llvm/test/CodeGen/AArch64/merge-store-dependency.ll
--- a/llvm/test/CodeGen/AArch64/merge-store-dependency.ll
+++ b/llvm/test/CodeGen/AArch64/merge-store-dependency.ll
@@ -36,7 +36,7 @@
 ; A53-NEXT:  // %bb.1:
 ; A53-NEXT:    ldr w8, [x19]
 ; A53-NEXT:    ldr w9, [x9]
-; A53-NEXT:    .p2align 4, 0x0, 8
+; A53-NEXT:    .p2align 4, , 8
 ; A53-NEXT:  .LBB0_2: // %while.body.i.split.ver.us
 ; A53-NEXT:    // =>This Inner Loop Header: Depth=1
 ; A53-NEXT:    lsl w9, w9, #1
@@ -51,7 +51,7 @@
 ; A53-NEXT:    .cfi_restore w19
 ; A53-NEXT:    .cfi_restore w30
 ; A53-NEXT:    ret
-; A53-NEXT:    .p2align 4, 0x0, 8
+; A53-NEXT:    .p2align 4, , 8
 ; A53-NEXT:  .LBB0_4: // %while.body.i.split
 ; A53-NEXT:    // =>This Inner Loop Header: Depth=1
 ; A53-NEXT:    .cfi_restore_state
diff --git a/llvm/test/MC/AsmParser/directive_align.s b/llvm/test/MC/AsmParser/directive_align.s
--- a/llvm/test/MC/AsmParser/directive_align.s
+++ b/llvm/test/MC/AsmParser/directive_align.s
@@ -7,7 +7,7 @@
         .align 1
 
 # CHECK: TEST1:
-# CHECK: .p2alignl 3, 0x0, 2
+# CHECK: .p2alignl 3, , 2
 TEST1:  
         .align32 3,,2