Index: llvm/test/TableGen/CompressWriteLatencyEntry.td
===================================================================
--- llvm/test/TableGen/CompressWriteLatencyEntry.td
+++ llvm/test/TableGen/CompressWriteLatencyEntry.td
@@ -21,7 +21,8 @@
 
 // CHECK:        MyTargetWriteLatencyTable[] = {
 // CHECK-NEXT:     { 0,  0}, // Invalid
-// CHECK-NEXT:     { 1,  0} // #1 Write_A_Write_B_Write_C
+// CHECK-NEXT:     { 1,  0}, // #1 Write_A_Write_C
+// CHECK-NEXT:     { 1,  2} // #2 Write_B
 // CHECK-NEXT:   }; // MyTargetWriteLatencyTable
 
 let SchedModel = SchedModel_A in {
Index: llvm/utils/TableGen/CodeGenSchedule.cpp
===================================================================
--- llvm/utils/TableGen/CodeGenSchedule.cpp
+++ llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -734,14 +734,12 @@
 }
 
 bool CodeGenSchedModels::hasReadOfWrite(Record *WriteDef) const {
-  for (const CodeGenSchedRW &Read : SchedReads) {
-    Record *ReadDef = Read.TheDef;
-    if (!ReadDef || !ReadDef->isSubClassOf("ProcReadAdvance"))
-      continue;
-
-    RecVec ValidWrites = ReadDef->getValueAsListOfDefs("ValidWrites");
-    if (is_contained(ValidWrites, WriteDef)) {
-      return true;
+  for (auto& ProcModel : ProcModels) {
+    const RecVec &RADefs = ProcModel.ReadAdvanceDefs;
+    for (auto& RADef : RADefs) {
+      RecVec ValidWrites = RADef->getValueAsListOfDefs("ValidWrites");
+      if (is_contained(ValidWrites, WriteDef))
+        return true;
     }
   }
   return false;