diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -3720,7 +3720,7 @@
   }
 
   // canonicalize (sub X, (vscale * C)) to (add X, (vscale * -C))
-  if (N1.getOpcode() == ISD::VSCALE) {
+  if (N1.getOpcode() == ISD::VSCALE && N1.hasOneUse()) {
     const APInt &IntVal = N1.getConstantOperandAPInt(0);
     return DAG.getNode(ISD::ADD, DL, VT, N0, DAG.getVScale(DL, VT, -IntVal));
   }
diff --git a/llvm/test/CodeGen/AArch64/sve-vscale-combine.ll b/llvm/test/CodeGen/AArch64/sve-vscale-combine.ll
--- a/llvm/test/CodeGen/AArch64/sve-vscale-combine.ll
+++ b/llvm/test/CodeGen/AArch64/sve-vscale-combine.ll
@@ -76,10 +76,8 @@
 define i64 @multiple_uses_sub_vscale_i64(i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: multiple_uses_sub_vscale_i64:
 ; CHECK-NEXT:  rdvl	x8, #1
-; CHECK-NEXT:  rdvl	x9, #-1
 ; CHECK-NEXT:  lsr	x8, x8, #4
-; CHECK-NEXT:  asr	x9, x9, #4
-; CHECK-NEXT:  add	x9, x0, x9
+; CHECK-NEXT:  sub	x9, x0, x8
 ; CHECK-NEXT:  add	x8, x1, x8
 ; CHECK-NEXT:  mul	x0, x9, x8
 ; CHECK-NEXT:  ret