diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -567,7 +567,7 @@ : DefaultAttrsIntrinsic<[], [ llvm_anyptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty ], [IntrInaccessibleMemOrArgMemOnly, IntrWillReturn, ReadOnly>, NoCapture>, - ImmArg>, ImmArg>]>; + ImmArg>, ImmArg>, ImmArg>]>; def int_pcmarker : DefaultAttrsIntrinsic<[], [llvm_i32_ty]>; def int_readcyclecounter : DefaultAttrsIntrinsic<[llvm_i64_ty]>; diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -5121,9 +5121,12 @@ Call); break; case Intrinsic::prefetch: - Check(cast(Call.getArgOperand(1))->getZExtValue() < 2 && - cast(Call.getArgOperand(2))->getZExtValue() < 4, - "invalid arguments to llvm.prefetch", Call); + Check(cast(Call.getArgOperand(1))->getZExtValue() < 2, + "rw argument to llvm.prefetch must be 0-1", Call); + Check(cast(Call.getArgOperand(2))->getZExtValue() < 4, + "locality argument to llvm.prefetch must be 0-4", Call); + Check(cast(Call.getArgOperand(3))->getZExtValue() < 2, + "cache type argument to llvm.prefetch must be 0-1", Call); break; case Intrinsic::stackprotector: Check(isa(Call.getArgOperand(1)->stripPointerCasts()), diff --git a/llvm/test/Assembler/auto_upgrade_intrinsics.ll b/llvm/test/Assembler/auto_upgrade_intrinsics.ll --- a/llvm/test/Assembler/auto_upgrade_intrinsics.ll +++ b/llvm/test/Assembler/auto_upgrade_intrinsics.ll @@ -189,24 +189,24 @@ declare void @llvm.prefetch(i8*, i32, i32, i32) define void @test.prefetch(i8* %ptr) { ; CHECK-LABEL: @test.prefetch( -; CHECK: @llvm.prefetch.p0i8(i8* %ptr, i32 0, i32 3, i32 2) - call void @llvm.prefetch(i8* %ptr, i32 0, i32 3, i32 2) +; CHECK: @llvm.prefetch.p0i8(i8* %ptr, i32 0, i32 3, i32 1) + call void @llvm.prefetch(i8* %ptr, i32 0, i32 3, i32 1) ret void } declare void @llvm.prefetch.p0i8(i8*, i32, i32, i32) define void @test.prefetch.2(i8* %ptr) { ; CHECK-LABEL: @test.prefetch.2( -; CHECK: @llvm.prefetch.p0i8(i8* %ptr, i32 0, i32 3, i32 2) - call void @llvm.prefetch(i8* %ptr, i32 0, i32 3, i32 2) +; CHECK: @llvm.prefetch.p0i8(i8* %ptr, i32 0, i32 3, i32 1) + call void @llvm.prefetch(i8* %ptr, i32 0, i32 3, i32 1) ret void } declare void @llvm.prefetch.unnamed(%0**, i32, i32, i32) define void @test.prefetch.unnamed(%0** %ptr) { ; CHECK-LABEL: @test.prefetch.unnamed( -; CHECK: @llvm.prefetch.p0p0s_s.0(%0** %ptr, i32 0, i32 3, i32 2) - call void @llvm.prefetch.unnamed(%0** %ptr, i32 0, i32 3, i32 2) +; CHECK: @llvm.prefetch.p0p0s_s.0(%0** %ptr, i32 0, i32 3, i32 1) + call void @llvm.prefetch.unnamed(%0** %ptr, i32 0, i32 3, i32 1) ret void } diff --git a/llvm/test/CodeGen/RISCV/prefetch.ll b/llvm/test/CodeGen/RISCV/prefetch.ll --- a/llvm/test/CodeGen/RISCV/prefetch.ll +++ b/llvm/test/CodeGen/RISCV/prefetch.ll @@ -14,6 +14,6 @@ ; RV64I-LABEL: test_prefetch: ; RV64I: # %bb.0: ; RV64I-NEXT: ret - call void @llvm.prefetch(i8* %a, i32 0, i32 1, i32 2) + call void @llvm.prefetch(i8* %a, i32 0, i32 2, i32 1) ret void } diff --git a/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir b/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir --- a/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir +++ b/mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir @@ -712,7 +712,7 @@ // CHECK-DAG: declare <8 x float> @llvm.fma.v8f32(<8 x float>, <8 x float>, <8 x float>) #0 // CHECK-DAG: declare float @llvm.fmuladd.f32(float, float, float) // CHECK-DAG: declare <8 x float> @llvm.fmuladd.v8f32(<8 x float>, <8 x float>, <8 x float>) #0 -// CHECK-DAG: declare void @llvm.prefetch.p0(ptr nocapture readonly, i32 immarg, i32 immarg, i32) +// CHECK-DAG: declare void @llvm.prefetch.p0(ptr nocapture readonly, i32 immarg, i32 immarg, i32 immarg) // CHECK-DAG: declare float @llvm.exp.f32(float) // CHECK-DAG: declare <8 x float> @llvm.exp.v8f32(<8 x float>) #0 // CHECK-DAG: declare float @llvm.log.f32(float)