diff --git a/llvm/test/CodeGen/AArch64/avoid-zero-copy.mir b/llvm/test/CodeGen/AArch64/avoid-zero-copy.mir
--- a/llvm/test/CodeGen/AArch64/avoid-zero-copy.mir
+++ b/llvm/test/CodeGen/AArch64/avoid-zero-copy.mir
@@ -7,12 +7,11 @@
   define i32 @foo() nounwind {
   ; ASM-LABEL: foo:
   ; ASM:       // %bb.0:
-  ; ASM-NEXT:    stp x30, x19, [sp, #-16]! // 16-byte Folded Spill
+  ; ASM-NEXT:    str x30, [sp, #-16]! // 8-byte Folded Spill
   ; ASM-NEXT:    mov w0, wzr
-  ; ASM-NEXT:    mov w19, wzr
   ; ASM-NEXT:    bl bar
-  ; ASM-NEXT:    mov w0, w19
-  ; ASM-NEXT:    ldp x30, x19, [sp], #16 // 16-byte Folded Reload
+  ; ASM-NEXT:    mov w0, wzr
+  ; ASM-NEXT:    ldr x30, [sp], #16 // 8-byte Folded Reload
   ; ASM-NEXT:    ret
     call i32 @bar(i32 0)
     ret i32 0
@@ -24,11 +23,10 @@
   bb.0 (%ir-block.0):
     ; CHECK-LABEL: name: foo
     ; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
-    ; CHECK-NEXT: renamable $w19 = COPY $wzr
     ; CHECK-NEXT: $w0 = COPY $wzr
     ; CHECK-NEXT: BL @bar, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
     ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
-    ; CHECK-NEXT: $w0 = COPY killed renamable $w19
+    ; CHECK-NEXT: $w0 = COPY $wzr
     ; CHECK-NEXT: RET_ReallyLR implicit $w0
     ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
     renamable $w19 = COPY $wzr
diff --git a/llvm/test/CodeGen/Mips/avoid-zero-copy.mir b/llvm/test/CodeGen/Mips/avoid-zero-copy.mir
--- a/llvm/test/CodeGen/Mips/avoid-zero-copy.mir
+++ b/llvm/test/CodeGen/Mips/avoid-zero-copy.mir
@@ -8,12 +8,9 @@
   ; ASM:       # %bb.0:
   ; ASM-NEXT:    daddiu $sp, $sp, -16
   ; ASM-NEXT:    sd $ra, 8($sp) # 8-byte Folded Spill
-  ; ASM-NEXT:    sd $16, 0($sp) # 8-byte Folded Spill
-  ; ASM-NEXT:    move $16, $zero
   ; ASM-NEXT:    jalr $25
   ; ASM-NEXT:    move $4, $zero
-  ; ASM-NEXT:    move $4, $16
-  ; ASM-NEXT:    ld $16, 0($sp) # 8-byte Folded Reload
+  ; ASM-NEXT:    move $4, $zero
   ; ASM-NEXT:    ld $ra, 8($sp) # 8-byte Folded Reload
   ; ASM-NEXT:    jr $ra
   ; ASM-NEXT:    daddiu $sp, $sp, 16
@@ -29,11 +26,10 @@
     ; CHECK: liveins: $a0_64, $t9_64, $ra_64, $fp_64, $gp_64
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
-    ; CHECK-NEXT: renamable $s0_64 = COPY $zero_64
     ; CHECK-NEXT: $a0_64 = COPY $zero_64
     ; CHECK-NEXT: JALR64Pseudo $t9_64, csr_n64, implicit-def dead $ra, implicit $a0_64, implicit $gp_64, implicit-def $sp, implicit-def $v0
     ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
-    ; CHECK-NEXT: $a0_64 = COPY killed renamable $s0_64
+    ; CHECK-NEXT: $a0_64 = COPY $zero_64
     ; CHECK-NEXT: PseudoReturn64 undef $ra_64, implicit $v0_64, implicit killed $a0_64
     ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
     renamable $s0_64 = COPY $zero_64
diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll
--- a/llvm/test/CodeGen/RISCV/double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/double-convert.ll
@@ -639,7 +639,7 @@
 ; RV32I-NEXT:    mv a1, s0
 ; RV32I-NEXT:    call __fixdfdi@plt
 ; RV32I-NEXT:    mv s5, a1
-; RV32I-NEXT:    mv a1, s2
+; RV32I-NEXT:    li a1, 0
 ; RV32I-NEXT:    bltz s6, .LBB12_2
 ; RV32I-NEXT:  # %bb.1: # %start
 ; RV32I-NEXT:    mv a1, a0
@@ -1425,7 +1425,7 @@
 ; RV32I-NEXT:    lui a3, 790016
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s1
-; RV32I-NEXT:    mv a2, s0
+; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    mv a0, s2
@@ -1738,7 +1738,7 @@
 ; RV32I-NEXT:    lui a3, 787968
 ; RV32I-NEXT:    mv a0, s2
 ; RV32I-NEXT:    mv a1, s1
-; RV32I-NEXT:    mv a2, s0
+; RV32I-NEXT:    li a2, 0
 ; RV32I-NEXT:    call __gedf2@plt
 ; RV32I-NEXT:    mv s4, a0
 ; RV32I-NEXT:    mv a0, s2
diff --git a/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
--- a/llvm/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterInfoEmitter.cpp
@@ -1615,6 +1615,15 @@
         ArrayRef<Record*>(OPSet.begin(), OPSet.end()));
     }
 
+    // Add all constant physical registers to the preserved mask:
+    SetTheory::RecSet ConstantSet;
+    for (auto &Reg : RegBank.getRegisters()) {
+      if (Reg.Constant)
+        ConstantSet.insert(Reg.TheDef);
+    }
+    Covered |= RegBank.computeCoveredRegisters(
+        ArrayRef<Record *>(ConstantSet.begin(), ConstantSet.end()));
+
     OS << "static const uint32_t " << CSRSet->getName()
        << "_RegMask[] = { ";
     printBitVectorAsHex(OS, Covered, 32);