diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -35,6 +35,7 @@
 #include "llvm/IR/IntrinsicsR600.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/KnownBits.h"
+#include "llvm/Support/TargetParser.h"
 
 using namespace llvm;
 
@@ -7821,10 +7822,17 @@
     };
     unsigned Opcode = 0;
     switch (IntrID) {
-    case Intrinsic::amdgcn_global_atomic_fadd:
-      if (!Subtarget->hasAtomicFaddNoRtnInsts())
+    case Intrinsic::amdgcn_global_atomic_fadd: {
+      auto IV = AMDGPU::getIsaVersion(Subtarget->getCPU());
+      auto IVTupl = std::make_tuple(IV.Major, IV.Minor, IV.Stepping);
+      using TuplTy = decltype(IVTupl);
+      // Emit `v_illegal` if ISA version is between gfx908 and gfx940
+      // (inclusive), or if ISA version is gfx11 or above.
+      if ((IVTupl < TuplTy(9u, 0u, 8u)) ||
+          (IVTupl > TuplTy(9u, 4u, 0u) && IVTupl < TuplTy(11u, 0u, 0u)))
         return makeV_ILLEGAL(Op, DAG);
       [[fallthrough]];
+    }
     case Intrinsic::amdgcn_flat_atomic_fadd: {
       EVT VT = Op.getOperand(3).getValueType();
       return DAG.getAtomic(ISD::ATOMIC_LOAD_FADD, DL, VT,
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.fadd.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.fadd.ll
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.fadd.ll
@@ -93,7 +93,8 @@
 ; Make sure this artificially selects with an incorrect subtarget, but
 ; the feature set.
 ; GCN-LABEL: {{^}}global_atomic_fadd_f32_wrong_subtarget:
-; GCN: global_atomic_add_f32 v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]$}}
+; GCN-NOT: global_atomic_add_f32
+; GCN: v_illegal
 define amdgpu_kernel void @global_atomic_fadd_f32_wrong_subtarget(float addrspace(1)* %ptr, float %data) #0 {
   %ret = call float @llvm.amdgcn.global.atomic.fadd.f32.p1f32.f32(float addrspace(1)* %ptr, float %data)
   ret void