Index: include/llvm/MC/MCTargetMachine.h =================================================================== --- /dev/null +++ include/llvm/MC/MCTargetMachine.h @@ -0,0 +1,43 @@ +//===-- llvm/MC/MCTargetMachine.h - Target Information ----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the MCTargetMachine classes. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_MC_MCTARGETMACHINE_H +#define LLVM_MC_MCTARGETMACHINE_H + +namespace llvm { +class Target; +class Triple; + +//===----------------------------------------------------------------------===// +/// +/// Primary interface to the complete machine description for the target +/// machine. All target-specific information should be accessible through this +/// interface. +/// +class MCTargetMachine { + MCTargetMachine(const MCTargetMachine &) = delete; + void operator=(const MCTargetMachine &) = delete; + +protected: + /// The Target that this machine was created for. + const Target &TheTarget; + +public: + MCTargetMachine(const Target &T, const Triple &); + + const Target &getTarget() const { return TheTarget; } +}; + +} // End llvm namespace + +#endif Index: include/llvm/Support/TargetRegistry.h =================================================================== --- include/llvm/Support/TargetRegistry.h +++ include/llvm/Support/TargetRegistry.h @@ -45,6 +45,7 @@ class MCSymbolizer; class MCRelocationInfo; class MCTargetAsmParser; +class MCTargetMachine; class MCTargetOptions; class MCTargetStreamer; class TargetMachine; @@ -91,7 +92,7 @@ typedef bool (*ArchMatchFnTy)(Triple::ArchType Arch); typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const MCRegisterInfo &MRI, - const Triple &TT); + const MCTargetMachine &MCTM); typedef MCCodeGenInfo *(*MCCodeGenInfoCtorFnTy)(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, @@ -106,6 +107,8 @@ const Target &T, const Triple &TT, StringRef CPU, StringRef Features, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL); + typedef MCTargetMachine *(*MCTargetMachineCtorTy)(const Target &T, + const Triple &TT); // If it weren't for layering issues (this header is in llvm/Support, but // depends on MC?) this should take the Streamer by value rather than rvalue // reference. @@ -200,6 +203,10 @@ /// TargetMachine, if registered. TargetMachineCtorTy TargetMachineCtorFn; + /// MCTargetMachineCtorFn - Construction function for this target's + /// MCTargetMachine, if registered. + MCTargetMachineCtorTy MCTargetMachineCtorFn; + /// MCAsmBackendCtorFn - Construction function for this target's /// MCAsmBackend, if registered. MCAsmBackendCtorTy MCAsmBackendCtorFn; @@ -278,6 +285,9 @@ /// hasTargetMachine - Check if this target supports code generation. bool hasTargetMachine() const { return TargetMachineCtorFn != nullptr; } + /// hasMCTargetMachine - Check if this target supports machine code. + bool hasMCTargetMachine() const { return MCTargetMachineCtorFn != nullptr; } + /// hasMCAsmBackend - Check if this target supports .o generation. bool hasMCAsmBackend() const { return MCAsmBackendCtorFn != nullptr; } @@ -287,16 +297,11 @@ /// createMCAsmInfo - Create a MCAsmInfo implementation for the specified /// target triple. - /// - /// \param TheTriple This argument is used to determine the target machine - /// feature set; it should always be provided. Generally this should be - /// either the target triple from the module, or the target triple of the - /// host if that does not exist. MCAsmInfo *createMCAsmInfo(const MCRegisterInfo &MRI, - StringRef TheTriple) const { + const MCTargetMachine &MCTM) const { if (!MCAsmInfoCtorFn) return nullptr; - return MCAsmInfoCtorFn(MRI, Triple(TheTriple)); + return MCAsmInfoCtorFn(MRI, MCTM); } /// createMCCodeGenInfo - Create a MCCodeGenInfo implementation. @@ -368,6 +373,19 @@ CM, OL); } + /// createMCTargetMachine - Create a target specific machine implementation + /// for the specified \p Triple. + /// + /// \param TT This argument is used to determine the target machine + /// feature set; it should always be provided. Generally this should be + /// either the target triple from the module, or the target triple of the + /// host if that does not exist. + MCTargetMachine *createMCTargetMachine(const Triple &TT) const { + if (!MCTargetMachineCtorFn) + return nullptr; + return MCTargetMachineCtorFn(*this, TT); + } + /// createMCAsmBackend - Create a target specific assembly parser. /// /// \param TheTriple The target triple string. @@ -717,6 +735,20 @@ T.TargetMachineCtorFn = Fn; } + /// RegisterMCTargetMachine - Register a MCTargetMachine implementation for + /// the given target. + /// + /// Clients are responsible for ensuring that registration doesn't occur + /// while another thread is attempting to access the registry. Typically + /// this is done by initializing all targets at program startup. + /// + /// @param T - The target being registered. + /// @param Fn - A function to construct a MCTargetMachine for the target. + static void RegisterMCTargetMachine(Target &T, + Target::MCTargetMachineCtorTy Fn) { + T.MCTargetMachineCtorFn = Fn; + } + /// RegisterMCAsmBackend - Register a MCAsmBackend implementation for the /// given target. /// @@ -885,15 +917,16 @@ /// extern Target TheFooTarget; /// RegisterMCAsmInfo X(TheFooTarget); /// } -template struct RegisterMCAsmInfo { +template +struct RegisterMCAsmInfo { RegisterMCAsmInfo(Target &T) { TargetRegistry::RegisterMCAsmInfo(T, &Allocator); } private: static MCAsmInfo *Allocator(const MCRegisterInfo & /*MRI*/, - const Triple &TT) { - return new MCAsmInfoImpl(TT); + const MCTargetMachine &MCTM) { + return new MCAsmInfoImpl(static_cast(MCTM)); } }; @@ -1100,6 +1133,25 @@ } }; +/// RegisterMCTargetMachine - Helper template for registering a target machine +/// implementation, for use in the target machine initialization +/// function. Usage: +/// +/// extern "C" void LLVMInitializeFooTarget() { +/// extern Target TheFooTarget; +/// RegisterMCTargetMachine X(TheFooTarget); +/// } +template struct RegisterMCTargetMachine { + RegisterMCTargetMachine(Target &T) { + TargetRegistry::RegisterMCTargetMachine(T, &Allocator); + } + +private: + static MCTargetMachine *Allocator(const Target &T, const Triple &TT) { + return new MCTargetMachineImpl(T, TT); + } +}; + /// RegisterMCAsmBackend - Helper template for registering a target specific /// assembler backend. Usage: /// Index: include/llvm/Target/TargetMachine.h =================================================================== --- include/llvm/Target/TargetMachine.h +++ include/llvm/Target/TargetMachine.h @@ -36,6 +36,7 @@ class MCRegisterInfo; class MCSubtargetInfo; class MCSymbol; +class MCTargetMachine; class Target; class DataLayout; class TargetLibraryInfo; @@ -90,6 +91,9 @@ std::string TargetCPU; std::string TargetFS; + /// Information about the target as it relates to the MC layer. + const MCTargetMachine *MCTM; + /// Low level target information such as relocation model. Non-const to /// allow resetting optimization level per-function. MCCodeGenInfo *CodeGenInfo; Index: lib/CodeGen/LLVMTargetMachine.cpp =================================================================== --- lib/CodeGen/LLVMTargetMachine.cpp +++ lib/CodeGen/LLVMTargetMachine.cpp @@ -43,6 +43,8 @@ cl::desc("Enable the \"fast\" instruction selector")); void LLVMTargetMachine::initAsmInfo() { + MCTM = TheTarget.createMCTargetMachine(getTargetTriple()); + assert(MCTM && "MCTargetMachine not initialized"); MRI = TheTarget.createMCRegInfo(getTargetTriple().str()); MII = TheTarget.createMCInstrInfo(); // FIXME: Having an MCSubtargetInfo on the target machine is a hack due @@ -52,8 +54,7 @@ STI = TheTarget.createMCSubtargetInfo(getTargetTriple().str(), getTargetCPU(), getTargetFeatureString()); - MCAsmInfo *TmpAsmInfo = - TheTarget.createMCAsmInfo(*MRI, getTargetTriple().str()); + MCAsmInfo *TmpAsmInfo = TheTarget.createMCAsmInfo(*MRI, *MCTM); // TargetSelect.h moved to a different directory between LLVM 2.9 and 3.0, // and if the old one gets included then MCAsmInfo will be NULL and // we'll crash later. Index: lib/MC/CMakeLists.txt =================================================================== --- lib/MC/CMakeLists.txt +++ lib/MC/CMakeLists.txt @@ -38,6 +38,7 @@ MCSymbol.cpp MCSymbolELF.cpp MCSymbolizer.cpp + MCTargetMachine.cpp MCTargetOptions.cpp MCValue.cpp MCWin64EH.cpp Index: lib/MC/MCDisassembler/Disassembler.cpp =================================================================== --- lib/MC/MCDisassembler/Disassembler.cpp +++ lib/MC/MCDisassembler/Disassembler.cpp @@ -43,12 +43,16 @@ if (!TheTarget) return nullptr; + const MCTargetMachine *MCTM = TheTarget->createMCTargetMachine(Triple(TT)); + if (!MCTM) + return nullptr; + const MCRegisterInfo *MRI = TheTarget->createMCRegInfo(TT); if (!MRI) return nullptr; // Get the assembler info needed to setup the MCContext. - const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, TT); + const MCAsmInfo *MAI = TheTarget->createMCAsmInfo(*MRI, *MCTM); if (!MAI) return nullptr; Index: lib/MC/MCTargetMachine.cpp =================================================================== --- /dev/null +++ lib/MC/MCTargetMachine.cpp @@ -0,0 +1,19 @@ +//===-- MCTargetMachine.cpp - General Target Information -------------------==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the general parts of a MC Target machine. +// +//===----------------------------------------------------------------------===// + +#include "llvm/MC/MCTargetMachine.h" +#include "llvm/Support/TargetRegistry.h" +using namespace llvm; + +MCTargetMachine::MCTargetMachine(const Target &T, const Triple &) + : TheTarget(T) {} Index: lib/Object/IRObjectFile.cpp =================================================================== --- lib/Object/IRObjectFile.cpp +++ lib/Object/IRObjectFile.cpp @@ -26,6 +26,7 @@ #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MCTargetAsmParser.h" #include "llvm/Object/ObjectFile.h" #include "llvm/Support/MemoryBuffer.h" @@ -49,11 +50,15 @@ if (!T) return; + std::unique_ptr MCTM(T->createMCTargetMachine(TT)); + if (!MCTM) + return; + std::unique_ptr MRI(T->createMCRegInfo(TT.str())); if (!MRI) return; - std::unique_ptr MAI(T->createMCAsmInfo(*MRI, TT.str())); + std::unique_ptr MAI(T->createMCAsmInfo(*MRI, *MCTM)); if (!MAI) return; Index: lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h +++ lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h @@ -20,7 +20,7 @@ namespace llvm { class MCStreamer; class Target; -class Triple; +class AArch64MCTargetMachine; struct AArch64MCAsmInfoDarwin : public MCAsmInfoDarwin { explicit AArch64MCAsmInfoDarwin(); @@ -30,7 +30,7 @@ }; struct AArch64MCAsmInfoELF : public MCAsmInfoELF { - explicit AArch64MCAsmInfoELF(const Triple &T); + explicit AArch64MCAsmInfoELF(const AArch64MCTargetMachine &T); }; } // namespace llvm Index: lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp +++ lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// #include "AArch64MCAsmInfo.h" -#include "llvm/ADT/Triple.h" +#include "AArch64MCTargetMachine.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCStreamer.h" @@ -69,9 +69,8 @@ return MCBinaryExpr::createSub(Res, PC, Context); } -AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const Triple &T) { - if (T.getArch() == Triple::aarch64_be) - IsLittleEndian = false; +AArch64MCAsmInfoELF::AArch64MCAsmInfoELF(const AArch64MCTargetMachine &MCTM) { + IsLittleEndian = MCTM.isLittleEndian(); // We prefer NEON instructions to be printed in the short form. AssemblerDialect = AsmWriterVariant == Default ? 0 : AsmWriterVariant; Index: lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp =================================================================== --- lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp +++ lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp @@ -14,6 +14,7 @@ #include "AArch64MCTargetDesc.h" #include "AArch64ELFStreamer.h" #include "AArch64MCAsmInfo.h" +#include "AArch64MCTargetMachine.h" #include "InstPrinter/AArch64InstPrinter.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" @@ -55,13 +56,15 @@ } static MCAsmInfo *createAArch64MCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TheTriple) { + const MCTargetMachine &MCTM_) { + const AArch64MCTargetMachine &MCTM = + static_cast(MCTM_); MCAsmInfo *MAI; - if (TheTriple.isOSBinFormatMachO()) + if (MCTM.isOSBinFormatMachO()) MAI = new AArch64MCAsmInfoDarwin(); else { - assert(TheTriple.isOSBinFormatELF() && "Only expect Darwin or ELF"); - MAI = new AArch64MCAsmInfoELF(TheTriple); + assert(MCTM.isOSBinFormatELF() && "Only expect Darwin or ELF"); + MAI = new AArch64MCAsmInfoELF(MCTM); } // Initial state of the frame pointer is SP. @@ -136,6 +139,9 @@ extern "C" void LLVMInitializeAArch64TargetMC() { for (Target *T : {&TheAArch64leTarget, &TheAArch64beTarget, &TheARM64Target}) { + // Register the MC target machine + RegisterMCTargetMachine Y(*T); + // Register the MC asm info. RegisterMCAsmInfoFn X(*T, createAArch64MCAsmInfo); Index: lib/Target/AArch64/MCTargetDesc/AArch64MCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/AArch64/MCTargetDesc/AArch64MCTargetMachine.h @@ -0,0 +1,47 @@ +//===-- AArch64MCTargetMachine.h - AArch64 Target Information ---*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the MCTargetMachine classes. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MCTARGETMACHINE_H +#define LLVM_LIB_TARGET_AARCH64_AARCH64MCTARGETMACHINE_H + +#include "llvm/ADT/Triple.h" +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class Target; + +class AArch64MCTargetMachine : public MCTargetMachine { + AArch64MCTargetMachine(const AArch64MCTargetMachine &) = delete; + void operator=(const AArch64MCTargetMachine &) = delete; + + bool IsOSDarwin; + bool IsOSBinFormatMachO; + bool IsOSBinFormatELF; + bool IsLittleEndian; + +public: + AArch64MCTargetMachine(const Target &T, const Triple &TargetTriple) + : MCTargetMachine(T, TargetTriple), IsOSDarwin(TargetTriple.isOSDarwin()), + IsOSBinFormatMachO(TargetTriple.isOSBinFormatMachO()), + IsOSBinFormatELF(TargetTriple.isOSBinFormatELF()), + IsLittleEndian(TargetTriple.getArch() != Triple::aarch64_be) {} + + bool isOSDarwin() const { return IsOSDarwin; } + bool isOSBinFormatMachO() const { return IsOSBinFormatMachO; }; + bool isOSBinFormatELF() const { return IsOSBinFormatELF; }; + bool isLittleEndian() const { return IsLittleEndian; } +}; + +} // End llvm namespace + +#endif Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.h @@ -16,8 +16,7 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { - -class Triple; +class MCTargetMachine; // If you need to create another MCAsmInfo class, which inherits from MCAsmInfo, // you will need to make sure your new class sets PrivateGlobalPrefix to @@ -26,7 +25,7 @@ // with 'L' as a local symbol. class AMDGPUMCAsmInfo : public MCAsmInfoELF { public: - explicit AMDGPUMCAsmInfo(const Triple &TT); + explicit AMDGPUMCAsmInfo(const MCTargetMachine &TM); }; } // namespace llvm #endif Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCAsmInfo.cpp @@ -11,7 +11,7 @@ #include "AMDGPUMCAsmInfo.h" using namespace llvm; -AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const Triple &TT) : MCAsmInfoELF() { +AMDGPUMCAsmInfo::AMDGPUMCAsmInfo(const MCTargetMachine &MCTM) : MCAsmInfoELF() { HasSingleParameterDotFile = false; //===------------------------------------------------------------------===// MaxInstLength = 16; Index: lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp =================================================================== --- lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp +++ lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp @@ -23,6 +23,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MachineLocation.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" @@ -87,6 +88,7 @@ extern "C" void LLVMInitializeAMDGPUTargetMC() { for (Target *T : {&TheAMDGPUTarget, &TheGCNTarget}) { + RegisterMCTargetMachine Y(*T); RegisterMCAsmInfo X(*T); TargetRegistry::RegisterMCCodeGenInfo(*T, createAMDGPUMCCodeGenInfo); Index: lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h +++ lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.h @@ -19,20 +19,20 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class Triple; +class ARMMCTargetMachine; class ARMMCAsmInfoDarwin : public MCAsmInfoDarwin { virtual void anchor(); public: - explicit ARMMCAsmInfoDarwin(const Triple &TheTriple); + explicit ARMMCAsmInfoDarwin(const ARMMCTargetMachine &MCTM); }; class ARMELFMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit ARMELFMCAsmInfo(const Triple &TT); + explicit ARMELFMCAsmInfo(const ARMMCTargetMachine &MCTM); void setUseIntegratedAssembler(bool Value) override; }; Index: lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp +++ lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp @@ -12,17 +12,15 @@ //===----------------------------------------------------------------------===// #include "ARMMCAsmInfo.h" -#include "llvm/ADT/Triple.h" +#include "ARMMCTargetMachine.h" #include "llvm/Support/CommandLine.h" using namespace llvm; void ARMMCAsmInfoDarwin::anchor() { } -ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const Triple &TheTriple) { - if ((TheTriple.getArch() == Triple::armeb) || - (TheTriple.getArch() == Triple::thumbeb)) - IsLittleEndian = false; +ARMMCAsmInfoDarwin::ARMMCAsmInfoDarwin(const ARMMCTargetMachine &MCTM) { + IsLittleEndian = MCTM.isLittleEndian(); Data64bitsDirective = nullptr; CommentString = "@"; @@ -40,10 +38,8 @@ void ARMELFMCAsmInfo::anchor() { } -ARMELFMCAsmInfo::ARMELFMCAsmInfo(const Triple &TheTriple) { - if ((TheTriple.getArch() == Triple::armeb) || - (TheTriple.getArch() == Triple::thumbeb)) - IsLittleEndian = false; +ARMELFMCAsmInfo::ARMELFMCAsmInfo(const ARMMCTargetMachine &MCTM) { + IsLittleEndian = MCTM.isLittleEndian(); // ".comm align is in bytes but .align is pow-2." AlignmentIsInBytes = false; @@ -56,7 +52,7 @@ SupportsDebugInformation = true; // Exceptions handling - switch (TheTriple.getOS()) { + switch (MCTM.getOS()) { case Triple::Bitrig: case Triple::NetBSD: ExceptionsType = ExceptionHandling::DwarfCFI; Index: lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp =================================================================== --- lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp +++ lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp @@ -14,6 +14,7 @@ #include "ARMBaseInfo.h" #include "ARMMCAsmInfo.h" #include "ARMMCTargetDesc.h" +#include "ARMMCTargetMachine.h" #include "InstPrinter/ARMInstPrinter.h" #include "llvm/ADT/Triple.h" #include "llvm/MC/MCCodeGenInfo.h" @@ -273,16 +274,18 @@ } static MCAsmInfo *createARMMCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TheTriple) { + const MCTargetMachine &MCTM_) { + const ARMMCTargetMachine &MCTM = + static_cast(MCTM_); MCAsmInfo *MAI; - if (TheTriple.isOSDarwin() || TheTriple.isOSBinFormatMachO()) - MAI = new ARMMCAsmInfoDarwin(TheTriple); - else if (TheTriple.isWindowsMSVCEnvironment()) + if (MCTM.isOSDarwin() || MCTM.isOSBinFormatMachO()) + MAI = new ARMMCAsmInfoDarwin(MCTM); + else if (MCTM.isWindowsMSVCEnvironment()) MAI = new ARMCOFFMCAsmInfoMicrosoft(); - else if (TheTriple.isOSWindows()) + else if (MCTM.isOSWindows()) MAI = new ARMCOFFMCAsmInfoGNU(); else - MAI = new ARMELFMCAsmInfo(TheTriple); + MAI = new ARMELFMCAsmInfo(MCTM); unsigned Reg = MRI.getDwarfRegNum(ARM::SP, true); MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0)); @@ -377,6 +380,9 @@ extern "C" void LLVMInitializeARMTargetMC() { for (Target *T : {&TheARMLETarget, &TheARMBETarget, &TheThumbLETarget, &TheThumbBETarget}) { + // Register the MC target machine + RegisterMCTargetMachine Y(*T); + // Register the MC asm info. RegisterMCAsmInfoFn X(*T, createARMMCAsmInfo); Index: lib/Target/ARM/MCTargetDesc/ARMMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/ARM/MCTargetDesc/ARMMCTargetMachine.h @@ -0,0 +1,54 @@ +//===-- ARMMCTargetMachine.h - ARM Target Information -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the MCTargetMachine classes. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_ARM_ARMMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_ARM_ARMMCTARGETMACHINE_H + +#include "llvm/ADT/Triple.h" +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class Target; + +class ARMMCTargetMachine : public MCTargetMachine { + ARMMCTargetMachine(const ARMMCTargetMachine &) = delete; + void operator=(const ARMMCTargetMachine &) = delete; + + bool IsOSDarwin; + bool IsOSWindows; + bool IsWindowsMSVCEnvironment; + bool IsOSBinFormatMachO; + bool IsLittleEndian; + Triple::OSType OS; + +public: + ARMMCTargetMachine(const Target &T, const Triple &TargetTriple) + : MCTargetMachine(T, TargetTriple), IsOSDarwin(TargetTriple.isOSDarwin()), + IsOSWindows(TargetTriple.isOSWindows()), + IsWindowsMSVCEnvironment(TargetTriple.isWindowsMSVCEnvironment()), + IsOSBinFormatMachO(TargetTriple.isOSBinFormatMachO()), + IsLittleEndian(TargetTriple.getArch() != Triple::armeb && + TargetTriple.getArch() != Triple::thumbeb), + OS(TargetTriple.getOS()) {} + + bool isOSDarwin() const { return IsOSDarwin; } + bool isOSBinFormatMachO() const { return IsOSBinFormatMachO; }; + bool isOSWindows() const { return IsOSWindows; } + bool isWindowsMSVCEnvironment() const { return IsWindowsMSVCEnvironment; } + Triple::OSType getOS() const { return OS; } + bool isLittleEndian() const { return IsLittleEndian; } +}; + +} // End llvm namespace + +#endif Index: lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h =================================================================== --- lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h +++ lib/Target/BPF/MCTargetDesc/BPFMCAsmInfo.h @@ -14,19 +14,21 @@ #ifndef LLVM_LIB_TARGET_BPF_MCTARGETDESC_BPFMCASMINFO_H #define LLVM_LIB_TARGET_BPF_MCTARGETDESC_BPFMCASMINFO_H +#include "BPFMCTargetMachine.h" #include "llvm/ADT/StringRef.h" -#include "llvm/MC/MCAsmInfo.h" #include "llvm/ADT/Triple.h" +#include "llvm/MC/MCAsmInfo.h" namespace llvm { class Target; -class Triple; +class BPFMCTargetMachine; class BPFMCAsmInfo : public MCAsmInfo { public: - explicit BPFMCAsmInfo(const Triple &TT) { - if (TT.getArch() == Triple::bpfeb) - IsLittleEndian = false; + explicit BPFMCAsmInfo(const MCTargetMachine &MCTM_) { + const BPFMCTargetMachine &MCTM = + static_cast(MCTM_); + IsLittleEndian = MCTM.isLittleEndian(); PrivateGlobalPrefix = ".L"; WeakRefDirective = "\t.weak\t"; Index: lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp =================================================================== --- lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp +++ lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.cpp @@ -12,8 +12,9 @@ //===----------------------------------------------------------------------===// #include "BPF.h" -#include "BPFMCTargetDesc.h" #include "BPFMCAsmInfo.h" +#include "BPFMCTargetDesc.h" +#include "BPFMCTargetMachine.h" #include "InstPrinter/BPFInstPrinter.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" @@ -78,8 +79,11 @@ extern "C" void LLVMInitializeBPFTargetMC() { for (Target *T : {&TheBPFleTarget, &TheBPFbeTarget, &TheBPFTarget}) { + // Register the MC target machine + RegisterMCTargetMachine Y(*T); + // Register the MC asm info. - RegisterMCAsmInfo X(*T); + RegisterMCAsmInfo X(*T); // Register the MC codegen info. TargetRegistry::RegisterMCCodeGenInfo(*T, createBPFMCCodeGenInfo); Index: lib/Target/BPF/MCTargetDesc/BPFMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/BPF/MCTargetDesc/BPFMCTargetMachine.h @@ -0,0 +1,39 @@ +//===-- BPFMCTargetMachine.h - BPF Target Information -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the MCTargetMachine classes. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_BPF_BPFMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_BPF_BPFMCTARGETMACHINE_H + +#include "llvm/ADT/Triple.h" +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class Target; + +class BPFMCTargetMachine : public MCTargetMachine { + BPFMCTargetMachine(const BPFMCTargetMachine &) = delete; + void operator=(const BPFMCTargetMachine &) = delete; + + bool IsLittleEndian; + +public: + BPFMCTargetMachine(const Target &T, const Triple &TargetTriple) + : MCTargetMachine(T, TargetTriple), + IsLittleEndian(TargetTriple.getArch() != Triple::bpfeb) {} + + bool isLittleEndian() const { return IsLittleEndian; } +}; + +} // End llvm namespace + +#endif Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h @@ -18,13 +18,13 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class Triple; +class MCTargetMachine; class HexagonMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit HexagonMCAsmInfo(const Triple &TT); + explicit HexagonMCAsmInfo(const MCTargetMachine &MCTM); }; } // namespace llvm Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp @@ -18,7 +18,7 @@ // Pin the vtable to this file. void HexagonMCAsmInfo::anchor() {} -HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) { +HexagonMCAsmInfo::HexagonMCAsmInfo(const MCTargetMachine &MCTM) { Data16bitsDirective = "\t.half\t"; Data32bitsDirective = "\t.word\t"; Data64bitsDirective = nullptr; // .xword is only supported by V9. Index: lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp =================================================================== --- lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -24,6 +24,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MachineLocation.h" #include "llvm/Support/ELF.h" #include "llvm/Support/ErrorHandling.h" @@ -138,8 +139,8 @@ } static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TT) { - MCAsmInfo *MAI = new HexagonMCAsmInfo(TT); + const MCTargetMachine &MCTM) { + MCAsmInfo *MAI = new HexagonMCAsmInfo(MCTM); // VirtualFP = (R30 + #0). MCCFIInstruction Inst = @@ -191,6 +192,9 @@ // Force static initialization. extern "C" void LLVMInitializeHexagonTargetMC() { + // Register the MC target machine + RegisterMCTargetMachine Y(TheHexagonTarget); + // Register the MC asm info. RegisterMCAsmInfoFn X(TheHexagonTarget, createHexagonMCAsmInfo); Index: lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h =================================================================== --- lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h +++ lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.h @@ -17,13 +17,13 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class Triple; +class MCTargetMachine; class MSP430MCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit MSP430MCAsmInfo(const Triple &TT); + explicit MSP430MCAsmInfo(const MCTargetMachine &MCTM); }; } // namespace llvm Index: lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp =================================================================== --- lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp +++ lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp @@ -16,7 +16,7 @@ void MSP430MCAsmInfo::anchor() { } -MSP430MCAsmInfo::MSP430MCAsmInfo(const Triple &TT) { +MSP430MCAsmInfo::MSP430MCAsmInfo(const MCTargetMachine &MCTM) { PointerSize = CalleeSaveStackSlotSize = 2; CommentString = ";"; Index: lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp =================================================================== --- lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp +++ lib/Target/MSP430/MCTargetDesc/MSP430MCTargetDesc.cpp @@ -18,6 +18,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -68,6 +69,9 @@ } extern "C" void LLVMInitializeMSP430TargetMC() { + // Register the MC target machine + RegisterMCTargetMachine Y(TheMSP430Target); + // Register the MC asm info. RegisterMCAsmInfo X(TheMSP430Target); Index: lib/Target/Mips/MCTargetDesc/MipsABIInfo.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsABIInfo.h +++ lib/Target/Mips/MCTargetDesc/MipsABIInfo.h @@ -72,6 +72,10 @@ unsigned GetPtrAddiuOp() const; unsigned GetGPRMoveOp() const; inline bool ArePtrs64bit() const { return IsN64(); } + inline unsigned GetPtrSizeInBytes() const { return ArePtrs64bit() ? 8 : 4; } + inline unsigned GetStackSlotSizeInBytes() const { + return AreGprs64bit() ? 8 : 4; + } inline bool AreGprs64bit() const { return IsN32() || IsN64(); } unsigned GetEhDataReg(unsigned I) const; Index: lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h +++ lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.h @@ -17,13 +17,13 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class Triple; +class MipsMCTargetMachine; class MipsMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit MipsMCAsmInfo(const Triple &TheTriple); + explicit MipsMCAsmInfo(const MipsMCTargetMachine &MCTM); }; } // namespace llvm Index: lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp @@ -12,21 +12,16 @@ //===----------------------------------------------------------------------===// #include "MipsMCAsmInfo.h" -#include "llvm/ADT/Triple.h" +#include "MipsMCTargetMachine.h" using namespace llvm; void MipsMCAsmInfo::anchor() { } -MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple) { - if ((TheTriple.getArch() == Triple::mips) || - (TheTriple.getArch() == Triple::mips64)) - IsLittleEndian = false; - - if ((TheTriple.getArch() == Triple::mips64el) || - (TheTriple.getArch() == Triple::mips64)) { - PointerSize = CalleeSaveStackSlotSize = 8; - } +MipsMCAsmInfo::MipsMCAsmInfo(const MipsMCTargetMachine &MCTM) { + IsLittleEndian = MCTM.isLittleEndian(); + PointerSize = MCTM.getABI().GetPtrSizeInBytes(); + CalleeSaveStackSlotSize = MCTM.getABI().GetStackSlotSizeInBytes(); AlignmentIsInBytes = false; Data16bitsDirective = "\t.2byte\t"; Index: lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -16,6 +16,7 @@ #include "MipsMCAsmInfo.h" #include "MipsMCNaCl.h" #include "MipsMCTargetDesc.h" +#include "MipsMCTargetMachine.h" #include "MipsTargetStreamer.h" #include "llvm/ADT/Triple.h" #include "llvm/MC/MCCodeGenInfo.h" @@ -72,8 +73,10 @@ } static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TT) { - MCAsmInfo *MAI = new MipsMCAsmInfo(TT); + const MCTargetMachine &MCTM_) { + const MipsMCTargetMachine &MCTM = + static_cast(MCTM_); + MCAsmInfo *MAI = new MipsMCAsmInfo(MCTM); unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, SP, 0); @@ -132,6 +135,9 @@ extern "C" void LLVMInitializeMipsTargetMC() { for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target, &TheMips64elTarget}) { + // Register the MC target machine + RegisterMCTargetMachine Y(*T); + // Register the MC asm info. RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo); Index: lib/Target/Mips/MCTargetDesc/MipsMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/Mips/MCTargetDesc/MipsMCTargetMachine.h @@ -0,0 +1,50 @@ +//===-- MipsMCTargetMachine.h - Mips Target Information ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the MCTargetMachine classes. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_MIPS_MIPSMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_MIPS_MIPSMCTARGETMACHINE_H + +#include "MipsABIInfo.h" +#include "llvm/ADT/Triple.h" +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class Target; + +class MipsMCTargetMachine : public MCTargetMachine { + MipsMCTargetMachine(const MipsMCTargetMachine &) = delete; + void operator=(const MipsMCTargetMachine &) = delete; + + bool IsLittleEndian; + MipsABIInfo ABI; + +public: + MipsMCTargetMachine(const Target &T, const Triple &TargetTriple) + : MCTargetMachine(T, TargetTriple), + IsLittleEndian(!(TargetTriple.getArch() == Triple::mips || + TargetTriple.getArch() == Triple::mips64)), + ABI( + // FIXME: This is wrong but it preserves current behaviour until + // we receive the correct ABI. + (TargetTriple.getArch() == Triple::mips64el || + TargetTriple.getArch() == Triple::mips64) + ? MipsABIInfo::N64() + : MipsABIInfo::O32()) {} + + bool isLittleEndian() const { return IsLittleEndian; } + const MipsABIInfo getABI() const { return ABI; }; +}; + +} // End llvm namespace + +#endif Index: lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h =================================================================== --- lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h +++ lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.h @@ -18,13 +18,13 @@ namespace llvm { class Target; -class Triple; +class NVPTXMCTargetMachine; class NVPTXMCAsmInfo : public MCAsmInfo { virtual void anchor(); public: - explicit NVPTXMCAsmInfo(const Triple &TheTriple); + explicit NVPTXMCAsmInfo(const NVPTXMCTargetMachine &MCTM); }; } // namespace llvm Index: lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp =================================================================== --- lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp +++ lib/Target/NVPTX/MCTargetDesc/NVPTXMCAsmInfo.cpp @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// #include "NVPTXMCAsmInfo.h" -#include "llvm/ADT/Triple.h" +#include "NVPTXMCTargetMachine.h" #include "llvm/Support/CommandLine.h" using namespace llvm; @@ -25,10 +25,9 @@ void NVPTXMCAsmInfo::anchor() {} -NVPTXMCAsmInfo::NVPTXMCAsmInfo(const Triple &TheTriple) { - if (TheTriple.getArch() == Triple::nvptx64) { +NVPTXMCAsmInfo::NVPTXMCAsmInfo(const NVPTXMCTargetMachine &MCTM) { + if (MCTM.isArch64Bit()) PointerSize = CalleeSaveStackSlotSize = 8; - } CommentString = "//"; Index: lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp =================================================================== --- lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp +++ lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetDesc.cpp @@ -14,6 +14,7 @@ #include "NVPTXMCTargetDesc.h" #include "InstPrinter/NVPTXInstPrinter.h" #include "NVPTXMCAsmInfo.h" +#include "NVPTXMCTargetMachine.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" @@ -74,8 +75,11 @@ // Force static initialization. extern "C" void LLVMInitializeNVPTXTargetMC() { for (Target *T : {&TheNVPTXTarget32, &TheNVPTXTarget64}) { + // Register the MC target machine + RegisterMCTargetMachine Y(*T); + // Register the MC asm info. - RegisterMCAsmInfo X(*T); + RegisterMCAsmInfo X(*T); // Register the MC codegen info. TargetRegistry::RegisterMCCodeGenInfo(*T, createNVPTXMCCodeGenInfo); Index: lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/NVPTX/MCTargetDesc/NVPTXMCTargetMachine.h @@ -0,0 +1,39 @@ +//===-- NVPTXMCTargetMachine.h - NVPTX Target Information -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the MCTargetMachine classes. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MCTARGETMACHINE_H +#define LLVM_LIB_TARGET_AARCH64_AARCH64MCTARGETMACHINE_H + +#include "llvm/ADT/Triple.h" +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class Target; + +class NVPTXMCTargetMachine : public MCTargetMachine { + NVPTXMCTargetMachine(const NVPTXMCTargetMachine &) = delete; + void operator=(const NVPTXMCTargetMachine &) = delete; + + bool IsArch64Bit; + +public: + NVPTXMCTargetMachine(const Target &T, const Triple &TargetTriple) + : MCTargetMachine(T, TargetTriple), + IsArch64Bit(TargetTriple.getArch() == Triple::nvptx64) {} + + bool isArch64Bit() const { return IsArch64Bit; } +}; + +} // End llvm namespace + +#endif Index: lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h =================================================================== --- lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h +++ lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.h @@ -18,20 +18,20 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class Triple; +class PPCMCTargetMachine; class PPCMCAsmInfoDarwin : public MCAsmInfoDarwin { virtual void anchor(); public: - explicit PPCMCAsmInfoDarwin(bool is64Bit, const Triple &); + explicit PPCMCAsmInfoDarwin(bool is64Bit, const PPCMCTargetMachine &); }; class PPCELFMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit PPCELFMCAsmInfo(bool is64Bit, const Triple &); + explicit PPCELFMCAsmInfo(bool is64Bit, const PPCMCTargetMachine &); }; } // namespace llvm Index: lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp =================================================================== --- lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp +++ lib/Target/PowerPC/MCTargetDesc/PPCMCAsmInfo.cpp @@ -12,13 +12,14 @@ //===----------------------------------------------------------------------===// #include "PPCMCAsmInfo.h" -#include "llvm/ADT/Triple.h" +#include "PPCMCTargetMachine.h" using namespace llvm; void PPCMCAsmInfoDarwin::anchor() { } -PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, const Triple& T) { +PPCMCAsmInfoDarwin::PPCMCAsmInfoDarwin(bool is64Bit, + const PPCMCTargetMachine &MCTM) { if (is64Bit) { PointerSize = CalleeSaveStackSlotSize = 8; } @@ -36,7 +37,7 @@ // The installed assembler for OSX < 10.6 lacks some directives. // FIXME: this should really be a check on the assembler characteristics // rather than OS version - if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6)) + if (MCTM.isMacOSX() && MCTM.isMacOSXVersionLT(10, 6)) HasWeakDefCanBeHiddenDirective = false; UseIntegratedAssembler = true; @@ -44,7 +45,7 @@ void PPCELFMCAsmInfo::anchor() { } -PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool is64Bit, const Triple& T) { +PPCELFMCAsmInfo::PPCELFMCAsmInfo(bool is64Bit, const PPCMCTargetMachine &MCTM) { // FIXME: This is not always needed. For example, it is not needed in the // v2 abi. NeedsLocalForSize = true; @@ -52,7 +53,7 @@ if (is64Bit) { PointerSize = CalleeSaveStackSlotSize = 8; } - IsLittleEndian = T.getArch() == Triple::ppc64le; + IsLittleEndian = MCTM.isLittleEndian(); // ".comm align is in bytes but .align is pow-2." AlignmentIsInBytes = false; Index: lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp =================================================================== --- lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -14,6 +14,7 @@ #include "PPCMCTargetDesc.h" #include "InstPrinter/PPCInstPrinter.h" #include "PPCMCAsmInfo.h" +#include "PPCMCTargetMachine.h" #include "PPCTargetStreamer.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCContext.h" @@ -68,15 +69,16 @@ } static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TheTriple) { - bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 || - TheTriple.getArch() == Triple::ppc64le); + const MCTargetMachine &MCTM_) { + const PPCMCTargetMachine &MCTM = + static_cast(MCTM_); + bool isPPC64 = MCTM.isArch64Bit(); MCAsmInfo *MAI; - if (TheTriple.isOSDarwin()) - MAI = new PPCMCAsmInfoDarwin(isPPC64, TheTriple); + if (MCTM.isOSDarwin()) + MAI = new PPCMCAsmInfoDarwin(isPPC64, MCTM); else - MAI = new PPCELFMCAsmInfo(isPPC64, TheTriple); + MAI = new PPCELFMCAsmInfo(isPPC64, MCTM); // Initial state of the frame pointer is R1. unsigned Reg = isPPC64 ? PPC::X1 : PPC::R1; @@ -241,6 +243,9 @@ extern "C" void LLVMInitializePowerPCTargetMC() { for (Target *T : {&ThePPC32Target, &ThePPC64Target, &ThePPC64LETarget}) { + // Register the MC target machine + RegisterMCTargetMachine Y(*T); + // Register the MC asm info. RegisterMCAsmInfoFn C(*T, createPPCMCAsmInfo); Index: lib/Target/PowerPC/MCTargetDesc/PPCMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/PowerPC/MCTargetDesc/PPCMCTargetMachine.h @@ -0,0 +1,57 @@ +//===-- PPCMCTargetMachine.h - PPC Target Information -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the MCTargetMachine classes. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_PPC_PPCMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_PPC_PPCMCTARGETMACHINE_H + +#include "llvm/ADT/Triple.h" +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class Target; + +class PPCMCTargetMachine : public MCTargetMachine { + PPCMCTargetMachine(const PPCMCTargetMachine &) = delete; + void operator=(const PPCMCTargetMachine &) = delete; + + // FIXME: We have this to be able to use the MacOSX version comparison. + // It should not be used as a description of the target. + Triple TheTargetTriple; + + bool IsOSDarwin; + bool IsMacOSX; + bool IsLittleEndian; + bool IsArch64Bit; + +public: + PPCMCTargetMachine(const Target &T, const Triple &TargetTriple) + : MCTargetMachine(T, TargetTriple), TheTargetTriple(TargetTriple), + IsOSDarwin(TargetTriple.isOSDarwin()), + IsMacOSX(TargetTriple.isMacOSX()), + IsLittleEndian(TargetTriple.getArch() == Triple::ppc64le), + IsArch64Bit(TargetTriple.getArch() == Triple::ppc64 || + TargetTriple.getArch() == Triple::ppc64le) {} + + bool isOSDarwin() const { return IsOSDarwin; } + bool isMacOSX() const { return IsMacOSX; } + unsigned isMacOSXVersionLT(unsigned Major, unsigned Minor = 0, + unsigned Micro = 0) const { + return TheTargetTriple.isMacOSXVersionLT(Major, Minor, Micro); + } + bool isLittleEndian() const { return IsLittleEndian; } + bool isArch64Bit() const { return IsArch64Bit; } +}; + +} // End llvm namespace + +#endif Index: lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h =================================================================== --- lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h +++ lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.h @@ -17,13 +17,13 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class Triple; +class SparcMCTargetMachine; class SparcELFMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit SparcELFMCAsmInfo(const Triple &TheTriple); + explicit SparcELFMCAsmInfo(const SparcMCTargetMachine &MCTM); const MCExpr* getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding, MCStreamer &Streamer) const override; Index: lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp =================================================================== --- lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp +++ lib/Target/Sparc/MCTargetDesc/SparcMCAsmInfo.cpp @@ -13,16 +13,16 @@ #include "SparcMCAsmInfo.h" #include "SparcMCExpr.h" -#include "llvm/ADT/Triple.h" +#include "SparcMCTargetMachine.h" #include "llvm/MC/MCStreamer.h" using namespace llvm; void SparcELFMCAsmInfo::anchor() {} -SparcELFMCAsmInfo::SparcELFMCAsmInfo(const Triple &TheTriple) { - bool isV9 = (TheTriple.getArch() == Triple::sparcv9); - IsLittleEndian = (TheTriple.getArch() == Triple::sparcel); +SparcELFMCAsmInfo::SparcELFMCAsmInfo(const SparcMCTargetMachine &MCTM) { + bool isV9 = MCTM.isV9(); + IsLittleEndian = MCTM.isLittleEndian(); if (isV9) { PointerSize = CalleeSaveStackSlotSize = 8; Index: lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp =================================================================== --- lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp +++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp @@ -14,6 +14,7 @@ #include "SparcMCTargetDesc.h" #include "InstPrinter/SparcInstPrinter.h" #include "SparcMCAsmInfo.h" +#include "SparcMCTargetMachine.h" #include "SparcTargetStreamer.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" @@ -34,8 +35,10 @@ #include "SparcGenRegisterInfo.inc" static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TT) { - MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); + const MCTargetMachine &MCTM_) { + const SparcMCTargetMachine &MCTM = + static_cast(MCTM_); + MCAsmInfo *MAI = new SparcELFMCAsmInfo(MCTM); unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 0); MAI->addInitialFrameState(Inst); @@ -43,8 +46,10 @@ } static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TT) { - MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); + const MCTargetMachine &MCTM_) { + const SparcMCTargetMachine &MCTM = + static_cast(MCTM_); + MCAsmInfo *MAI = new SparcELFMCAsmInfo(MCTM); unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, Reg, 2047); MAI->addInitialFrameState(Inst); @@ -148,6 +153,9 @@ RegisterMCAsmInfoFn Z(TheSparcelTarget, createSparcMCAsmInfo); for (Target *T : {&TheSparcTarget, &TheSparcV9Target, &TheSparcelTarget}) { + // Register the MC target machine + RegisterMCTargetMachine Y(*T); + // Register the MC instruction info. TargetRegistry::RegisterMCInstrInfo(*T, createSparcMCInstrInfo); Index: lib/Target/Sparc/MCTargetDesc/SparcMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetMachine.h @@ -0,0 +1,42 @@ +//===-- SparcMCTargetMachine.h - Sparc Target Information -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the MCTargetMachine classes. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_SPARC_SPARCMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_SPARC_SPARCMCTARGETMACHINE_H + +#include "llvm/ADT/Triple.h" +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class Target; + +class SparcMCTargetMachine : public MCTargetMachine { + SparcMCTargetMachine(const SparcMCTargetMachine &) = delete; + void operator=(const SparcMCTargetMachine &) = delete; + + bool IsV9; + bool IsLittleEndian; + +public: + SparcMCTargetMachine(const Target &T, const Triple &TargetTriple) + : MCTargetMachine(T, TargetTriple), + IsV9(TargetTriple.getArch() == Triple::sparcv9), + IsLittleEndian(TargetTriple.getArch() == Triple::sparcel) {} + + bool isV9() const { return IsV9; } + bool isLittleEndian() const { return IsLittleEndian; } +}; + +} // End llvm namespace + +#endif Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h =================================================================== --- lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.h @@ -14,11 +14,11 @@ #include "llvm/Support/Compiler.h" namespace llvm { -class Triple; +class MCTargetMachine; class SystemZMCAsmInfo : public MCAsmInfoELF { public: - explicit SystemZMCAsmInfo(const Triple &TT); + explicit SystemZMCAsmInfo(const MCTargetMachine &MCTM); }; } // end namespace llvm Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp =================================================================== --- lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp @@ -13,7 +13,7 @@ using namespace llvm; -SystemZMCAsmInfo::SystemZMCAsmInfo(const Triple &TT) { +SystemZMCAsmInfo::SystemZMCAsmInfo(const MCTargetMachine &MCTM) { PointerSize = 8; CalleeSaveStackSlotSize = 8; IsLittleEndian = false; Index: lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp =================================================================== --- lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp +++ lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp @@ -15,6 +15,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/TargetRegistry.h" using namespace llvm; @@ -132,8 +133,8 @@ } static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TT) { - MCAsmInfo *MAI = new SystemZMCAsmInfo(TT); + const MCTargetMachine &MCTM) { + MCAsmInfo *MAI = new SystemZMCAsmInfo(MCTM); MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, MRI.getDwarfRegNum(SystemZ::R15D, true), @@ -216,6 +217,9 @@ } extern "C" void LLVMInitializeSystemZTargetMC() { + // Register the MC target machine + RegisterMCTargetMachine Y(TheSystemZTarget); + // Register the MCAsmInfo. TargetRegistry::RegisterMCAsmInfo(TheSystemZTarget, createSystemZMCAsmInfo); Index: lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h =================================================================== --- lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h +++ lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.h @@ -19,11 +19,11 @@ namespace llvm { -class Triple; +class WebAssemblyMCTargetMachine; class WebAssemblyMCAsmInfo final : public MCAsmInfo { public: - explicit WebAssemblyMCAsmInfo(const Triple &T); + explicit WebAssemblyMCAsmInfo(const WebAssemblyMCTargetMachine &MCTM); ~WebAssemblyMCAsmInfo() override; }; Index: lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp =================================================================== --- lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp +++ lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCAsmInfo.cpp @@ -14,7 +14,7 @@ //===----------------------------------------------------------------------===// #include "WebAssemblyMCAsmInfo.h" -#include "llvm/ADT/Triple.h" +#include "WebAssemblyMCTargetMachine.h" #include "llvm/Support/CommandLine.h" using namespace llvm; @@ -22,8 +22,9 @@ WebAssemblyMCAsmInfo::~WebAssemblyMCAsmInfo() {} -WebAssemblyMCAsmInfo::WebAssemblyMCAsmInfo(const Triple &T) { - PointerSize = CalleeSaveStackSlotSize = T.isArch64Bit() ? 8 : 4; +WebAssemblyMCAsmInfo::WebAssemblyMCAsmInfo( + const WebAssemblyMCTargetMachine &MCTM) { + PointerSize = CalleeSaveStackSlotSize = MCTM.isArch64Bit() ? 8 : 4; // TODO: What should MaxInstLength be? Index: lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp =================================================================== --- lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp +++ lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetDesc.cpp @@ -15,6 +15,7 @@ #include "WebAssemblyMCTargetDesc.h" #include "InstPrinter/WebAssemblyInstPrinter.h" #include "WebAssemblyMCAsmInfo.h" +#include "WebAssemblyMCTargetMachine.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" @@ -35,11 +36,6 @@ #define GET_REGINFO_MC_DESC #include "WebAssemblyGenRegisterInfo.inc" -static MCAsmInfo *createWebAssemblyMCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TT) { - return new WebAssemblyMCAsmInfo(TT); -} - static MCInstPrinter * createWebAssemblyMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, @@ -51,8 +47,11 @@ // Force static initialization. extern "C" void LLVMInitializeWebAssemblyTargetMC() { for (Target *T : {&TheWebAssemblyTarget32, &TheWebAssemblyTarget64}) { + // Register the MC target machine + RegisterMCTargetMachine Y(*T); + // Register the MC asm info. - RegisterMCAsmInfoFn X(*T, createWebAssemblyMCAsmInfo); + RegisterMCAsmInfo X(*T); // Register the MCInstPrinter. TargetRegistry::RegisterMCInstPrinter(*T, createWebAssemblyMCInstPrinter); Index: lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTargetMachine.h @@ -0,0 +1,39 @@ +//===-- WebAssemblyMCTargetMachine.h - Target Information -------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the MCTargetMachine classes. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMCTARGETMACHINE_H +#define LLVM_LIB_TARGET_WEBASSEMBLY_WEBASSEMBLYMCTARGETMACHINE_H + +#include "llvm/ADT/Triple.h" +#include "llvm/MC/MCTargetMachine.h" + +namespace llvm { +class Target; + +class WebAssemblyMCTargetMachine : public MCTargetMachine { + WebAssemblyMCTargetMachine(const WebAssemblyMCTargetMachine &) = delete; + void operator=(const WebAssemblyMCTargetMachine &) = delete; + + bool IsArch64Bit; + +public: + WebAssemblyMCTargetMachine(const Target &T, const Triple &TargetTriple) + : MCTargetMachine(T, TargetTriple), + IsArch64Bit(TargetTriple.isArch64Bit()) {} + + bool isArch64Bit() const { return IsArch64Bit; } +}; + +} // End llvm namespace + +#endif Index: lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h =================================================================== --- lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h +++ lib/Target/X86/MCTargetDesc/X86MCAsmInfo.h @@ -20,17 +20,17 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class Triple; +class X86MCTargetMachine; class X86MCAsmInfoDarwin : public MCAsmInfoDarwin { virtual void anchor(); public: - explicit X86MCAsmInfoDarwin(const Triple &Triple); + explicit X86MCAsmInfoDarwin(const X86MCTargetMachine &MCTM); }; struct X86_64MCAsmInfoDarwin : public X86MCAsmInfoDarwin { - explicit X86_64MCAsmInfoDarwin(const Triple &Triple); + explicit X86_64MCAsmInfoDarwin(const X86MCTargetMachine &MCTM); const MCExpr * getExprForPersonalitySymbol(const MCSymbol *Sym, unsigned Encoding, MCStreamer &Streamer) const override; @@ -40,21 +40,21 @@ void anchor() override; public: - explicit X86ELFMCAsmInfo(const Triple &Triple); + explicit X86ELFMCAsmInfo(const X86MCTargetMachine &MCTM); }; class X86MCAsmInfoMicrosoft : public MCAsmInfoMicrosoft { void anchor() override; public: - explicit X86MCAsmInfoMicrosoft(const Triple &Triple); + explicit X86MCAsmInfoMicrosoft(const X86MCTargetMachine &MCTM); }; class X86MCAsmInfoGNUCOFF : public MCAsmInfoGNUCOFF { void anchor() override; public: - explicit X86MCAsmInfoGNUCOFF(const Triple &Triple); + explicit X86MCAsmInfoGNUCOFF(const X86MCTargetMachine &MCTM); }; } // namespace llvm Index: lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp =================================================================== --- lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp +++ lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// #include "X86MCAsmInfo.h" -#include "llvm/ADT/Triple.h" +#include "X86MCTargetMachine.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCSectionELF.h" @@ -41,8 +41,8 @@ void X86MCAsmInfoDarwin::anchor() { } -X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const Triple &T) { - bool is64Bit = T.getArch() == Triple::x86_64; +X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const X86MCTargetMachine &MCTM) { + bool is64Bit = MCTM.isArch64Bit(); if (is64Bit) PointerSize = CalleeSaveStackSlotSize = 8; @@ -69,7 +69,7 @@ // old assembler lacks some directives // FIXME: this should really be a check on the assembler characteristics // rather than OS version - if (T.isMacOSX() && T.isMacOSXVersionLT(10, 6)) + if (MCTM.isMacOSX() && MCTM.isMacOSXVersionLT(10, 6)) HasWeakDefCanBeHiddenDirective = false; // Assume ld64 is new enough that the abs-ified FDE relocs may be used @@ -80,15 +80,14 @@ UseIntegratedAssembler = true; } -X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const Triple &Triple) - : X86MCAsmInfoDarwin(Triple) { -} +X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const X86MCTargetMachine &MCTM) + : X86MCAsmInfoDarwin(MCTM) {} void X86ELFMCAsmInfo::anchor() { } -X86ELFMCAsmInfo::X86ELFMCAsmInfo(const Triple &T) { - bool is64Bit = T.getArch() == Triple::x86_64; - bool isX32 = T.getEnvironment() == Triple::GNUX32; +X86ELFMCAsmInfo::X86ELFMCAsmInfo(const X86MCTargetMachine &MCTM) { + bool is64Bit = MCTM.isArch64Bit(); + bool isX32 = MCTM.isGnuX32Environment(); // For ELF, x86-64 pointer size depends on the ABI. // For x86-64 without the x32 ABI, pointer size is 8. For x86 and for x86-64 @@ -126,8 +125,8 @@ void X86MCAsmInfoMicrosoft::anchor() { } -X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const Triple &Triple) { - if (Triple.getArch() == Triple::x86_64) { +X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const X86MCTargetMachine &MCTM) { + if (MCTM.isArch64Bit()) { PrivateGlobalPrefix = ".L"; PrivateLabelPrefix = ".L"; PointerSize = 8; @@ -152,9 +151,9 @@ void X86MCAsmInfoGNUCOFF::anchor() { } -X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const Triple &Triple) { - assert(Triple.isOSWindows() && "Windows is the only supported COFF target"); - if (Triple.getArch() == Triple::x86_64) { +X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const X86MCTargetMachine &MCTM) { + assert(MCTM.isOSWindows() && "Windows is the only supported COFF target"); + if (MCTM.isArch64Bit()) { PrivateGlobalPrefix = ".L"; PrivateLabelPrefix = ".L"; PointerSize = 8; Index: lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp =================================================================== --- lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp +++ lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp @@ -15,6 +15,7 @@ #include "InstPrinter/X86ATTInstPrinter.h" #include "InstPrinter/X86IntelInstPrinter.h" #include "X86MCAsmInfo.h" +#include "X86MCTargetMachine.h" #include "llvm/ADT/Triple.h" #include "llvm/MC/MCCodeGenInfo.h" #include "llvm/MC/MCInstrAnalysis.h" @@ -110,27 +111,28 @@ } static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TheTriple) { - bool is64Bit = TheTriple.getArch() == Triple::x86_64; + const MCTargetMachine &MCTM_) { + const X86MCTargetMachine &MCTM = + static_cast(MCTM_); + bool is64Bit = MCTM.isArch64Bit(); MCAsmInfo *MAI; - if (TheTriple.isOSBinFormatMachO()) { + if (MCTM.isOSBinFormatMachO()) { if (is64Bit) - MAI = new X86_64MCAsmInfoDarwin(TheTriple); + MAI = new X86_64MCAsmInfoDarwin(MCTM); else - MAI = new X86MCAsmInfoDarwin(TheTriple); - } else if (TheTriple.isOSBinFormatELF()) { + MAI = new X86MCAsmInfoDarwin(MCTM); + } else if (MCTM.isOSBinFormatELF()) { // Force the use of an ELF container. - MAI = new X86ELFMCAsmInfo(TheTriple); - } else if (TheTriple.isWindowsMSVCEnvironment() || - TheTriple.isWindowsCoreCLREnvironment()) { - MAI = new X86MCAsmInfoMicrosoft(TheTriple); - } else if (TheTriple.isOSCygMing() || - TheTriple.isWindowsItaniumEnvironment()) { - MAI = new X86MCAsmInfoGNUCOFF(TheTriple); + MAI = new X86ELFMCAsmInfo(MCTM); + } else if (MCTM.isWindowsMSVCEnvironment() || + MCTM.isWindowsCoreCLREnvironment()) { + MAI = new X86MCAsmInfoMicrosoft(MCTM); + } else if (MCTM.isOSCygMing() || MCTM.isWindowsItaniumEnvironment()) { + MAI = new X86MCAsmInfoGNUCOFF(MCTM); } else { // The default is ELF. - MAI = new X86ELFMCAsmInfo(TheTriple); + MAI = new X86ELFMCAsmInfo(MCTM); } // Initialize initial frame state. @@ -230,6 +232,9 @@ // Force static initialization. extern "C" void LLVMInitializeX86TargetMC() { for (Target *T : {&TheX86_32Target, &TheX86_64Target}) { + // Register the MC target machine + RegisterMCTargetMachine Z(*T); + // Register the MC asm info. RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo); Index: lib/Target/X86/MCTargetDesc/X86MCTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/X86/MCTargetDesc/X86MCTargetMachine.h @@ -0,0 +1,78 @@ +//===-- X86MCTargetMachine.h - X86 Target Information -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the MCTargetMachine classes. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_X86_X86MCTARGETMACHINE_H +#define LLVM_LIB_TARGET_X86_X86MCTARGETMACHINE_H + +#include "llvm/MC/MCTargetMachine.h" +#include "llvm/ADT/Triple.h" + +namespace llvm { +class Target; + +class X86MCTargetMachine : public MCTargetMachine { + X86MCTargetMachine(const X86MCTargetMachine &) = delete; + void operator=(const X86MCTargetMachine &) = delete; + + // FIXME: We have this to be able to use the MacOSX version comparison. + // It should not be used as a description of the target. + Triple TheTargetTriple; + + bool IsMachO; + bool IsELF; + bool IsMacOSX; + bool IsOSCygMing; + bool IsWindows; + bool IsWindowsMSVCEnvironment; + bool IsWindowsCoreCLREnvironment; + bool IsWindowsItaniumEnvironment; + bool IsGnuX32Environment; + bool IsArch64Bit; + +public: + X86MCTargetMachine(const Target &T, const Triple &TargetTriple) + : MCTargetMachine(T, TargetTriple), TheTargetTriple(TargetTriple), + IsMachO(TargetTriple.isOSBinFormatMachO()), + IsELF(TargetTriple.isOSBinFormatELF()), + IsMacOSX(TargetTriple.isMacOSX()), + IsOSCygMing(TargetTriple.isOSCygMing()), + IsWindows(TargetTriple.isOSWindows()), + IsWindowsMSVCEnvironment(TargetTriple.isWindowsMSVCEnvironment()), + IsWindowsCoreCLREnvironment(TargetTriple.isWindowsCoreCLREnvironment()), + IsWindowsItaniumEnvironment(TargetTriple.isWindowsItaniumEnvironment()), + IsGnuX32Environment(TargetTriple.getEnvironment() == Triple::GNUX32), + IsArch64Bit(TargetTriple.getArch() == Triple::x86_64) {} + + bool isOSBinFormatELF() const { return IsELF; }; + bool isOSBinFormatMachO() const { return IsMachO; }; + bool isMacOSX() const { return IsMacOSX; } + unsigned isMacOSXVersionLT(unsigned Major, unsigned Minor = 0, + unsigned Micro = 0) const { + return TheTargetTriple.isMacOSXVersionLT(Major, Minor, Micro); + } + bool isOSWindows() const { return IsWindows; } + bool isOSCygMing() const { return IsOSCygMing; } + bool isWindowsItaniumEnvironment() const { + return IsWindowsItaniumEnvironment; + } + bool isWindowsCoreCLREnvironment() const { + return IsWindowsCoreCLREnvironment; + } + bool isWindowsMSVCEnvironment() const { return IsWindowsMSVCEnvironment; } + bool isGnuX32Environment() const { return IsGnuX32Environment; } + bool isArch64Bit() const { return IsArch64Bit; } +}; + +} // End llvm namespace + +#endif Index: lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h =================================================================== --- lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h +++ lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.h @@ -17,13 +17,13 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class Triple; +class MCTargetMachine; class XCoreMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit XCoreMCAsmInfo(const Triple &TT); + explicit XCoreMCAsmInfo(const MCTargetMachine &MCTM); }; } // namespace llvm Index: lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp =================================================================== --- lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp +++ lib/Target/XCore/MCTargetDesc/XCoreMCAsmInfo.cpp @@ -12,7 +12,7 @@ void XCoreMCAsmInfo::anchor() { } -XCoreMCAsmInfo::XCoreMCAsmInfo(const Triple &TT) { +XCoreMCAsmInfo::XCoreMCAsmInfo(const MCTargetMachine &MCTM) { SupportsDebugInformation = true; Data16bitsDirective = "\t.short\t"; Data32bitsDirective = "\t.long\t"; Index: lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp =================================================================== --- lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp +++ lib/Target/XCore/MCTargetDesc/XCoreMCTargetDesc.cpp @@ -19,6 +19,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Support/TargetRegistry.h" @@ -52,8 +53,8 @@ } static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI, - const Triple &TT) { - MCAsmInfo *MAI = new XCoreMCAsmInfo(TT); + const MCTargetMachine &MCTM) { + MCAsmInfo *MAI = new XCoreMCAsmInfo(MCTM); // Initial state of the frame pointer is SP. MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(nullptr, XCore::SP, 0); @@ -133,6 +134,9 @@ // Force static initialization. extern "C" void LLVMInitializeXCoreTargetMC() { + // Register the MC target machine + RegisterMCTargetMachine Y(TheXCoreTarget); + // Register the MC asm info. RegisterMCAsmInfoFn X(TheXCoreTarget, createXCoreMCAsmInfo); Index: tools/dsymutil/DwarfLinker.cpp =================================================================== --- tools/dsymutil/DwarfLinker.cpp +++ tools/dsymutil/DwarfLinker.cpp @@ -31,6 +31,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Object/MachO.h" #include "llvm/Support/Dwarf.h" #include "llvm/Support/LEB128.h" @@ -463,6 +464,7 @@ class DwarfStreamer { /// \defgroup MCObjects MC layer objects constructed by the streamer /// @{ + std::unique_ptr MCTM; std::unique_ptr MRI; std::unique_ptr MAI; std::unique_ptr MOFI; @@ -581,11 +583,16 @@ TripleName = TheTriple.getTriple(); // Create all the MC Objects. + MCTM.reset(TheTarget->createMCTargetMachine(TheTriple)); + if (!MCTM) + return error(Twine("no MC target machine for target ") + TripleName, + Context); + MRI.reset(TheTarget->createMCRegInfo(TripleName)); if (!MRI) return error(Twine("no register info for target ") + TripleName, Context); - MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName)); + MAI.reset(TheTarget->createMCAsmInfo(*MRI, *MCTM)); if (!MAI) return error("no asm info for target " + TripleName, Context); Index: tools/llvm-mc/Disassembler.cpp =================================================================== --- tools/llvm-mc/Disassembler.cpp +++ tools/llvm-mc/Disassembler.cpp @@ -21,6 +21,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/TargetRegistry.h" @@ -130,23 +131,27 @@ return false; } -int Disassembler::disassemble(const Target &T, - const std::string &Triple, - MCSubtargetInfo &STI, - MCStreamer &Streamer, - MemoryBuffer &Buffer, - SourceMgr &SM, +int Disassembler::disassemble(const Target &T, const std::string &TripleStr, + MCSubtargetInfo &STI, MCStreamer &Streamer, + MemoryBuffer &Buffer, SourceMgr &SM, raw_ostream &Out) { + Triple TT(TripleStr); - std::unique_ptr MRI(T.createMCRegInfo(Triple)); + std::unique_ptr MCTM(T.createMCTargetMachine(TT)); + if (!MCTM) { + errs() << "error: no MC target machine for target " << TripleStr << "\n"; + return -1; + } + + std::unique_ptr MRI(T.createMCRegInfo(TripleStr)); if (!MRI) { - errs() << "error: no register info for target " << Triple << "\n"; + errs() << "error: no register info for target " << TripleStr << "\n"; return -1; } - std::unique_ptr MAI(T.createMCAsmInfo(*MRI, Triple)); + std::unique_ptr MAI(T.createMCAsmInfo(*MRI, *MCTM)); if (!MAI) { - errs() << "error: no assembly info for target " << Triple << "\n"; + errs() << "error: no assembly info for target " << TripleStr << "\n"; return -1; } @@ -156,7 +161,7 @@ std::unique_ptr DisAsm( T.createMCDisassembler(STI, Ctx)); if (!DisAsm) { - errs() << "error: no disassembler for target " << Triple << "\n"; + errs() << "error: no disassembler for target " << TripleStr << "\n"; return -1; } Index: tools/llvm-mc/llvm-mc.cpp =================================================================== --- tools/llvm-mc/llvm-mc.cpp +++ tools/llvm-mc/llvm-mc.cpp @@ -25,6 +25,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCTargetAsmParser.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/MC/MCTargetOptionsCommandFlags.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Compression.h" @@ -412,10 +413,14 @@ // it later. SrcMgr.setIncludeDirs(IncludeDirs); + std::unique_ptr MCTM( + TheTarget->createMCTargetMachine(TheTriple)); + assert(MCTM && "Unable to create MC target machine info!"); + std::unique_ptr MRI(TheTarget->createMCRegInfo(TripleName)); assert(MRI && "Unable to create target register info!"); - std::unique_ptr MAI(TheTarget->createMCAsmInfo(*MRI, TripleName)); + std::unique_ptr MAI(TheTarget->createMCAsmInfo(*MRI, *MCTM)); assert(MAI && "Unable to create target asm info!"); if (CompressDebugSections) { Index: tools/llvm-objdump/MachODump.cpp =================================================================== --- tools/llvm-objdump/MachODump.cpp +++ tools/llvm-objdump/MachODump.cpp @@ -28,6 +28,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Object/MachO.h" #include "llvm/Object/MachOUniversal.h" #include "llvm/Support/Casting.h" @@ -5889,10 +5890,13 @@ } // Set up disassembler. + Triple TT(TripleName); + std::unique_ptr MCTM( + TheTarget->createMCTargetMachine(TT)); std::unique_ptr MRI( TheTarget->createMCRegInfo(TripleName)); std::unique_ptr AsmInfo( - TheTarget->createMCAsmInfo(*MRI, TripleName)); + TheTarget->createMCAsmInfo(*MRI, *MCTM)); std::unique_ptr STI( TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr)); MCContext Ctx(AsmInfo.get(), MRI.get(), nullptr); @@ -5910,7 +5914,7 @@ } int AsmPrinterVariant = AsmInfo->getAssemblerDialect(); std::unique_ptr IP(TheTarget->createMCInstPrinter( - Triple(TripleName), AsmPrinterVariant, *AsmInfo, *InstrInfo, *MRI)); + TT, AsmPrinterVariant, *AsmInfo, *InstrInfo, *MRI)); // Set the display preference for hex vs. decimal immediates. IP->setPrintImmHex(PrintImmHex); // Comment stream and backing vector. @@ -5930,6 +5934,7 @@ } // Set up thumb disassembler. + std::unique_ptr ThumbMCTM; std::unique_ptr ThumbMRI; std::unique_ptr ThumbAsmInfo; std::unique_ptr ThumbSTI; @@ -5940,9 +5945,10 @@ struct DisassembleInfo ThumbSymbolizerInfo; std::unique_ptr ThumbRelInfo; if (ThumbTarget) { + Triple ThumbTT(ThumbTripleName); + ThumbMCTM.reset(ThumbTarget->createMCTargetMachine(ThumbTT)); ThumbMRI.reset(ThumbTarget->createMCRegInfo(ThumbTripleName)); - ThumbAsmInfo.reset( - ThumbTarget->createMCAsmInfo(*ThumbMRI, ThumbTripleName)); + ThumbAsmInfo.reset(ThumbTarget->createMCAsmInfo(*ThumbMRI, *ThumbMCTM)); ThumbSTI.reset( ThumbTarget->createMCSubtargetInfo(ThumbTripleName, MCPU, FeaturesStr)); ThumbCtx.reset(new MCContext(ThumbAsmInfo.get(), ThumbMRI.get(), nullptr)); @@ -5958,8 +5964,8 @@ } int ThumbAsmPrinterVariant = ThumbAsmInfo->getAssemblerDialect(); ThumbIP.reset(ThumbTarget->createMCInstPrinter( - Triple(ThumbTripleName), ThumbAsmPrinterVariant, *ThumbAsmInfo, - *ThumbInstrInfo, *ThumbMRI)); + ThumbTT, ThumbAsmPrinterVariant, *ThumbAsmInfo, *ThumbInstrInfo, + *ThumbMRI)); // Set the display preference for hex vs. decimal immediates. ThumbIP->setPrintImmHex(PrintImmHex); } Index: tools/llvm-objdump/llvm-objdump.cpp =================================================================== --- tools/llvm-objdump/llvm-objdump.cpp +++ tools/llvm-objdump/llvm-objdump.cpp @@ -33,6 +33,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCRelocationInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Object/Archive.h" #include "llvm/Object/ELFObjectFile.h" #include "llvm/Object/COFF.h" @@ -809,6 +810,8 @@ if (!TheTarget) return; + Triple TT(TripleName); + // Package up features to be passed to target/subtarget std::string FeaturesStr; if (MAttrs.size()) { @@ -818,6 +821,13 @@ FeaturesStr = Features.getString(); } + std::unique_ptr MCTM( + TheTarget->createMCTargetMachine(TT)); + if (!MCTM) { + errs() << "error: no register info for target " << TripleName << "\n"; + return; + } + std::unique_ptr MRI( TheTarget->createMCRegInfo(TripleName)); if (!MRI) { @@ -827,7 +837,7 @@ // Set up disassembler. std::unique_ptr AsmInfo( - TheTarget->createMCAsmInfo(*MRI, TripleName)); + TheTarget->createMCAsmInfo(*MRI, *MCTM)); if (!AsmInfo) { errs() << "error: no assembly info for target " << TripleName << "\n"; return; Index: tools/llvm-rtdyld/llvm-rtdyld.cpp =================================================================== --- tools/llvm-rtdyld/llvm-rtdyld.cpp +++ tools/llvm-rtdyld/llvm-rtdyld.cpp @@ -24,6 +24,7 @@ #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCTargetMachine.h" #include "llvm/Object/MachO.h" #include "llvm/Object/SymbolSize.h" #include "llvm/Support/CommandLine.h" @@ -590,10 +591,14 @@ TheTarget->createMCSubtargetInfo(TripleName, MCPU, "")); assert(STI && "Unable to create subtarget info!"); + std::unique_ptr MCTM( + TheTarget->createMCTargetMachine(TheTriple)); + assert(MCTM && "Unable to create MC target machine info!"); + std::unique_ptr MRI(TheTarget->createMCRegInfo(TripleName)); assert(MRI && "Unable to create target register info!"); - std::unique_ptr MAI(TheTarget->createMCAsmInfo(*MRI, TripleName)); + std::unique_ptr MAI(TheTarget->createMCAsmInfo(*MRI, *MCTM)); assert(MAI && "Unable to create target asm info!"); MCContext Ctx(MAI.get(), MRI.get(), nullptr);