diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2977,20 +2977,38 @@
   case ARM::t2SBCri:
   case ARM::ANDrr:
   case ARM::ANDri:
+  case ARM::ANDrsr:
+  case ARM::ANDrsi:
   case ARM::t2ANDrr:
   case ARM::t2ANDri:
+  case ARM::t2ANDrs:
   case ARM::ORRrr:
   case ARM::ORRri:
+  case ARM::ORRrsr:
+  case ARM::ORRrsi:
   case ARM::t2ORRrr:
   case ARM::t2ORRri:
+  case ARM::t2ORRrs:
   case ARM::EORrr:
   case ARM::EORri:
+  case ARM::EORrsr:
+  case ARM::EORrsi:
   case ARM::t2EORrr:
   case ARM::t2EORri:
+  case ARM::t2EORrs:
+  case ARM::BICri:
+  case ARM::BICrr:
+  case ARM::BICrsi:
+  case ARM::BICrsr:
+  case ARM::t2BICri:
+  case ARM::t2BICrr:
+  case ARM::t2BICrs:
   case ARM::t2LSRri:
   case ARM::t2LSRrr:
   case ARM::t2LSLri:
   case ARM::t2LSLrr:
+  case ARM::MOVsr:
+  case ARM::MOVsi:
     return true;
   }
 }
@@ -3264,8 +3282,9 @@
   // Toggle the optional operand to CPSR (if it exists - in Thumb1 we always
   // set CPSR so this is represented as an explicit output)
   if (!IsThumb1) {
-    MI->getOperand(5).setReg(ARM::CPSR);
-    MI->getOperand(5).setIsDef(true);
+    unsigned CPSRRegNum = MI->getNumExplicitOperands() - 1;
+    MI->getOperand(CPSRRegNum).setReg(ARM::CPSR);
+    MI->getOperand(CPSRRegNum).setIsDef(true);
   }
   assert(!isPredicated(*MI) && "Can't use flags from predicated instruction");
   CmpInstr.eraseFromParent();
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td
--- a/llvm/lib/Target/ARM/ARMInstrInfo.td
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -4883,14 +4883,13 @@
                         IIC_iCMPi, IIC_iCMPr, IIC_iCMPsr, ARMcmp>;
 
 // ARMcmpZ can re-use the above instruction definitions.
+// There are no patterns with shifted second operand
+// as it will be handeled separately after isel by trying
+// to fuse shift with comparison (by using shift's S-version).
 def : ARMPat<(ARMcmpZ GPR:$src, mod_imm:$imm),
              (CMPri   GPR:$src, mod_imm:$imm)>;
 def : ARMPat<(ARMcmpZ GPR:$src, GPR:$rhs),
              (CMPrr   GPR:$src, GPR:$rhs)>;
-def : ARMPat<(ARMcmpZ GPR:$src, so_reg_imm:$rhs),
-             (CMPrsi   GPR:$src, so_reg_imm:$rhs)>;
-def : ARMPat<(ARMcmpZ GPR:$src, so_reg_reg:$rhs),
-             (CMPrsr   GPR:$src, so_reg_reg:$rhs)>;
 
 // CMN register-integer
 let isCompare = 1, Defs = [CPSR] in {
diff --git a/llvm/test/CodeGen/ARM/branch-on-zero.ll b/llvm/test/CodeGen/ARM/branch-on-zero.ll
--- a/llvm/test/CodeGen/ARM/branch-on-zero.ll
+++ b/llvm/test/CodeGen/ARM/branch-on-zero.ll
@@ -56,19 +56,16 @@
 ;
 ; CHECK-V7A-LABEL: test_lshr:
 ; CHECK-V7A:       @ %bb.0: @ %entry
-; CHECK-V7A-NEXT:    mov r3, #0
-; CHECK-V7A-NEXT:    cmp r3, r2, lsr #2
-; CHECK-V7A-NEXT:    beq .LBB0_3
-; CHECK-V7A-NEXT:  @ %bb.1: @ %while.body.preheader
-; CHECK-V7A-NEXT:    lsr r2, r2, #2
-; CHECK-V7A-NEXT:  .LBB0_2: @ %while.body
+; CHECK-V7A-NEXT:    lsrs r2, r2, #2
+; CHECK-V7A-NEXT:    beq .LBB0_2
+; CHECK-V7A-NEXT:  .LBB0_1: @ %while.body
 ; CHECK-V7A-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-V7A-NEXT:    ldr r3, [r1], #4
 ; CHECK-V7A-NEXT:    subs r2, r2, #1
 ; CHECK-V7A-NEXT:    lsl r3, r3, #1
 ; CHECK-V7A-NEXT:    str r3, [r0], #4
-; CHECK-V7A-NEXT:    bne .LBB0_2
-; CHECK-V7A-NEXT:  .LBB0_3: @ %while.end
+; CHECK-V7A-NEXT:    bne .LBB0_1
+; CHECK-V7A-NEXT:  .LBB0_2: @ %while.end
 ; CHECK-V7A-NEXT:    mov r0, #0
 ; CHECK-V7A-NEXT:    bx lr
 entry:
@@ -145,19 +142,16 @@
 ;
 ; CHECK-V7A-LABEL: test_lshr2:
 ; CHECK-V7A:       @ %bb.0: @ %entry
-; CHECK-V7A-NEXT:    mov r3, #0
-; CHECK-V7A-NEXT:    cmp r3, r2, lsr #2
-; CHECK-V7A-NEXT:    beq .LBB1_3
-; CHECK-V7A-NEXT:  @ %bb.1: @ %while.body.preheader
-; CHECK-V7A-NEXT:    lsr r2, r2, #2
-; CHECK-V7A-NEXT:  .LBB1_2: @ %while.body
+; CHECK-V7A-NEXT:    lsrs r2, r2, #2
+; CHECK-V7A-NEXT:    beq .LBB1_2
+; CHECK-V7A-NEXT:  .LBB1_1: @ %while.body
 ; CHECK-V7A-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-V7A-NEXT:    ldr r3, [r1], #4
 ; CHECK-V7A-NEXT:    subs r2, r2, #1
 ; CHECK-V7A-NEXT:    lsl r3, r3, #1
 ; CHECK-V7A-NEXT:    str r3, [r0], #4
-; CHECK-V7A-NEXT:    bne .LBB1_2
-; CHECK-V7A-NEXT:  .LBB1_3: @ %while.end
+; CHECK-V7A-NEXT:    bne .LBB1_1
+; CHECK-V7A-NEXT:  .LBB1_2: @ %while.end
 ; CHECK-V7A-NEXT:    mov r0, #0
 ; CHECK-V7A-NEXT:    bx lr
 entry:
diff --git a/llvm/test/CodeGen/ARM/cmp-peephole.ll b/llvm/test/CodeGen/ARM/cmp-peephole.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/cmp-peephole.ll
@@ -0,0 +1,589 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=armv7a < %s | FileCheck %s --check-prefix=ARM
+; RUN: llc -mtriple=armv6m < %s | FileCheck %s --check-prefix=THUMB
+; RUN: llc -mtriple=armv7m < %s | FileCheck %s --check-prefix=THUMB2
+
+define i1 @cmp_ne_zero_and_rr(i32 %a, i32 %b) {
+; ARM-LABEL: cmp_ne_zero_and_rr:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    ands r0, r0, r1
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_and_rr:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    ands r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_and_rr:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    ands r0, r1
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+  %and = and i32 %a, %b
+  %res = icmp ne i32 %and, 0
+  ret i1 %res
+}
+
+define i1 @cmp_ne_zero_and_ri(i32 %a) {
+; ARM-LABEL: cmp_ne_zero_and_ri:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    ands r0, r0, #42
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_and_ri:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    movs r1, #42
+; THUMB-NEXT:    ands r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_and_ri:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    ands r0, r0, #42
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+  %and = and i32 %a, 42
+  %res = icmp ne i32 %and, 0
+  ret i1 %res
+}
+
+define i1 @cmp_ne_zero_and_rsr(i32 %a, i32 %b, i32 %c) {
+; ARM-LABEL: cmp_ne_zero_and_rsr:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    ands r0, r0, r1, lsl r2
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_and_rsr:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    lsls r1, r2
+; THUMB-NEXT:    ands r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_and_rsr:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    lsls r1, r2
+; THUMB2-NEXT:    ands r0, r1
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+  %sh = shl i32 %b, %c
+  %and = and i32 %sh, %a
+  %res = icmp ne i32 %and, 0
+  ret i1 %res
+}
+
+define i1 @cmp_ne_zero_and_rsi(i32 %a, i32 %b) {
+; ARM-LABEL: cmp_ne_zero_and_rsi:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    ands r0, r0, r1, lsl #17
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_and_rsi:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    lsls r1, r1, #17
+; THUMB-NEXT:    ands r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_and_rsi:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    ands.w r0, r0, r1, lsl #17
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+  %sh = shl i32 %b, 17
+  %and = and i32 %sh, %a
+  %res = icmp ne i32 %and, 0
+  ret i1 %res
+}
+
+define i1 @cmp_ne_zero_or_rr(i32 %a, i32 %b) {
+; ARM-LABEL: cmp_ne_zero_or_rr:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    orrs r0, r0, r1
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_or_rr:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    orrs r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_or_rr:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    orrs r0, r1
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+  %or = or i32 %a, %b
+  %res = icmp ne i32 %or, 0
+  ret i1 %res
+}
+
+define i1 @cmp_ne_zero_or_ri(i32 %a) {
+; ARM-LABEL: cmp_ne_zero_or_ri:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    orrs r0, r0, #42
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_or_ri:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    movs r1, #42
+; THUMB-NEXT:    orrs r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_or_ri:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    orrs r0, r0, #42
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+  %or = or i32 %a, 42
+  %res = icmp ne i32 %or, 0
+  ret i1 %res
+}
+
+define i1 @cmp_ne_zero_or_rsr(i32 %a, i32 %b, i32 %c) {
+; ARM-LABEL: cmp_ne_zero_or_rsr:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    orrs r0, r0, r1, lsl r2
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_or_rsr:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    lsls r1, r2
+; THUMB-NEXT:    orrs r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_or_rsr:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    lsls r1, r2
+; THUMB2-NEXT:    orrs r0, r1
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+  %sh = shl i32 %b, %c
+  %or = or i32 %sh, %a
+  %res = icmp ne i32 %or, 0
+  ret i1 %res
+}
+
+define i1 @cmp_ne_zero_or_rsi(i32 %a, i32 %b) {
+; ARM-LABEL: cmp_ne_zero_or_rsi:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    orrs r0, r0, r1, lsl #17
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_or_rsi:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    lsls r1, r1, #17
+; THUMB-NEXT:    orrs r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_or_rsi:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    orrs.w r0, r0, r1, lsl #17
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+  %sh = shl i32 %b, 17
+  %or = or i32 %sh, %a
+  %res = icmp ne i32 %or, 0
+  ret i1 %res
+}
+
+define i1 @cmp_ne_zero_xor_rr(i32 %a, i32 %b) {
+; ARM-LABEL: cmp_ne_zero_xor_rr:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    eors r0, r0, r1
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_xor_rr:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    eors r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_xor_rr:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    eors r0, r1
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+  %xor = xor i32 %a, %b
+  %res = icmp ne i32 %xor, 0
+  ret i1 %res
+}
+
+define i1 @cmp_ne_zero_xor_ri(i32 %a) {
+; ARM-LABEL: cmp_ne_zero_xor_ri:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    subs r0, r0, #42
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_xor_ri:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    subs r0, #42
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_xor_ri:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    subs r0, #42
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+  %xor = xor i32 %a, 42
+  %res = icmp ne i32 %xor, 0
+  ret i1 %res
+}
+
+define i1 @cmp_ne_zero_xor_rsr(i32 %a, i32 %b, i32 %c) {
+; ARM-LABEL: cmp_ne_zero_xor_rsr:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    eors r0, r0, r1, lsl r2
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_xor_rsr:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    lsls r1, r2
+; THUMB-NEXT:    eors r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_xor_rsr:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    lsls r1, r2
+; THUMB2-NEXT:    eors r0, r1
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+  %sh = shl i32 %b, %c
+  %xor = xor i32 %sh, %a
+  %res = icmp ne i32 %xor, 0
+  ret i1 %res
+}
+
+define i1 @cmp_ne_zero_xor_rsi(i32 %a, i32 %b) {
+; ARM-LABEL: cmp_ne_zero_xor_rsi:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    eors r0, r0, r1, lsl #17
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_xor_rsi:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    lsls r1, r1, #17
+; THUMB-NEXT:    eors r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_xor_rsi:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    eors.w r0, r0, r1, lsl #17
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+  %sh = shl i32 %b, 17
+  %xor = xor i32 %sh, %a
+  %res = icmp ne i32 %xor, 0
+  ret i1 %res
+}
+
+define i1 @cmp_ne_zero_and_not_rr(i32 %a, i32 %b) {
+; ARM-LABEL: cmp_ne_zero_and_not_rr:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    bics r0, r0, r1
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_and_not_rr:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    bics r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_and_not_rr:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    bics r0, r1
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+  %not = xor i32 %b, -1
+  %and = and i32 %a, %not
+  %res = icmp ne i32 %and, 0
+  ret i1 %res
+}
+
+define i1 @cmp_ne_zero_and_not_ri(i32 %a) {
+; ARM-LABEL: cmp_ne_zero_and_not_ri:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    bics r0, r0, #42
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_and_not_ri:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    movs r1, #42
+; THUMB-NEXT:    bics r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_and_not_ri:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    bics r0, r0, #42
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+  %not = xor i32 42, -1
+  %and = and i32 %a, %not
+  %res = icmp ne i32 %and, 0
+  ret i1 %res
+}
+
+define i1 @cmp_ne_zero_and_not_rsr(i32 %a, i32 %b, i32 %c) {
+; ARM-LABEL: cmp_ne_zero_and_not_rsr:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    mvn r1, r1
+; ARM-NEXT:    ands r0, r0, r1, lsl r2
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_and_not_rsr:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    mvns r1, r1
+; THUMB-NEXT:    lsls r1, r2
+; THUMB-NEXT:    ands r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_and_not_rsr:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    mvns r1, r1
+; THUMB2-NEXT:    lsls r1, r2
+; THUMB2-NEXT:    ands r0, r1
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+  %not = xor i32 %b, -1
+  %sh = shl i32 %not, %c
+  %and = and i32 %sh, %a
+  %res = icmp ne i32 %and, 0
+  ret i1 %res
+}
+
+define i1 @cmp_ne_zero_and_not_rsi(i32 %a, i32 %b) {
+; ARM-LABEL: cmp_ne_zero_and_not_rsi:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    mvn r1, r1
+; ARM-NEXT:    ands r0, r0, r1, lsl #17
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_and_not_rsi:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    mvns r1, r1
+; THUMB-NEXT:    lsls r1, r1, #17
+; THUMB-NEXT:    ands r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_and_not_rsi:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    mvns r1, r1
+; THUMB2-NEXT:    ands.w r0, r0, r1, lsl #17
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+  %not = xor i32 %b, -1
+  %sh = shl i32 %not, 17
+  %and = and i32 %sh, %a
+  %res = icmp ne i32 %and, 0
+  ret i1 %res
+}
+
+define i1 @cmp_ne_zero_shl_rr(i32 %a, i32 %b) {
+; ARM-LABEL: cmp_ne_zero_shl_rr:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    lsls r0, r0, r1
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_shl_rr:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    lsls r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_shl_rr:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    lsls r0, r1
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+    %sh = shl i32 %a, %b
+    %cmp = icmp ne i32 %sh, 0
+    ret i1 %cmp
+}
+
+define i1 @cmp_ne_zero_shl_ri(i32 %a) {
+; ARM-LABEL: cmp_ne_zero_shl_ri:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    lsls r0, r0, #7
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_shl_ri:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    lsls r0, r0, #7
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_shl_ri:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    lsls r0, r0, #7
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+    %sh = shl i32 %a, 7
+    %cmp = icmp ne i32 %sh, 0
+    ret i1 %cmp
+}
+
+define i1 @cmp_ne_zero_lshr_rr(i32 %a, i32 %b) {
+; ARM-LABEL: cmp_ne_zero_lshr_rr:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    lsrs r0, r0, r1
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_lshr_rr:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    lsrs r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_lshr_rr:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    lsrs r0, r1
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+    %sh = lshr i32 %a, %b
+    %cmp = icmp ne i32 %sh, 0
+    ret i1 %cmp
+}
+
+define i1 @cmp_ne_zero_lshr_ri(i32 %a) {
+; ARM-LABEL: cmp_ne_zero_lshr_ri:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    lsrs r0, r0, #7
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_lshr_ri:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    lsrs r0, r0, #7
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_lshr_ri:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    lsrs r0, r0, #7
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+    %sh = lshr i32 %a, 7
+    %cmp = icmp ne i32 %sh, 0
+    ret i1 %cmp
+}
+
+define i1 @cmp_ne_zero_ashr_rr(i32 %a, i32 %b) {
+; ARM-LABEL: cmp_ne_zero_ashr_rr:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    asrs r0, r0, r1
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_ashr_rr:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    asrs r0, r1
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_ashr_rr:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    asrs r0, r1
+; THUMB2-NEXT:    cmp r0, #0
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+    %sh = ashr i32 %a, %b
+    %cmp = icmp ne i32 %sh, 0
+    ret i1 %cmp
+}
+
+define i1 @cmp_ne_zero_ashr_ri(i32 %a) {
+; ARM-LABEL: cmp_ne_zero_ashr_ri:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    asrs r0, r0, #7
+; ARM-NEXT:    movwne r0, #1
+; ARM-NEXT:    bx lr
+;
+; THUMB-LABEL: cmp_ne_zero_ashr_ri:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    asrs r0, r0, #7
+; THUMB-NEXT:    subs r1, r0, #1
+; THUMB-NEXT:    sbcs r0, r1
+; THUMB-NEXT:    bx lr
+;
+; THUMB2-LABEL: cmp_ne_zero_ashr_ri:
+; THUMB2:       @ %bb.0:
+; THUMB2-NEXT:    asrs r0, r0, #7
+; THUMB2-NEXT:    cmp r0, #0
+; THUMB2-NEXT:    it ne
+; THUMB2-NEXT:    movne r0, #1
+; THUMB2-NEXT:    bx lr
+    %sh = ashr i32 %a, 7
+    %cmp = icmp ne i32 %sh, 0
+    ret i1 %cmp
+}
diff --git a/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll b/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
--- a/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
+++ b/llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
@@ -630,20 +630,17 @@
 ; CHECKV7M-NEXT:    ldrd lr, r0, [sp, #8]
 ; CHECKV7M-NEXT:    beq .LBB6_2
 ; CHECKV7M-NEXT:  @ %bb.1: @ %then
-; CHECKV7M-NEXT:    orr.w r2, r3, r2, lsr #17
-; CHECKV7M-NEXT:    orr.w r1, r1, r12, lsr #17
-; CHECKV7M-NEXT:    cmp r2, #0
+; CHECKV7M-NEXT:    orrs.w r2, r3, r2, lsr #17
 ; CHECKV7M-NEXT:    mov r2, r0
 ; CHECKV7M-NEXT:    it ne
 ; CHECKV7M-NEXT:    movne r2, lr
-; CHECKV7M-NEXT:    cmp r1, #0
+; CHECKV7M-NEXT:    orrs.w r1, r1, r12, lsr #17
 ; CHECKV7M-NEXT:    it ne
 ; CHECKV7M-NEXT:    movne r0, lr
 ; CHECKV7M-NEXT:    add r0, r2
 ; CHECKV7M-NEXT:    pop {r7, pc}
 ; CHECKV7M-NEXT:  .LBB6_2: @ %else
-; CHECKV7M-NEXT:    orr.w r1, r3, r2, lsr #17
-; CHECKV7M-NEXT:    cmp r1, #0
+; CHECKV7M-NEXT:    orrs.w r1, r3, r2, lsr #17
 ; CHECKV7M-NEXT:    it ne
 ; CHECKV7M-NEXT:    movne r0, lr
 ; CHECKV7M-NEXT:    pop {r7, pc}
@@ -658,20 +655,17 @@
 ; CHECKV7A-NEXT:    lsls r4, r4, #31
 ; CHECKV7A-NEXT:    beq .LBB6_2
 ; CHECKV7A-NEXT:  @ %bb.1: @ %then
-; CHECKV7A-NEXT:    orr.w r2, r3, r2, lsr #17
-; CHECKV7A-NEXT:    orr.w r1, r1, r12, lsr #17
-; CHECKV7A-NEXT:    cmp r2, #0
+; CHECKV7A-NEXT:    orrs.w r2, r3, r2, lsr #17
 ; CHECKV7A-NEXT:    mov r2, r0
 ; CHECKV7A-NEXT:    it ne
 ; CHECKV7A-NEXT:    movne r2, lr
-; CHECKV7A-NEXT:    cmp r1, #0
+; CHECKV7A-NEXT:    orrs.w r1, r1, r12, lsr #17
 ; CHECKV7A-NEXT:    it ne
 ; CHECKV7A-NEXT:    movne r0, lr
 ; CHECKV7A-NEXT:    add r0, r2
 ; CHECKV7A-NEXT:    pop {r4, pc}
 ; CHECKV7A-NEXT:  .LBB6_2: @ %else
-; CHECKV7A-NEXT:    orr.w r1, r3, r2, lsr #17
-; CHECKV7A-NEXT:    cmp r1, #0
+; CHECKV7A-NEXT:    orrs.w r1, r3, r2, lsr #17
 ; CHECKV7A-NEXT:    it ne
 ; CHECKV7A-NEXT:    movne r0, lr
 ; CHECKV7A-NEXT:    pop {r4, pc}
diff --git a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
--- a/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
+++ b/llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
@@ -970,9 +970,8 @@
 ; ARM6:       @ %bb.0:
 ; ARM6-NEXT:    uxtb r1, r1
 ; ARM6-NEXT:    mov r2, #24
-; ARM6-NEXT:    and r1, r0, r2, lsr r1
+; ARM6-NEXT:    ands r0, r0, r2, lsr r1
 ; ARM6-NEXT:    mov r0, #0
-; ARM6-NEXT:    cmp r1, #0
 ; ARM6-NEXT:    movmi r0, #1
 ; ARM6-NEXT:    bx lr
 ;
@@ -980,9 +979,8 @@
 ; ARM78:       @ %bb.0:
 ; ARM78-NEXT:    uxtb r1, r1
 ; ARM78-NEXT:    mov r2, #24
-; ARM78-NEXT:    and r1, r0, r2, lsr r1
+; ARM78-NEXT:    ands r0, r0, r2, lsr r1
 ; ARM78-NEXT:    mov r0, #0
-; ARM78-NEXT:    cmp r1, #0
 ; ARM78-NEXT:    movwmi r0, #1
 ; ARM78-NEXT:    bx lr
 ;
diff --git a/llvm/test/CodeGen/ARM/icmp-shift-opt.ll b/llvm/test/CodeGen/ARM/icmp-shift-opt.ll
--- a/llvm/test/CodeGen/ARM/icmp-shift-opt.ll
+++ b/llvm/test/CodeGen/ARM/icmp-shift-opt.ll
@@ -12,8 +12,7 @@
 ; CHECK-NEXT:    @ =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    adds r0, r0, #1
 ; CHECK-NEXT:    adc r1, r1, #0
-; CHECK-NEXT:    orr r2, r1, r0, lsr #16
-; CHECK-NEXT:    cmp r2, #0
+; CHECK-NEXT:    orrs r2, r1, r0, lsr #16
 ; CHECK-NEXT:    bne .LBB0_1
 ; CHECK-NEXT:  @ %bb.2: @ %exit
 ; CHECK-NEXT:    bx lr
@@ -44,8 +43,7 @@
 define i1 @opt_setcc_srl_ne_zero(i64 %a) nounwind {
 ; CHECK-LABEL: opt_setcc_srl_ne_zero:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    orr r0, r1, r0, lsr #17
-; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    orrs r0, r1, r0, lsr #17
 ; CHECK-NEXT:    movwne r0, #1
 ; CHECK-NEXT:    bx lr
    %srl = lshr i64 %a, 17
@@ -68,8 +66,7 @@
 define i1 @opt_setcc_shl_ne_zero(i64 %a) nounwind {
 ; CHECK-LABEL: opt_setcc_shl_ne_zero:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    orr r0, r0, r1, lsl #17
-; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    orrs r0, r0, r1, lsl #17
 ; CHECK-NEXT:    movwne r0, #1
 ; CHECK-NEXT:    bx lr
    %shl = shl i64 %a, 17
@@ -144,8 +141,7 @@
 ; CHECK-NEXT:    orr r2, r0, r3
 ; CHECK-NEXT:    orr r0, r0, r1
 ; CHECK-NEXT:    lsr r0, r0, #15
-; CHECK-NEXT:    orr r0, r0, r2, lsl #17
-; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    orrs r0, r0, r2, lsl #17
 ; CHECK-NEXT:    movwne r0, #1
 ; CHECK-NEXT:    bx lr
   %shl = shl i128 %a, 17
diff --git a/llvm/test/CodeGen/ARM/sadd_sat.ll b/llvm/test/CodeGen/ARM/sadd_sat.ll
--- a/llvm/test/CodeGen/ARM/sadd_sat.ll
+++ b/llvm/test/CodeGen/ARM/sadd_sat.ll
@@ -94,11 +94,10 @@
 ; CHECK-T2-NEXT:    eor.w r12, r1, r3
 ; CHECK-T2-NEXT:    adc.w r2, r1, r3
 ; CHECK-T2-NEXT:    eors r1, r2
-; CHECK-T2-NEXT:    bic.w r1, r1, r12
-; CHECK-T2-NEXT:    cmp r1, #0
-; CHECK-T2-NEXT:    mov.w r1, #-2147483648
+; CHECK-T2-NEXT:    bics.w r1, r1, r12
 ; CHECK-T2-NEXT:    it mi
 ; CHECK-T2-NEXT:    asrmi r0, r2, #31
+; CHECK-T2-NEXT:    mov.w r1, #-2147483648
 ; CHECK-T2-NEXT:    it mi
 ; CHECK-T2-NEXT:    eormi.w r2, r1, r2, asr #31
 ; CHECK-T2-NEXT:    mov r1, r2
@@ -110,10 +109,9 @@
 ; CHECK-ARM-NEXT:    eor r12, r1, r3
 ; CHECK-ARM-NEXT:    adc r2, r1, r3
 ; CHECK-ARM-NEXT:    eor r1, r1, r2
-; CHECK-ARM-NEXT:    bic r1, r1, r12
-; CHECK-ARM-NEXT:    cmp r1, #0
-; CHECK-ARM-NEXT:    mov r1, #-2147483648
+; CHECK-ARM-NEXT:    bics r1, r1, r12
 ; CHECK-ARM-NEXT:    asrmi r0, r2, #31
+; CHECK-ARM-NEXT:    mov r1, #-2147483648
 ; CHECK-ARM-NEXT:    eormi r2, r1, r2, asr #31
 ; CHECK-ARM-NEXT:    mov r1, r2
 ; CHECK-ARM-NEXT:    bx lr
diff --git a/llvm/test/CodeGen/ARM/sadd_sat_plus.ll b/llvm/test/CodeGen/ARM/sadd_sat_plus.ll
--- a/llvm/test/CodeGen/ARM/sadd_sat_plus.ll
+++ b/llvm/test/CodeGen/ARM/sadd_sat_plus.ll
@@ -91,10 +91,9 @@
 ; CHECK-T2-NEXT:    eor.w r3, r1, r12
 ; CHECK-T2-NEXT:    eors r1, r2
 ; CHECK-T2-NEXT:    bics r1, r3
-; CHECK-T2-NEXT:    cmp r1, #0
-; CHECK-T2-NEXT:    mov.w r1, #-2147483648
 ; CHECK-T2-NEXT:    it mi
 ; CHECK-T2-NEXT:    asrmi r0, r2, #31
+; CHECK-T2-NEXT:    mov.w r1, #-2147483648
 ; CHECK-T2-NEXT:    it mi
 ; CHECK-T2-NEXT:    eormi.w r2, r1, r2, asr #31
 ; CHECK-T2-NEXT:    mov r1, r2
@@ -108,10 +107,9 @@
 ; CHECK-ARM-NEXT:    eor r3, r1, r2
 ; CHECK-ARM-NEXT:    adc r2, r1, r2
 ; CHECK-ARM-NEXT:    eor r1, r1, r2
-; CHECK-ARM-NEXT:    bic r1, r1, r3
-; CHECK-ARM-NEXT:    cmp r1, #0
-; CHECK-ARM-NEXT:    mov r1, #-2147483648
+; CHECK-ARM-NEXT:    bics r1, r1, r3
 ; CHECK-ARM-NEXT:    asrmi r0, r2, #31
+; CHECK-ARM-NEXT:    mov r1, #-2147483648
 ; CHECK-ARM-NEXT:    eormi r2, r1, r2, asr #31
 ; CHECK-ARM-NEXT:    mov r1, r2
 ; CHECK-ARM-NEXT:    bx lr
diff --git a/llvm/test/CodeGen/ARM/sat-to-bitop.ll b/llvm/test/CodeGen/ARM/sat-to-bitop.ll
--- a/llvm/test/CodeGen/ARM/sat-to-bitop.ll
+++ b/llvm/test/CodeGen/ARM/sat-to-bitop.ll
@@ -37,8 +37,7 @@
 ; CHECK-ARM-LABEL: sat0_base_16bit:
 ; CHECK-ARM:       @ %bb.0: @ %entry
 ; CHECK-ARM-NEXT:    lsl r1, r0, #16
-; CHECK-ARM-NEXT:    asr r1, r1, #16
-; CHECK-ARM-NEXT:    cmp r1, #0
+; CHECK-ARM-NEXT:    asrs r1, r1, #16
 ; CHECK-ARM-NEXT:    movmi r0, #0
 ; CHECK-ARM-NEXT:    mov pc, lr
 ;
@@ -71,8 +70,7 @@
 ; CHECK-ARM-LABEL: sat0_base_8bit:
 ; CHECK-ARM:       @ %bb.0: @ %entry
 ; CHECK-ARM-NEXT:    lsl r1, r0, #24
-; CHECK-ARM-NEXT:    asr r1, r1, #24
-; CHECK-ARM-NEXT:    cmp r1, #0
+; CHECK-ARM-NEXT:    asrs r1, r1, #24
 ; CHECK-ARM-NEXT:    movmi r0, #0
 ; CHECK-ARM-NEXT:    mov pc, lr
 ;
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
@@ -39,10 +39,10 @@
 ; CHECK-NEXT:    vcmla.f32 q0, q1, q2, #90
 ; CHECK-NEXT:    vldrw.u32 q1, [r1, #-16]
 ; CHECK-NEXT:    vldrw.u32 q2, [r0, #-16]
-; CHECK-NEXT:    and.w r2, r4, r2, lsl #1
+; CHECK-NEXT:    ands.w r2, r4, r2, lsl #1
 ; CHECK-NEXT:    vcmla.f32 q0, q2, q1, #0
 ; CHECK-NEXT:    vcmla.f32 q0, q2, q1, #90
-; CHECK-NEXT:    cbz r2, .LBB0_8
+; CHECK-NEXT:    beq .LBB0_8
 ; CHECK-NEXT:  @ %bb.4: @ %while.body9
 ; CHECK-NEXT:    vctp.32 r2
 ; CHECK-NEXT:    cmp r2, #4
diff --git a/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll b/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
--- a/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
@@ -335,39 +335,36 @@
 ; CHECK-NEXT:    vmov.f32 s10, s7
 ; CHECK-NEXT:    vmov r10, s8
 ; CHECK-NEXT:    vmov.f32 s8, s6
-; CHECK-NEXT:    vmov r6, s2
+; CHECK-NEXT:    vmov r7, s2
 ; CHECK-NEXT:    vmov.f32 s2, s1
 ; CHECK-NEXT:    vmov.f32 s6, s5
 ; CHECK-NEXT:    vmov r2, s8
 ; CHECK-NEXT:    asr.w r0, r10, #31
-; CHECK-NEXT:    asrs r7, r6, #31
+; CHECK-NEXT:    asrs r5, r7, #31
 ; CHECK-NEXT:    adds.w r4, r10, r2
+; CHECK-NEXT:    eor.w r6, r10, r2
 ; CHECK-NEXT:    adc r3, r0, #0
 ; CHECK-NEXT:    asrl r4, r3, r2
 ; CHECK-NEXT:    subs r0, r4, r2
 ; CHECK-NEXT:    sbc lr, r3, #0
 ; CHECK-NEXT:    vmov r3, s10
 ; CHECK-NEXT:    umull r0, r8, r0, r2
-; CHECK-NEXT:    adds r4, r6, r3
-; CHECK-NEXT:    eor.w r1, r6, r3
-; CHECK-NEXT:    adc r5, r7, #0
-; CHECK-NEXT:    eor.w r7, r10, r2
+; CHECK-NEXT:    adds r4, r7, r3
+; CHECK-NEXT:    eor.w r1, r7, r3
+; CHECK-NEXT:    adc r5, r5, #0
 ; CHECK-NEXT:    asrl r4, r5, r3
-; CHECK-NEXT:    orr.w r7, r7, r10, asr #31
 ; CHECK-NEXT:    subs r4, r4, r3
-; CHECK-NEXT:    orr.w r1, r1, r6, asr #31
 ; CHECK-NEXT:    sbc r5, r5, #0
-; CHECK-NEXT:    cmp r7, #0
+; CHECK-NEXT:    orrs.w r6, r6, r10, asr #31
 ; CHECK-NEXT:    umull r4, r12, r4, r3
 ; CHECK-NEXT:    csetm r9, eq
-; CHECK-NEXT:    movs r7, #0
-; CHECK-NEXT:    cmp r1, #0
-; CHECK-NEXT:    bfi r7, r9, #0, #8
+; CHECK-NEXT:    orrs.w r1, r1, r7, asr #31
+; CHECK-NEXT:    mov.w r6, #0
 ; CHECK-NEXT:    csetm r1, eq
-; CHECK-NEXT:    bfi r7, r1, #8, #8
+; CHECK-NEXT:    bfi r6, r9, #0, #8
 ; CHECK-NEXT:    mla r5, r5, r3, r12
-; CHECK-NEXT:    rsbs r1, r6, #0
-; CHECK-NEXT:    vmsr p0, r7
+; CHECK-NEXT:    bfi r6, r1, #8, #8
+; CHECK-NEXT:    rsbs r1, r7, #0
 ; CHECK-NEXT:    mla r7, lr, r2, r8
 ; CHECK-NEXT:    lsll r4, r5, r1
 ; CHECK-NEXT:    rsb.w r1, r10, #0
@@ -376,8 +373,9 @@
 ; CHECK-NEXT:    vmov r1, s6
 ; CHECK-NEXT:    lsll r0, r7, r2
 ; CHECK-NEXT:    lsll r4, r5, r3
-; CHECK-NEXT:    mov.w r12, #0
+; CHECK-NEXT:    vmsr p0, r6
 ; CHECK-NEXT:    vmov q3[2], q3[0], r0, r4
+; CHECK-NEXT:    mov.w r12, #0
 ; CHECK-NEXT:    vpsel q2, q3, q2
 ; CHECK-NEXT:    adds.w r2, lr, r1
 ; CHECK-NEXT:    asr.w r0, lr, #31
@@ -396,12 +394,10 @@
 ; CHECK-NEXT:    sbc r8, r5, #0
 ; CHECK-NEXT:    mla r5, r7, r1, r6
 ; CHECK-NEXT:    eor.w r6, lr, r1
-; CHECK-NEXT:    orr.w r6, r6, lr, asr #31
+; CHECK-NEXT:    orrs.w r6, r6, lr, asr #31
 ; CHECK-NEXT:    eor.w r7, r2, r3
-; CHECK-NEXT:    cmp r6, #0
-; CHECK-NEXT:    orr.w r7, r7, r2, asr #31
 ; CHECK-NEXT:    csetm r6, eq
-; CHECK-NEXT:    cmp r7, #0
+; CHECK-NEXT:    orrs.w r7, r7, r2, asr #31
 ; CHECK-NEXT:    csetm r7, eq
 ; CHECK-NEXT:    rsb.w lr, lr, #0
 ; CHECK-NEXT:    bfi r12, r7, #0, #8