Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -772,16 +772,6 @@
            VK == RISCVMCExpr::VK_RISCV_None;
   }
 
-  bool isSImm5Plus1NonZero() const {
-    if (!isImm())
-      return false;
-    RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
-    int64_t Imm;
-    bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
-    return (Imm != 0) && IsConstantImm && isInt<5>(Imm - 1) &&
-           VK == RISCVMCExpr::VK_RISCV_None;
-  }
-
   /// getStartLoc - Gets location of the first token of this operand
   SMLoc getStartLoc() const override { return StartLoc; }
   /// getEndLoc - Gets location of the last token of this operand
@@ -1289,11 +1279,6 @@
                                       (1 << 4),
                                       "immediate must be in the range");
   }
-  case Match_InvalidSImm5Plus1NonZero: {
-    return generateImmOutOfRangeError(
-        Operands, ErrorInfo, -(1 << 4) + 1, (1 << 4),
-        "immediate must be not 0 and be in the range");
-  }
   case Match_InvalidRnumArg: {
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 10);
   }
Index: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
===================================================================
--- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
+++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
@@ -216,7 +216,6 @@
   OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET,
   OPERAND_UIMM2 = OPERAND_FIRST_RISCV_IMM,
   OPERAND_UIMM3,
-
   OPERAND_UIMM4,
   OPERAND_UIMM5,
   OPERAND_UIMM7,
@@ -227,7 +226,6 @@
   OPERAND_ZERO,
   OPERAND_SIMM5,
   OPERAND_SIMM5_PLUS1,
-  OPERAND_SIMM5_PLUS1_NONZERO,
   OPERAND_SIMM6,
   OPERAND_SIMM6_NONZERO,
   OPERAND_SIMM12,
@@ -236,8 +234,8 @@
   OPERAND_UIMMLOG2XLEN,
   OPERAND_UIMMLOG2XLEN_NONZERO,
   OPERAND_UIMM_SHFL,
-  OPERAND_VI10,
-  OPERAND_VI11,
+  OPERAND_VTYPEI10,
+  OPERAND_VTYPEI11,
   OPERAND_RVKRNUM,
   OPERAND_LAST_RISCV_IMM = OPERAND_RVKRNUM,
   // Operand is either a register or uimm5, this is used by V extension pseudo
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1146,19 +1146,16 @@
         case RISCVOp::OPERAND_SIMM5_PLUS1:
           Ok = (isInt<5>(Imm) && Imm != -16) || Imm == 16;
           break;
-        case RISCVOp::OPERAND_SIMM5_PLUS1_NONZERO:
-          Ok = Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);
-          break;
         case RISCVOp::OPERAND_SIMM6:
           Ok = isInt<6>(Imm);
           break;
         case RISCVOp::OPERAND_SIMM6_NONZERO:
           Ok = Imm != 0 && isInt<6>(Imm);
           break;
-        case RISCVOp::OPERAND_VI10:
+        case RISCVOp::OPERAND_VTYPEI10:
           Ok = isUInt<10>(Imm);
           break;
-        case RISCVOp::OPERAND_VI11:
+        case RISCVOp::OPERAND_VTYPEI11:
           Ok = isUInt<11>(Imm);
           break;
         case RISCVOp::OPERAND_SIMM12:
Index: llvm/lib/Target/RISCV/RISCVInstrInfoV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -28,7 +28,7 @@
   let ParserMatchClass = VTypeIAsmOperand<VTypeINum>;
   let PrintMethod = "printVTypeI";
   let DecoderMethod = "decodeUImmOperand<"#VTypeINum#">";
-  let OperandType = "OPERAND_VI" # VTypeINum;
+  let OperandType = "OPERAND_VTYPEI" # VTypeINum;
   let OperandNamespace = "RISCVOp";
   let MCOperandPredicate = [{
     int64_t Imm;
@@ -38,8 +38,8 @@
   }];
 }
 
-def VTypeIOp10 : VTypeIOp<10>, ImmLeaf<XLenVT, [{return isUInt<10>(Imm);}]>;
-def VTypeIOp11 : VTypeIOp<11>, ImmLeaf<XLenVT, [{return isUInt<11>(Imm);}]>;
+def VTypeIOp10 : VTypeIOp<10>;
+def VTypeIOp11 : VTypeIOp<11>;
 
 def VMaskAsmOperand : AsmOperandClass {
   let Name = "RVVMaskRegOpOperand";
@@ -91,25 +91,8 @@
   }];
 }
 
-
-def SImm5Plus1NonZeroAsmOperand : AsmOperandClass {
-  let Name = "SImm5Plus1NonZero";
-  let RenderMethod = "addImmOperands";
-  let DiagnosticType = "InvalidSImm5Plus1NonZero";
-}
-
-def simm5_plus1_nonzero : Operand<XLenVT>, ImmLeaf<XLenVT,
-  [{return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);}]> {
-  let ParserMatchClass = SImm5Plus1NonZeroAsmOperand;
-  let OperandType = "OPERAND_SIMM5_PLUS1_NONZERO";
-  let OperandNamespace = "RISCVOp";
-  let MCOperandPredicate = [{
-    int64_t Imm;
-    if (MCOp.evaluateAsConstantImm(Imm))
-      return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);
-    return MCOp.isBareSymbolRef();
-  }];
-}
+def simm5_plus1_nonzero : ImmLeaf<XLenVT,
+  [{return Imm != 0 && ((isInt<5>(Imm) && Imm != -16) || Imm == 16);}]>;
 
 //===----------------------------------------------------------------------===//
 // Scheduling definitions.