diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -191,6 +191,12 @@ - ... +RISC-V Support in Clang +----------------------- + +- ``sifive-7-rv32`` and ``sifive-7-rv64`` are no longer supported for `-mcpu`. + Use `sifive-e76`, `sifive-s76`, or `sifive-u74` instead. + X86 Support in Clang -------------------- diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -2190,10 +2190,8 @@ SetRISCVSmallDataLimit(getToolChain(), Args, CmdArgs); if (const Arg *A = Args.getLastArg(options::OPT_mtune_EQ)) { - StringRef Name = - llvm::RISCV::resolveTuneCPUAlias(A->getValue(), Triple.isArch64Bit()); CmdArgs.push_back("-tune-cpu"); - CmdArgs.push_back(Name.data()); + CmdArgs.push_back(A->getValue()); } } diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -7,43 +7,24 @@ // MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64" // MCPU-ROCKET64: "-target-feature" "+64bit" -// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=sifive-7-rv32 | FileCheck -check-prefix=MCPU-SIFIVE7-32 %s -// MCPU-SIFIVE7-32: "-nostdsysteminc" "-target-cpu" "sifive-7-rv32" - -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-7-rv64 | FileCheck -check-prefix=MCPU-SIFIVE7-64 %s -// MCPU-SIFIVE7-64: "-nostdsysteminc" "-target-cpu" "sifive-7-rv64" -// MCPU-SIFIVE7-64: "-target-feature" "+64bit" - // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=rocket-rv32 | FileCheck -check-prefix=MTUNE-ROCKET32 %s // MTUNE-ROCKET32: "-tune-cpu" "rocket-rv32" // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket-rv64 | FileCheck -check-prefix=MTUNE-ROCKET64 %s // MTUNE-ROCKET64: "-tune-cpu" "rocket-rv64" -// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=sifive-7-rv32 | FileCheck -check-prefix=MTUNE-SIFIVE7-32 %s -// MTUNE-SIFIVE7-32: "-tune-cpu" "sifive-7-rv32" - -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=sifive-7-rv64 | FileCheck -check-prefix=MTUNE-SIFIVE7-64 %s -// MTUNE-SIFIVE7-64: "-tune-cpu" "sifive-7-rv64" - // Check mtune alias CPU has resolved to the right CPU according XLEN. // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-32 %s -// MTUNE-GENERIC-32: "-tune-cpu" "generic-rv32" +// MTUNE-GENERIC-32: "-tune-cpu" "generic" // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=generic | FileCheck -check-prefix=MTUNE-GENERIC-64 %s -// MTUNE-GENERIC-64: "-tune-cpu" "generic-rv64" +// MTUNE-GENERIC-64: "-tune-cpu" "generic" // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=rocket | FileCheck -check-prefix=MTUNE-ROCKET-32 %s -// MTUNE-ROCKET-32: "-tune-cpu" "rocket-rv32" +// MTUNE-ROCKET-32: "-tune-cpu" "rocket" // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=rocket | FileCheck -check-prefix=MTUNE-ROCKET-64 %s -// MTUNE-ROCKET-64: "-tune-cpu" "rocket-rv64" - -// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=sifive-7-series | FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-32 %s -// MTUNE-SIFIVE7-SERIES-32: "-tune-cpu" "sifive-7-rv32" - -// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s -// MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64" +// MTUNE-ROCKET-64: "-tune-cpu" "rocket" // mcpu with default march // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e20 | FileCheck -check-prefix=MCPU-SIFIVE-E20 %s diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -81,16 +81,16 @@ // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32 // RISCV32: error: unknown target CPU 'not-a-cpu' -// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76{{$}} +// RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76{{$}} // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu' -// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74{{$}} +// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74{{$}} // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, generic, rocket, sifive-7-series{{$}} +// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, generic, rocket, sifive-7-series{{$}} // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu' -// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, generic, rocket, sifive-7-series{{$}} +// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, generic, rocket, sifive-7-series{{$}} diff --git a/llvm/include/llvm/Support/RISCVTargetParser.def b/llvm/include/llvm/Support/RISCVTargetParser.def --- a/llvm/include/llvm/Support/RISCVTargetParser.def +++ b/llvm/include/llvm/Support/RISCVTargetParser.def @@ -1,13 +1,3 @@ -#ifndef TUNE_ALIAS -#define TUNE_ALIAS(NAME, RV32, RV64) -#endif - -TUNE_ALIAS("generic", "generic-rv32", "generic-rv64") -TUNE_ALIAS("rocket", "rocket-rv32", "rocket-rv64") -TUNE_ALIAS("sifive-7-series", "sifive-7-rv32", "sifive-7-rv64") - -#undef TUNE_ALIAS - #ifndef PROC #define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) #endif @@ -17,8 +7,6 @@ PROC(GENERIC_RV64, {"generic-rv64"}, FK_64BIT, {""}) PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {""}) PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""}) -PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""}) -PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""}) PROC(SIFIVE_E20, {"sifive-e20"}, FK_NONE, {"rv32imc"}) PROC(SIFIVE_E21, {"sifive-e21"}, FK_NONE, {"rv32imac"}) PROC(SIFIVE_E24, {"sifive-e24"}, FK_NONE, {"rv32imafc"}) @@ -33,3 +21,13 @@ PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"}) #undef PROC + +#ifndef TUNE_PROC +#define TUNE_PROC(ENUM, NAME) +#endif + +TUNE_PROC(GENERIC, "generic") +TUNE_PROC(ROCKET, "rocket") +TUNE_PROC(SIFIVE_7, "sifive-7-series") + +#undef TUNE_PROC diff --git a/llvm/include/llvm/Support/TargetParser.h b/llvm/include/llvm/Support/TargetParser.h --- a/llvm/include/llvm/Support/TargetParser.h +++ b/llvm/include/llvm/Support/TargetParser.h @@ -159,6 +159,7 @@ enum CPUKind : unsigned { #define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) CK_##ENUM, +#define TUNE_PROC(ENUM, NAME) CK_##ENUM, #include "RISCVTargetParser.def" }; @@ -176,7 +177,6 @@ void fillValidCPUArchList(SmallVectorImpl &Values, bool IsRV64); void fillValidTuneCPUArchList(SmallVectorImpl &Values, bool IsRV64); bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector &Features); -StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64); } // namespace RISCV diff --git a/llvm/lib/Support/TargetParser.cpp b/llvm/lib/Support/TargetParser.cpp --- a/llvm/lib/Support/TargetParser.cpp +++ b/llvm/lib/Support/TargetParser.cpp @@ -278,6 +278,8 @@ bool checkTuneCPUKind(CPUKind Kind, bool IsRV64) { if (Kind == CK_INVALID) return false; +#define TUNE_PROC(ENUM, NAME) if (Kind == CK_##ENUM) return true; +#include "llvm/Support/RISCVTargetParser.def" return RISCVCPUInfo[static_cast(Kind)].is64Bit() == IsRV64; } @@ -288,18 +290,10 @@ .Default(CK_INVALID); } -StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64) { - return llvm::StringSwitch(TuneCPU) -#define TUNE_ALIAS(NAME, RV32, RV64) .Case(NAME, IsRV64 ? StringRef(RV64) : StringRef(RV32)) -#include "llvm/Support/RISCVTargetParser.def" - .Default(TuneCPU); -} - CPUKind parseTuneCPUKind(StringRef TuneCPU, bool IsRV64) { - TuneCPU = resolveTuneCPUAlias(TuneCPU, IsRV64); - return llvm::StringSwitch(TuneCPU) #define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) .Case(NAME, CK_##ENUM) +#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM) #include "llvm/Support/RISCVTargetParser.def" .Default(CK_INVALID); } @@ -321,7 +315,7 @@ if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit()) Values.emplace_back(C.Name); } -#define TUNE_ALIAS(NAME, RV32, RV64) Values.emplace_back(StringRef(NAME)); +#define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME)); #include "llvm/Support/RISCVTargetParser.def" } diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp @@ -97,10 +97,13 @@ void validate(const Triple &TT, const FeatureBitset &FeatureBits) { if (TT.isArch64Bit() && !FeatureBits[RISCV::Feature64Bit]) report_fatal_error("RV64 target requires an RV64 CPU"); - if (!TT.isArch64Bit() && FeatureBits[RISCV::Feature64Bit]) + if (!TT.isArch64Bit() && !FeatureBits[RISCV::Feature32Bit]) report_fatal_error("RV32 target requires an RV32 CPU"); if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E]) report_fatal_error("RV32E can't be enabled for an RV64 target"); + if (FeatureBits[RISCV::Feature32Bit] && + FeatureBits[RISCV::Feature64Bit]) + report_fatal_error("RV32 and RV64 can't be combined"); } llvm::Expected> diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -447,6 +447,10 @@ AssemblerPredicate<(all_of FeatureStdExtZicbop), "'Zicbop' (Cache-Block Prefetch Instructions)">; +// Feature32Bit exists to mark CPUs that support RV32 to distinquish them from +// tuning CPU names. +def Feature32Bit + : SubtargetFeature<"32bit", "HasRV32", "true", "Implements RV32">; def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; def IsRV64 : Predicate<"Subtarget->is64Bit()">, @@ -527,42 +531,47 @@ // RISC-V processors supported. //===----------------------------------------------------------------------===// -def : ProcessorModel<"generic-rv32", NoSchedModel, []>; +def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>; def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; // Support generic for compatibility with other targets. The triple will be used // to change to the appropriate rv32/rv64 version. def : ProcessorModel<"generic", NoSchedModel, []>; -def : ProcessorModel<"rocket-rv32", RocketModel, []>; +def : ProcessorModel<"rocket-rv32", RocketModel, [Feature32Bit]>; def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>; +def : ProcessorModel<"rocket", RocketModel, []>; -def : ProcessorModel<"sifive-7-rv32", SiFive7Model, [], - [TuneSiFive7]>; -def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit], +def : ProcessorModel<"sifive-7-series", SiFive7Model, [], [TuneSiFive7]>; -def : ProcessorModel<"sifive-e20", RocketModel, [FeatureStdExtM, +def : ProcessorModel<"sifive-e20", RocketModel, [Feature32Bit, + FeatureStdExtM, FeatureStdExtC]>; -def : ProcessorModel<"sifive-e21", RocketModel, [FeatureStdExtM, +def : ProcessorModel<"sifive-e21", RocketModel, [Feature32Bit, + FeatureStdExtM, FeatureStdExtA, FeatureStdExtC]>; -def : ProcessorModel<"sifive-e24", RocketModel, [FeatureStdExtM, +def : ProcessorModel<"sifive-e24", RocketModel, [Feature32Bit, + FeatureStdExtM, FeatureStdExtA, FeatureStdExtF, FeatureStdExtC]>; -def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM, +def : ProcessorModel<"sifive-e31", RocketModel, [Feature32Bit, + FeatureStdExtM, FeatureStdExtA, FeatureStdExtC]>; -def : ProcessorModel<"sifive-e34", RocketModel, [FeatureStdExtM, +def : ProcessorModel<"sifive-e34", RocketModel, [Feature32Bit, + FeatureStdExtM, FeatureStdExtA, FeatureStdExtF, FeatureStdExtC]>; -def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM, +def : ProcessorModel<"sifive-e76", SiFive7Model, [Feature32Bit, + FeatureStdExtM, FeatureStdExtA, FeatureStdExtF, FeatureStdExtC], diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -91,6 +91,7 @@ bool HasStdExtZicboz = false; bool HasStdExtZicbop = false; bool HasStdExtZmmul = false; + bool HasRV32 = false; bool HasRV64 = false; bool IsRV32E = false; bool EnableLinkerRelax = false; diff --git a/llvm/test/Transforms/LoopUnroll/RISCV/unroll.ll b/llvm/test/Transforms/LoopUnroll/RISCV/unroll.ll --- a/llvm/test/Transforms/LoopUnroll/RISCV/unroll.ll +++ b/llvm/test/Transforms/LoopUnroll/RISCV/unroll.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt %s -S -mtriple=riscv64 -loop-unroll -mcpu=sifive-7-rv64 | FileCheck %s +; RUN: opt %s -S -mtriple=riscv64 -loop-unroll -mcpu=sifive-s76 | FileCheck %s define dso_local void @saxpy(float %a, float* %x, float* %y) { ; CHECK-LABEL: @saxpy(