diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -605,6 +605,83 @@
   }
 }
 
+class VPatBinaryMaskSDNode_VV<SDNode vop,
+                              string instruction_name,
+                              ValueType result_type,
+                              ValueType op_type,
+                              ValueType mask_type,
+                              int sew,
+                              LMULInfo vlmul,
+                              OutPatFrag avl,
+                              VReg op_reg_class,
+                              int imm> :
+    Pat<(result_type (vop (op_type op_reg_class:$rs1),
+                          (op_type (vselect (mask_type V0),
+                                            (op_type op_reg_class:$rs2),
+                                            (riscv_vmv_v_x_vl
+                                                 (op_type undef), imm,
+                                                 (XLenVT srcvalue)))))),
+        (!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX#"_MASK")
+                     op_reg_class:$rs1,
+                     op_reg_class:$rs1,
+                     op_reg_class:$rs2,
+                     (mask_type V0),
+                     avl, sew, TAIL_AGNOSTIC)>;
+
+class VPatBinaryMaskSDNode_XI<SDNode vop,
+                              string instruction_name,
+                              string suffix,
+                              ValueType result_type,
+                              ValueType vop_type,
+                              ValueType mask_type,
+                              int sew,
+                              LMULInfo vlmul,
+                              OutPatFrag avl,
+                              VReg vop_reg_class,
+                              ComplexPattern SplatPatKind,
+                              DAGOperand xop_kind,
+                              int imm> :
+    Pat<(result_type (vop
+                     (vop_type vop_reg_class:$rs1),
+                     (vop_type (vselect (mask_type V0),
+                                        (vop_type (SplatPatKind xop_kind:$rs2)),
+                                        (riscv_vmv_v_x_vl
+                                             (vop_type undef), imm,
+                                             (XLenVT srcvalue)))))),
+        (!cast<Instruction>(instruction_name#_#suffix#_# vlmul.MX#"_MASK")
+                     vop_reg_class:$rs1,
+                     vop_reg_class:$rs1,
+                     xop_kind:$rs2,
+                     (mask_type V0),
+                     avl, sew, TAIL_AGNOSTIC)>;
+
+
+multiclass VPatBinaryMaskSDNode_VV_VX<SDNode vop, string instruction_name,
+                                      int imm> {
+  foreach vti = AllIntegerVectors in {
+    def : VPatBinaryMaskSDNode_VV<vop, instruction_name,
+                                  vti.Vector, vti.Vector, vti.Mask,
+                                  vti.Log2SEW, vti.LMul, vti.AVL,
+                                  vti.RegClass, imm>;
+    def : VPatBinaryMaskSDNode_XI<vop, instruction_name, "VX",
+                                  vti.Vector, vti.Vector, vti.Mask,
+                                  vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
+                                  SplatPat, GPR, imm>;
+  }
+}
+
+multiclass VPatBinaryMaskSDNode_VV_VX_VI<SDNode vop, string instruction_name,
+                                         int imm, Operand ImmType = simm5>
+    : VPatBinaryMaskSDNode_VV_VX<vop, instruction_name, imm> {
+  foreach vti = AllIntegerVectors in {
+    def : VPatBinaryMaskSDNode_XI<vop, instruction_name, "VI",
+                                  vti.Vector, vti.Vector, vti.Mask,
+                                  vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
+                                  !cast<ComplexPattern>(SplatPat#_#ImmType),
+                                  ImmType, imm>;
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Patterns.
 //===----------------------------------------------------------------------===//
@@ -627,7 +704,11 @@
 
 // 12.1. Vector Single-Width Integer Add and Subtract
 defm : VPatBinarySDNode_VV_VX_VI<add, "PseudoVADD">;
+defm : VPatBinaryMaskSDNode_VV_VX_VI<add, "PseudoVADD", 0>;
+
 defm : VPatBinarySDNode_VV_VX<sub, "PseudoVSUB">;
+defm : VPatBinaryMaskSDNode_VV_VX<sub, "PseudoVSUB", 0>;
+
 // Handle VRSUB specially since it's the only integer binary op with reversed
 // pattern operands
 foreach vti = AllIntegerVectors in {
@@ -666,13 +747,19 @@
 
 // 12.5. Vector Bitwise Logical Instructions
 defm : VPatBinarySDNode_VV_VX_VI<and, "PseudoVAND">;
+defm : VPatBinaryMaskSDNode_VV_VX_VI<and, "PseudoVAND", -1>;
 defm : VPatBinarySDNode_VV_VX_VI<or, "PseudoVOR">;
+defm : VPatBinaryMaskSDNode_VV_VX_VI<or, "PseudoVOR", 0>;
 defm : VPatBinarySDNode_VV_VX_VI<xor, "PseudoVXOR">;
+defm : VPatBinaryMaskSDNode_VV_VX_VI<xor, "PseudoVXOR", 0>;
 
 // 12.6. Vector Single-Width Bit Shift Instructions
 defm : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>;
+defm : VPatBinaryMaskSDNode_VV_VX_VI<shl, "PseudoVSLL", 0, uimm5>;
 defm : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>;
+defm : VPatBinaryMaskSDNode_VV_VX_VI<srl, "PseudoVSRL", 0, uimm5>;
 defm : VPatBinarySDNode_VV_VX_VI<sra, "PseudoVSRA", uimm5>;
+defm : VPatBinaryMaskSDNode_VV_VX_VI<sra, "PseudoVSRA", 0, uimm5>;
 
 foreach vti = AllIntegerVectors in {
   // Emit shift by 1 as an add since it might be faster.
@@ -720,20 +807,29 @@
 
 // 12.9. Vector Integer Min/Max Instructions
 defm : VPatBinarySDNode_VV_VX<umin, "PseudoVMINU">;
+defm : VPatBinaryMaskSDNode_VV_VX<umin, "PseudoVMINU", -1>;
 defm : VPatBinarySDNode_VV_VX<smin, "PseudoVMIN">;
 defm : VPatBinarySDNode_VV_VX<umax, "PseudoVMAXU">;
+defm : VPatBinaryMaskSDNode_VV_VX<umax, "PseudoVMAXU", 0>;
 defm : VPatBinarySDNode_VV_VX<smax, "PseudoVMAX">;
 
 // 12.10. Vector Single-Width Integer Multiply Instructions
 defm : VPatBinarySDNode_VV_VX<mul, "PseudoVMUL">;
+defm : VPatBinaryMaskSDNode_VV_VX<mul, "PseudoVMUL", 1>;
 defm : VPatBinarySDNode_VV_VX<mulhs, "PseudoVMULH">;
+defm : VPatBinaryMaskSDNode_VV_VX<mulhs, "PseudoVMULH", 1>;
 defm : VPatBinarySDNode_VV_VX<mulhu, "PseudoVMULHU">;
+defm : VPatBinaryMaskSDNode_VV_VX<mulhu, "PseudoVMULHU", 1>;
 
 // 12.11. Vector Integer Divide Instructions
 defm : VPatBinarySDNode_VV_VX<udiv, "PseudoVDIVU">;
+defm : VPatBinaryMaskSDNode_VV_VX<udiv, "PseudoVDIVU", 1>;
 defm : VPatBinarySDNode_VV_VX<sdiv, "PseudoVDIV">;
+defm : VPatBinaryMaskSDNode_VV_VX<sdiv, "PseudoVDIV", 1>;
 defm : VPatBinarySDNode_VV_VX<urem, "PseudoVREMU">;
+defm : VPatBinaryMaskSDNode_VV_VX<urem, "PseudoVREMU", 1>;
 defm : VPatBinarySDNode_VV_VX<srem, "PseudoVREM">;
+defm : VPatBinaryMaskSDNode_VV_VX<srem, "PseudoVREM", 1>;
 
 // 12.12. Vector Widening Integer Multiply Instructions
 defm : VPatWidenBinarySDNode_VV_VX<mul, sext_oneuse, sext_oneuse,
diff --git a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
@@ -890,3 +890,40 @@
   %v = add <vscale x 8 x i64> %splat1, %splat2
   ret <vscale x 8 x i64> %v
 }
+
+define <vscale x 8 x i32> @vadd_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vadd_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vadd.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vadd_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vadd_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vadd.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vadd_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vadd_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vadd.vi v8, v8, 7, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = add <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
@@ -1381,3 +1381,46 @@
   %v = and <vscale x 8 x i64> %splat1, %splat2
   ret <vscale x 8 x i64> %v
 }
+
+define <vscale x 8 x i32> @vand_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vand_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vand.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+  %allones = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %allones
+  %vc = and <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vand_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vand_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vand.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+  %allones = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %allones
+  %vc = and <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vand_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vand_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vand.vi v8, v8, 7, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+  %allones = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %allones
+  %vc = and <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
@@ -1184,3 +1184,47 @@
   %vc = sdiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
+
+define <vscale x 8 x i32> @vdiv_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdiv_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vdiv.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+  %vc = sdiv <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vdiv_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdiv_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vdiv.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = sdiv <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vdiv_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdiv_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vdiv.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = sdiv <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
@@ -1197,3 +1197,47 @@
   %vd = udiv <vscale x 8 x i64> %va, %vc
   ret <vscale x 8 x i64> %vd
 }
+
+define <vscale x 8 x i32> @vdivu_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdivu_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vdivu.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+  %vc = udiv <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vdivu_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdivu_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vdivu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = udiv <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vdivu_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vdivu_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vdivu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = udiv <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll
@@ -890,3 +890,43 @@
   ret <vscale x 8 x i64> %vc
 }
 
+define <vscale x 8 x i32> @vmax_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmax_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmaxu.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+  %cmp = icmp ugt <vscale x 8 x i32> %va, %vs
+  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmax_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmax_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %cmp = icmp ugt <vscale x 8 x i32> %va, %vs
+  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmax_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmax_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, -3
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmaxu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 -3, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %cmp = icmp ugt <vscale x 8 x i32> %va, %vs
+  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+  ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll
@@ -890,3 +890,49 @@
   ret <vscale x 8 x i64> %vc
 }
 
+define <vscale x 8 x i32> @vmin_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmin_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vminu.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+  %max = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %max
+  %cmp = icmp ult <vscale x 8 x i32> %va, %vs
+  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmin_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmin_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vminu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head0 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+  %max = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %max
+  %cmp = icmp ult <vscale x 8 x i32> %va, %vs
+  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmin_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmin_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, -3
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vminu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head0 = insertelement <vscale x 8 x i32> poison, i32 -1, i32 0
+  %max = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 -3, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %max
+  %cmp = icmp ult <vscale x 8 x i32> %va, %vs
+  %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i32> %va, <vscale x 8 x i32> %vs
+  ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
@@ -959,3 +959,48 @@
   %v = mul <vscale x 8 x i64> %splat1, %splat2
   ret <vscale x 8 x i64> %v
 }
+
+define <vscale x 8 x i32> @vmul_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmul_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmul.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+  %vc = mul <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmul_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmul_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmul.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = mul <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vmul_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmul_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmul.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = mul <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode.ll
@@ -348,3 +348,65 @@
   %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %vf
 }
+
+define <vscale x 8 x i32> @vmulh_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmulh_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulh.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head0 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+  %vc = sext <vscale x 8 x i32> %vs to <vscale x 8 x i64>
+  %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %ve = mul <vscale x 8 x i64> %vc, %vd
+  %head1 = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+  %vf = lshr <vscale x 8 x i64> %ve, %splat
+  %vg = trunc <vscale x 8 x i64> %vf to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vg
+}
+
+define <vscale x 8 x i32> @vmulh_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %x, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmulh_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head0 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 %x, i32 0
+  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat1, <vscale x 8 x i32> %one
+  %vb = sext <vscale x 8 x i32> %vs to <vscale x 8 x i64>
+  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %vd = mul <vscale x 8 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+  %ve = lshr <vscale x 8 x i64> %vd, %splat2
+  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vf
+}
+
+define <vscale x 8 x i32> @vmulh_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmulh_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head0 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat1, <vscale x 8 x i32> %one
+  %vb = sext <vscale x 8 x i32> %vs to <vscale x 8 x i64>
+  %vc = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %vd = mul <vscale x 8 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+  %ve = lshr <vscale x 8 x i64> %vd, %splat2
+  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vf
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vmulhu-sdnode.ll
@@ -349,3 +349,65 @@
   %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %vf
 }
+
+define <vscale x 8 x i32> @vmulhu_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmulhu_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head0 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+  %vc = zext <vscale x 8 x i32> %vs to <vscale x 8 x i64>
+  %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %ve = mul <vscale x 8 x i64> %vc, %vd
+  %head1 = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
+  %splat = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+  %vf = lshr <vscale x 8 x i64> %ve, %splat
+  %vg = trunc <vscale x 8 x i64> %vf to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vg
+}
+
+define <vscale x 8 x i32> @vmulhu_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %x, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmulhu_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head0 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 %x, i32 0
+  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat1, <vscale x 8 x i32> %one
+  %vb = zext <vscale x 8 x i32> %vs to <vscale x 8 x i64>
+  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %vd = mul <vscale x 8 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+  %ve = lshr <vscale x 8 x i64> %vd, %splat2
+  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vf
+}
+
+define <vscale x 8 x i32> @vmulhu_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vmulhu_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head0 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head0, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat1 = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat1, <vscale x 8 x i32> %one
+  %vb = zext <vscale x 8 x i32> %vs to <vscale x 8 x i64>
+  %vc = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
+  %vd = mul <vscale x 8 x i64> %vb, %vc
+  %head2 = insertelement <vscale x 8 x i64> poison, i64 32, i32 0
+  %splat2 = shufflevector <vscale x 8 x i64> %head2, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
+  %ve = lshr <vscale x 8 x i64> %vd, %splat2
+  %vf = trunc <vscale x 8 x i64> %ve to <vscale x 8 x i32>
+  ret <vscale x 8 x i32> %vf
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
@@ -1174,3 +1174,40 @@
   %v = or <vscale x 8 x i64> %splat1, %splat2
   ret <vscale x 8 x i64> %v
 }
+
+define <vscale x 8 x i32> @vor_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vor_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vor.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vor_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vor_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vor.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vor_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vor_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vor.vi v8, v8, 7, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = or <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
@@ -1235,3 +1235,48 @@
   ret <vscale x 8 x i64> %vc
 }
 
+
+define <vscale x 8 x i32> @vrem_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vrem_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vrem.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+  %vc = srem <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vrem_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vrem_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vrem.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = srem <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vrem_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vrem_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vrem.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = srem <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
@@ -1263,3 +1263,47 @@
   %vd = urem <vscale x 8 x i64> %va, %vc
   ret <vscale x 8 x i64> %vd
 }
+
+define <vscale x 8 x i32> @vremu_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vremu_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vremu.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> %one
+  %vc = urem <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vremu_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vremu_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vremu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = urem <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vremu_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vremu_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vremu.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head1 = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
+  %one = shufflevector <vscale x 8 x i32> %head1, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %head2 = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head2, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> %one
+  %vc = urem <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vshl-sdnode.ll
@@ -629,3 +629,40 @@
   %vc = shl <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
+
+define <vscale x 8 x i32> @vshl_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vshl_vv_mask_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsll.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vshl_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vshl_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsll.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vshl_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vshl_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsll.vi v8, v8, 31, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 31, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = shl <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsra-sdnode.ll
@@ -802,3 +802,39 @@
   ret <vscale x 8 x i64> %vc
 }
 
+define <vscale x 8 x i32> @vsra_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsra_vv_mask_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsra.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+  %vc = ashr <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsra_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsra_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsra.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = ashr <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsra_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsra_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsra.vi v8, v8, 31, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 31, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = ashr <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode.ll
@@ -582,3 +582,39 @@
   ret <vscale x 8 x i64> %vc
 }
 
+define <vscale x 8 x i32> @vsrl_vv_mask_nxv4i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsrl_vv_mask_nxv4i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsrl.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsrl_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsrl_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsrl.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsrl_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsrl_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsrl.vi v8, v8, 31, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 31, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = lshr <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
@@ -868,3 +868,42 @@
   %v = sub <vscale x 8 x i64> %splat1, %splat2
   ret <vscale x 8 x i64> %v
 }
+
+define <vscale x 8 x i32> @vsub_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsub_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsub.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+  %vc = sub <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsub_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsub_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = sub <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vsub_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vsub_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    li a0, 7
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vsub.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = sub <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
@@ -1381,3 +1381,40 @@
   %v = xor <vscale x 8 x i64> %splat1, %splat2
   ret <vscale x 8 x i64> %v
 }
+
+define <vscale x 8 x i32> @vxor_vv_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vxor_vv_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vxor.vv v8, v8, v12, v0.t
+; CHECK-NEXT:    ret
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %vb, <vscale x 8 x i32> zeroinitializer
+  %vc = xor <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vxor_vx_mask_nxv8i32(<vscale x 8 x i32> %va, i32 signext %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vxor_vx_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vxor.vx v8, v8, a0, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = xor <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}
+
+define <vscale x 8 x i32> @vxor_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: vxor_vi_mask_nxv8i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vxor.vi v8, v8, 7, v0.t
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i32> poison, i32 7, i32 0
+  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
+  %vs = select <vscale x 8 x i1> %mask, <vscale x 8 x i32> %splat, <vscale x 8 x i32> zeroinitializer
+  %vc = xor <vscale x 8 x i32> %va, %vs
+  ret <vscale x 8 x i32> %vc
+}