Index: clang/test/CodeGen/aarch64-bf16-dotprod-intrinsics.c =================================================================== --- clang/test/CodeGen/aarch64-bf16-dotprod-intrinsics.c +++ clang/test/CodeGen/aarch64-bf16-dotprod-intrinsics.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \ -// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns %s -o - | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-bf16-getset-intrinsics.c =================================================================== --- clang/test/CodeGen/aarch64-bf16-getset-intrinsics.c +++ clang/test/CodeGen/aarch64-bf16-getset-intrinsics.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \ -// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm %s -fallow-half-arguments-and-returns -o - | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-bf16-lane-intrinsics.c =================================================================== --- clang/test/CodeGen/aarch64-bf16-lane-intrinsics.c +++ clang/test/CodeGen/aarch64-bf16-lane-intrinsics.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \ -// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-LE %s +// RUN: -disable-O0-optnone -emit-llvm %s -fallow-half-arguments-and-returns -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-LE %s // RUN: %clang_cc1 -triple aarch64_be-arm-none-eabi -target-feature +neon -target-feature +bf16 \ -// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-BE %s +// RUN: -disable-O0-optnone -emit-llvm %s -fallow-half-arguments-and-returns -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-BE %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-bf16-ldst-intrinsics.c =================================================================== --- clang/test/CodeGen/aarch64-bf16-ldst-intrinsics.c +++ clang/test/CodeGen/aarch64-bf16-ldst-intrinsics.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \ -// RUN: -O2 -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK64 +// RUN: -O2 -emit-llvm %s -fallow-half-arguments-and-returns -o - | FileCheck %s --check-prefixes=CHECK,CHECK64 // RUN: %clang_cc1 -no-opaque-pointers -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi hard \ -// RUN: -O2 -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK32 +// RUN: -O2 -emit-llvm %s -fallow-half-arguments-and-returns -o - | FileCheck %s --check-prefixes=CHECK,CHECK32 // REQUIRES: arm-registered-target,aarch64-registered-target Index: clang/test/CodeGen/aarch64-bf16-reinterpret-intrinsics.c =================================================================== --- clang/test/CodeGen/aarch64-bf16-reinterpret-intrinsics.c +++ clang/test/CodeGen/aarch64-bf16-reinterpret-intrinsics.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \ -// RUN: -disable-O0-optnone -S -emit-llvm -o - %s \ +// RUN: -disable-O0-optnone -S -emit-llvm -fallow-half-arguments-and-returns -o - %s \ // RUN: | opt -S -mem2reg \ // RUN: | FileCheck %s Index: clang/test/CodeGen/aarch64-neon-2velem.c =================================================================== --- clang/test/CodeGen/aarch64-neon-2velem.c +++ clang/test/CodeGen/aarch64-neon-2velem.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-neon-3v.c =================================================================== --- clang/test/CodeGen/aarch64-neon-3v.c +++ clang/test/CodeGen/aarch64-neon-3v.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-neon-across.c =================================================================== --- clang/test/CodeGen/aarch64-neon-across.c +++ clang/test/CodeGen/aarch64-neon-across.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-neon-dot-product.c =================================================================== --- clang/test/CodeGen/aarch64-neon-dot-product.c +++ clang/test/CodeGen/aarch64-neon-dot-product.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +dotprod \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -instcombine | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -instcombine | FileCheck %s // REQUIRES: aarch64-registered-target Index: clang/test/CodeGen/aarch64-neon-extract.c =================================================================== --- clang/test/CodeGen/aarch64-neon-extract.c +++ clang/test/CodeGen/aarch64-neon-extract.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target Index: clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c =================================================================== --- clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c +++ clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-neon-fma.c =================================================================== --- clang/test/CodeGen/aarch64-neon-fma.c +++ clang/test/CodeGen/aarch64-neon-fma.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature -// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -S -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-neon-fp16fml.c =================================================================== --- clang/test/CodeGen/aarch64-neon-fp16fml.c +++ clang/test/CodeGen/aarch64-neon-fp16fml.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -no-opaque-pointers -triple arm64-none-linux-gnu -target-feature +v8.2a -target-feature +neon -target-feature +fp16fml \ -// RUN: -fallow-half-arguments-and-returns -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -fallow-half-arguments-and-returns -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target Index: clang/test/CodeGen/aarch64-neon-perm.c =================================================================== --- clang/test/CodeGen/aarch64-neon-perm.c +++ clang/test/CodeGen/aarch64-neon-perm.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -no-opaque-pointers -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-neon-range-checks.c =================================================================== --- clang/test/CodeGen/aarch64-neon-range-checks.c +++ clang/test/CodeGen/aarch64-neon-range-checks.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon -target-feature +sha3 -target-feature +sm4 -verify %s +// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon -target-feature +sha3 -target-feature +sm4 -verify -fallow-half-arguments-and-returns %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-neon-scalar-copy.c =================================================================== --- clang/test/CodeGen/aarch64-neon-scalar-copy.c +++ clang/test/CodeGen/aarch64-neon-scalar-copy.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem-constrained.c =================================================================== --- clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem-constrained.c +++ clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem-constrained.c @@ -1,18 +1,18 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg \ +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg \ // RUN: | FileCheck --check-prefix=COMMON --check-prefix=COMMONIR --check-prefix=UNCONSTRAINED %s // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone \ // RUN: -ffp-exception-behavior=strict \ // RUN: -fexperimental-strict-floating-point \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg \ +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg \ // RUN: | FileCheck --check-prefix=COMMON --check-prefix=COMMONIR --check-prefix=CONSTRAINED %s // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | llc -o=- - \ +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | llc -o=- - \ // RUN: | FileCheck --check-prefix=COMMON --check-prefix=CHECK-ASM %s // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone \ // RUN: -ffp-exception-behavior=strict \ // RUN: -fexperimental-strict-floating-point \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | llc -o=- - \ +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | llc -o=- - \ // RUN: | FileCheck --check-prefix=COMMON --check-prefix=CHECK-ASM %s // REQUIRES: aarch64-registered-target Index: clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c =================================================================== --- clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c +++ clang/test/CodeGen/aarch64-neon-scalar-x-indexed-elem.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-cpu cyclone \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-neon-sha3.c =================================================================== --- clang/test/CodeGen/aarch64-neon-sha3.c +++ clang/test/CodeGen/aarch64-neon-sha3.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \ -// RUN: -target-feature +sha3 -S -emit-llvm -o - %s \ +// RUN: -target-feature +sha3 -S -emit-llvm -fallow-half-arguments-and-returns -o - %s \ // RUN: | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-neon-shifts.c =================================================================== --- clang/test/CodeGen/aarch64-neon-shifts.c +++ clang/test/CodeGen/aarch64-neon-shifts.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -disable-O0-optnone -ffp-contract=fast -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -ffp-contract=fast -S -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-neon-sm4-sm3.c =================================================================== --- clang/test/CodeGen/aarch64-neon-sm4-sm3.c +++ clang/test/CodeGen/aarch64-neon-sm4-sm3.c @@ -1,9 +1,9 @@ // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \ -// RUN: -target-feature +sm4 -S -emit-llvm -o - %s \ +// RUN: -target-feature +sm4 -S -emit-llvm -fallow-half-arguments-and-returns -o - %s \ // RUN: | FileCheck %s // RUN: not %clang_cc1 -Wno-error=implicit-function-declaration -triple aarch64-linux-gnu -target-feature +neon \ -// RUN: -S -emit-llvm -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s +// RUN: -S -emit-llvm -fallow-half-arguments-and-returns -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-neon-tbl.c =================================================================== --- clang/test/CodeGen/aarch64-neon-tbl.c +++ clang/test/CodeGen/aarch64-neon-tbl.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature // RUN: %clang_cc1 -no-opaque-pointers -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-neon-vcadd.c =================================================================== --- clang/test/CodeGen/aarch64-neon-vcadd.c +++ clang/test/CodeGen/aarch64-neon-vcadd.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \ -// RUN: -target-feature +v8.3a -target-feature +fullfp16 -S -emit-llvm -o - %s \ +// RUN: -target-feature +v8.3a -target-feature +fullfp16 -S -emit-llvm -fallow-half-arguments-and-returns -o - %s \ // RUN: | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-neon-vcmla.c =================================================================== --- clang/test/CodeGen/aarch64-neon-vcmla.c +++ clang/test/CodeGen/aarch64-neon-vcmla.c @@ -1,7 +1,7 @@ // RUN: %clang_cc1 -triple arm64-apple-ios -target-feature +neon \ // RUN: -target-feature +v8.3a \ // RUN: -target-feature +fullfp16 \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -O1 | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -O1 | FileCheck %s // REQUIRES: aarch64-registered-target Index: clang/test/CodeGen/aarch64-neon-vsqadd-float-conversion.c =================================================================== --- clang/test/CodeGen/aarch64-neon-vsqadd-float-conversion.c +++ clang/test/CodeGen/aarch64-neon-vsqadd-float-conversion.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg -dce \ +// RUN: -S -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg -dce \ // RUN: | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-neon-vuqadd-float-conversion-warning.c =================================================================== --- clang/test/CodeGen/aarch64-neon-vuqadd-float-conversion-warning.c +++ clang/test/CodeGen/aarch64-neon-vuqadd-float-conversion-warning.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -S -disable-O0-optnone -emit-llvm -o - %s 2>&1 | FileCheck %s +// RUN: -S -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s 2>&1 | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-poly-add.c =================================================================== --- clang/test/CodeGen/aarch64-poly-add.c +++ clang/test/CodeGen/aarch64-poly-add.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg \ +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg \ // RUN: | FileCheck %s // REQUIRES: aarch64-registered-target Index: clang/test/CodeGen/aarch64-poly128.c =================================================================== --- clang/test/CodeGen/aarch64-poly128.c +++ clang/test/CodeGen/aarch64-poly128.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature // RUN: %clang_cc1 -no-opaque-pointers -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -disable-O0-optnone -ffp-contract=fast -emit-llvm -o - %s | opt -S -mem2reg \ +// RUN: -disable-O0-optnone -ffp-contract=fast -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg \ // RUN: | FileCheck %s // REQUIRES: aarch64-registered-target Index: clang/test/CodeGen/aarch64-poly64.c =================================================================== --- clang/test/CodeGen/aarch64-poly64.c +++ clang/test/CodeGen/aarch64-poly64.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -no-opaque-pointers -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -ffp-contract=fast -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg \ +// RUN: -ffp-contract=fast -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg \ // RUN: | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c =================================================================== --- clang/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c +++ clang/test/CodeGen/aarch64-v8.1a-neon-intrinsics.c @@ -1,6 +1,6 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \ -// RUN: -target-feature +v8.1a -S -emit-llvm -disable-O0-optnone -o - %s | opt -mem2reg -dce -S | FileCheck %s +// RUN: -target-feature +v8.1a -S -emit-llvm -disable-O0-optnone -fallow-half-arguments-and-returns -o - %s | opt -mem2reg -dce -S | FileCheck %s // REQUIRES: aarch64-registered-target Index: clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c =================================================================== --- clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c +++ clang/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c @@ -1469,14 +1469,14 @@ // CHECK-LABEL: define {{[^@]+}}@test_vfma_n_f16 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], half noundef [[C:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x half> undef, half [[C]], i32 0 -// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[C]], i32 1 -// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[C]], i32 2 -// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[C]], i32 3 +// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x half> undef, half [[C]], i32 0 +// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x half> [[VECINIT_I]], half [[C]], i32 1 +// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x half> [[VECINIT1_I]], half [[C]], i32 2 +// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x half> [[VECINIT2_I]], half [[C]], i32 3 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x half> [[B]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x half> [[VECINIT3]] to <8 x i8> -// CHECK-NEXT: [[TMP3:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[B]], <4 x half> [[VECINIT3]], <4 x half> [[A]]) +// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x half> [[VECINIT3_I]] to <8 x i8> +// CHECK-NEXT: [[TMP3:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[B]], <4 x half> [[VECINIT3_I]], <4 x half> [[A]]) // CHECK-NEXT: ret <4 x half> [[TMP3]] // float16x4_t test_vfma_n_f16(float16x4_t a, float16x4_t b, float16_t c) { @@ -1486,18 +1486,18 @@ // CHECK-LABEL: define {{[^@]+}}@test_vfmaq_n_f16 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]], half noundef [[C:%.*]]) #[[ATTR1]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <8 x half> undef, half [[C]], i32 0 -// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[C]], i32 1 -// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[C]], i32 2 -// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[C]], i32 3 -// CHECK-NEXT: [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[C]], i32 4 -// CHECK-NEXT: [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[C]], i32 5 -// CHECK-NEXT: [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[C]], i32 6 -// CHECK-NEXT: [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[C]], i32 7 +// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x half> undef, half [[C]], i32 0 +// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x half> [[VECINIT_I]], half [[C]], i32 1 +// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x half> [[VECINIT1_I]], half [[C]], i32 2 +// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x half> [[VECINIT2_I]], half [[C]], i32 3 +// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x half> [[VECINIT3_I]], half [[C]], i32 4 +// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x half> [[VECINIT4_I]], half [[C]], i32 5 +// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x half> [[VECINIT5_I]], half [[C]], i32 6 +// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x half> [[VECINIT6_I]], half [[C]], i32 7 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x half> [[VECINIT7]] to <16 x i8> -// CHECK-NEXT: [[TMP3:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[B]], <8 x half> [[VECINIT7]], <8 x half> [[A]]) +// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x half> [[VECINIT7_I]] to <16 x i8> +// CHECK-NEXT: [[TMP3:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[B]], <8 x half> [[VECINIT7_I]], <8 x half> [[A]]) // CHECK-NEXT: ret <8 x half> [[TMP3]] // float16x8_t test_vfmaq_n_f16(float16x8_t a, float16x8_t b, float16_t c) { @@ -1601,15 +1601,15 @@ // CHECK-LABEL: define {{[^@]+}}@test_vfms_n_f16 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], <4 x half> noundef [[B:%.*]], half noundef [[C:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[FNEG:%.*]] = fneg <4 x half> [[B]] -// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x half> undef, half [[C]], i32 0 -// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[C]], i32 1 -// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[C]], i32 2 -// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[C]], i32 3 +// CHECK-NEXT: [[FNEG_I:%.*]] = fneg <4 x half> [[B]] +// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x half> undef, half [[C]], i32 0 +// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x half> [[VECINIT_I]], half [[C]], i32 1 +// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x half> [[VECINIT1_I]], half [[C]], i32 2 +// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x half> [[VECINIT2_I]], half [[C]], i32 3 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x half> [[FNEG]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x half> [[VECINIT3]] to <8 x i8> -// CHECK-NEXT: [[TMP3:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[FNEG]], <4 x half> [[VECINIT3]], <4 x half> [[A]]) +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x half> [[FNEG_I]] to <8 x i8> +// CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x half> [[VECINIT3_I]] to <8 x i8> +// CHECK-NEXT: [[TMP3:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[FNEG_I]], <4 x half> [[VECINIT3_I]], <4 x half> [[A]]) // CHECK-NEXT: ret <4 x half> [[TMP3]] // float16x4_t test_vfms_n_f16(float16x4_t a, float16x4_t b, float16_t c) { @@ -1619,19 +1619,19 @@ // CHECK-LABEL: define {{[^@]+}}@test_vfmsq_n_f16 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], <8 x half> noundef [[B:%.*]], half noundef [[C:%.*]]) #[[ATTR1]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[FNEG:%.*]] = fneg <8 x half> [[B]] -// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <8 x half> undef, half [[C]], i32 0 -// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[C]], i32 1 -// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[C]], i32 2 -// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[C]], i32 3 -// CHECK-NEXT: [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[C]], i32 4 -// CHECK-NEXT: [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[C]], i32 5 -// CHECK-NEXT: [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[C]], i32 6 -// CHECK-NEXT: [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[C]], i32 7 +// CHECK-NEXT: [[FNEG_I:%.*]] = fneg <8 x half> [[B]] +// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x half> undef, half [[C]], i32 0 +// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x half> [[VECINIT_I]], half [[C]], i32 1 +// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x half> [[VECINIT1_I]], half [[C]], i32 2 +// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x half> [[VECINIT2_I]], half [[C]], i32 3 +// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x half> [[VECINIT3_I]], half [[C]], i32 4 +// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x half> [[VECINIT4_I]], half [[C]], i32 5 +// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x half> [[VECINIT5_I]], half [[C]], i32 6 +// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x half> [[VECINIT6_I]], half [[C]], i32 7 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[FNEG]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x half> [[VECINIT7]] to <16 x i8> -// CHECK-NEXT: [[TMP3:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[FNEG]], <8 x half> [[VECINIT7]], <8 x half> [[A]]) +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[FNEG_I]] to <16 x i8> +// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x half> [[VECINIT7_I]] to <16 x i8> +// CHECK-NEXT: [[TMP3:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[FNEG_I]], <8 x half> [[VECINIT7_I]], <8 x half> [[A]]) // CHECK-NEXT: ret <8 x half> [[TMP3]] // float16x8_t test_vfmsq_n_f16(float16x8_t a, float16x8_t b, float16_t c) { @@ -1721,12 +1721,12 @@ // CHECK-LABEL: define {{[^@]+}}@test_vmul_n_f16 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], half noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x half> undef, half [[B]], i32 0 -// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[B]], i32 1 -// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[B]], i32 2 -// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[B]], i32 3 -// CHECK-NEXT: [[MUL:%.*]] = fmul <4 x half> [[A]], [[VECINIT3]] -// CHECK-NEXT: ret <4 x half> [[MUL]] +// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x half> undef, half [[B]], i32 0 +// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x half> [[VECINIT_I]], half [[B]], i32 1 +// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x half> [[VECINIT1_I]], half [[B]], i32 2 +// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x half> [[VECINIT2_I]], half [[B]], i32 3 +// CHECK-NEXT: [[MUL_I:%.*]] = fmul <4 x half> [[A]], [[VECINIT3_I]] +// CHECK-NEXT: ret <4 x half> [[MUL_I]] // float16x4_t test_vmul_n_f16(float16x4_t a, float16_t b) { return vmul_n_f16(a, b); @@ -1735,16 +1735,16 @@ // CHECK-LABEL: define {{[^@]+}}@test_vmulq_n_f16 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], half noundef [[B:%.*]]) #[[ATTR1]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <8 x half> undef, half [[B]], i32 0 -// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[B]], i32 1 -// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[B]], i32 2 -// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[B]], i32 3 -// CHECK-NEXT: [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[B]], i32 4 -// CHECK-NEXT: [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[B]], i32 5 -// CHECK-NEXT: [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[B]], i32 6 -// CHECK-NEXT: [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[B]], i32 7 -// CHECK-NEXT: [[MUL:%.*]] = fmul <8 x half> [[A]], [[VECINIT7]] -// CHECK-NEXT: ret <8 x half> [[MUL]] +// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x half> undef, half [[B]], i32 0 +// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x half> [[VECINIT_I]], half [[B]], i32 1 +// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x half> [[VECINIT1_I]], half [[B]], i32 2 +// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x half> [[VECINIT2_I]], half [[B]], i32 3 +// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x half> [[VECINIT3_I]], half [[B]], i32 4 +// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x half> [[VECINIT4_I]], half [[B]], i32 5 +// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x half> [[VECINIT5_I]], half [[B]], i32 6 +// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x half> [[VECINIT6_I]], half [[B]], i32 7 +// CHECK-NEXT: [[MUL_I:%.*]] = fmul <8 x half> [[A]], [[VECINIT7_I]] +// CHECK-NEXT: ret <8 x half> [[MUL_I]] // float16x8_t test_vmulq_n_f16(float16x8_t a, float16_t b) { return vmulq_n_f16(a, b); @@ -1858,14 +1858,14 @@ // CHECK-LABEL: define {{[^@]+}}@test_vmulx_n_f16 // CHECK-SAME: (<4 x half> noundef [[A:%.*]], half noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x half> undef, half [[B]], i32 0 -// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[B]], i32 1 -// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[B]], i32 2 -// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[B]], i32 3 +// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x half> undef, half [[B]], i32 0 +// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x half> [[VECINIT_I]], half [[B]], i32 1 +// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x half> [[VECINIT1_I]], half [[B]], i32 2 +// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x half> [[VECINIT2_I]], half [[B]], i32 3 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x half> [[VECINIT3]] to <8 x i8> -// CHECK-NEXT: [[VMULX2_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> [[A]], <4 x half> [[VECINIT3]]) -// CHECK-NEXT: ret <4 x half> [[VMULX2_I]] +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x half> [[VECINIT3_I]] to <8 x i8> +// CHECK-NEXT: [[VMULX2_I_I:%.*]] = call <4 x half> @llvm.aarch64.neon.fmulx.v4f16(<4 x half> [[A]], <4 x half> [[VECINIT3_I]]) +// CHECK-NEXT: ret <4 x half> [[VMULX2_I_I]] // float16x4_t test_vmulx_n_f16(float16x4_t a, float16_t b) { return vmulx_n_f16(a, b); @@ -1874,18 +1874,18 @@ // CHECK-LABEL: define {{[^@]+}}@test_vmulxq_n_f16 // CHECK-SAME: (<8 x half> noundef [[A:%.*]], half noundef [[B:%.*]]) #[[ATTR1]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <8 x half> undef, half [[B]], i32 0 -// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[B]], i32 1 -// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[B]], i32 2 -// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[B]], i32 3 -// CHECK-NEXT: [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[B]], i32 4 -// CHECK-NEXT: [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[B]], i32 5 -// CHECK-NEXT: [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[B]], i32 6 -// CHECK-NEXT: [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[B]], i32 7 +// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x half> undef, half [[B]], i32 0 +// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x half> [[VECINIT_I]], half [[B]], i32 1 +// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x half> [[VECINIT1_I]], half [[B]], i32 2 +// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x half> [[VECINIT2_I]], half [[B]], i32 3 +// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x half> [[VECINIT3_I]], half [[B]], i32 4 +// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x half> [[VECINIT4_I]], half [[B]], i32 5 +// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x half> [[VECINIT5_I]], half [[B]], i32 6 +// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x half> [[VECINIT6_I]], half [[B]], i32 7 // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[VECINIT7]] to <16 x i8> -// CHECK-NEXT: [[VMULX2_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> [[A]], <8 x half> [[VECINIT7]]) -// CHECK-NEXT: ret <8 x half> [[VMULX2_I]] +// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[VECINIT7_I]] to <16 x i8> +// CHECK-NEXT: [[VMULX2_I_I:%.*]] = call <8 x half> @llvm.aarch64.neon.fmulx.v8f16(<8 x half> [[A]], <8 x half> [[VECINIT7_I]]) +// CHECK-NEXT: ret <8 x half> [[VMULX2_I_I]] // float16x8_t test_vmulxq_n_f16(float16x8_t a, float16_t b) { return vmulxq_n_f16(a, b); @@ -1917,9 +1917,8 @@ // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8> -// CHECK-NEXT: [[VMAXV:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half> -// CHECK-NEXT: [[VMAXV1:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v4f16(<4 x half> [[VMAXV]]) -// CHECK-NEXT: ret half [[VMAXV1]] +// CHECK-NEXT: [[VMAXV1_I:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v4f16(<4 x half> [[A]]) +// CHECK-NEXT: ret half [[VMAXV1_I]] // float16_t test_vmaxv_f16(float16x4_t a) { return vmaxv_f16(a); @@ -1929,9 +1928,8 @@ // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR1]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8> -// CHECK-NEXT: [[VMAXV:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half> -// CHECK-NEXT: [[VMAXV1:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v8f16(<8 x half> [[VMAXV]]) -// CHECK-NEXT: ret half [[VMAXV1]] +// CHECK-NEXT: [[VMAXV1_I:%.*]] = call half @llvm.aarch64.neon.fmaxv.f16.v8f16(<8 x half> [[A]]) +// CHECK-NEXT: ret half [[VMAXV1_I]] // float16_t test_vmaxvq_f16(float16x8_t a) { return vmaxvq_f16(a); @@ -1941,9 +1939,8 @@ // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8> -// CHECK-NEXT: [[VMINV:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half> -// CHECK-NEXT: [[VMINV1:%.*]] = call half @llvm.aarch64.neon.fminv.f16.v4f16(<4 x half> [[VMINV]]) -// CHECK-NEXT: ret half [[VMINV1]] +// CHECK-NEXT: [[VMINV1_I:%.*]] = call half @llvm.aarch64.neon.fminv.f16.v4f16(<4 x half> [[A]]) +// CHECK-NEXT: ret half [[VMINV1_I]] // float16_t test_vminv_f16(float16x4_t a) { return vminv_f16(a); @@ -1953,9 +1950,8 @@ // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR1]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8> -// CHECK-NEXT: [[VMINV:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half> -// CHECK-NEXT: [[VMINV1:%.*]] = call half @llvm.aarch64.neon.fminv.f16.v8f16(<8 x half> [[VMINV]]) -// CHECK-NEXT: ret half [[VMINV1]] +// CHECK-NEXT: [[VMINV1_I:%.*]] = call half @llvm.aarch64.neon.fminv.f16.v8f16(<8 x half> [[A]]) +// CHECK-NEXT: ret half [[VMINV1_I]] // float16_t test_vminvq_f16(float16x8_t a) { return vminvq_f16(a); @@ -1965,9 +1961,8 @@ // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8> -// CHECK-NEXT: [[VMAXNMV:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half> -// CHECK-NEXT: [[VMAXNMV1:%.*]] = call half @llvm.aarch64.neon.fmaxnmv.f16.v4f16(<4 x half> [[VMAXNMV]]) -// CHECK-NEXT: ret half [[VMAXNMV1]] +// CHECK-NEXT: [[VMAXNMV1_I:%.*]] = call half @llvm.aarch64.neon.fmaxnmv.f16.v4f16(<4 x half> [[A]]) +// CHECK-NEXT: ret half [[VMAXNMV1_I]] // float16_t test_vmaxnmv_f16(float16x4_t a) { return vmaxnmv_f16(a); @@ -1977,9 +1972,8 @@ // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR1]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8> -// CHECK-NEXT: [[VMAXNMV:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half> -// CHECK-NEXT: [[VMAXNMV1:%.*]] = call half @llvm.aarch64.neon.fmaxnmv.f16.v8f16(<8 x half> [[VMAXNMV]]) -// CHECK-NEXT: ret half [[VMAXNMV1]] +// CHECK-NEXT: [[VMAXNMV1_I:%.*]] = call half @llvm.aarch64.neon.fmaxnmv.f16.v8f16(<8 x half> [[A]]) +// CHECK-NEXT: ret half [[VMAXNMV1_I]] // float16_t test_vmaxnmvq_f16(float16x8_t a) { return vmaxnmvq_f16(a); @@ -1989,9 +1983,8 @@ // CHECK-SAME: (<4 x half> noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x half> [[A]] to <8 x i8> -// CHECK-NEXT: [[VMINNMV:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half> -// CHECK-NEXT: [[VMINNMV1:%.*]] = call half @llvm.aarch64.neon.fminnmv.f16.v4f16(<4 x half> [[VMINNMV]]) -// CHECK-NEXT: ret half [[VMINNMV1]] +// CHECK-NEXT: [[VMINNMV1_I:%.*]] = call half @llvm.aarch64.neon.fminnmv.f16.v4f16(<4 x half> [[A]]) +// CHECK-NEXT: ret half [[VMINNMV1_I]] // float16_t test_vminnmv_f16(float16x4_t a) { return vminnmv_f16(a); @@ -2001,9 +1994,8 @@ // CHECK-SAME: (<8 x half> noundef [[A:%.*]]) #[[ATTR1]] { // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A]] to <16 x i8> -// CHECK-NEXT: [[VMINNMV:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half> -// CHECK-NEXT: [[VMINNMV1:%.*]] = call half @llvm.aarch64.neon.fminnmv.f16.v8f16(<8 x half> [[VMINNMV]]) -// CHECK-NEXT: ret half [[VMINNMV1]] +// CHECK-NEXT: [[VMINNMV1_I:%.*]] = call half @llvm.aarch64.neon.fminnmv.f16.v8f16(<8 x half> [[A]]) +// CHECK-NEXT: ret half [[VMINNMV1_I]] // float16_t test_vminnmvq_f16(float16x8_t a) { return vminnmvq_f16(a); @@ -2200,11 +2192,11 @@ // CHECK-LABEL: define {{[^@]+}}@test_vmov_n_f16 // CHECK-SAME: (half noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x half> undef, half [[A]], i32 0 -// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[A]], i32 1 -// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[A]], i32 2 -// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[A]], i32 3 -// CHECK-NEXT: ret <4 x half> [[VECINIT3]] +// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x half> undef, half [[A]], i32 0 +// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x half> [[VECINIT_I]], half [[A]], i32 1 +// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x half> [[VECINIT1_I]], half [[A]], i32 2 +// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x half> [[VECINIT2_I]], half [[A]], i32 3 +// CHECK-NEXT: ret <4 x half> [[VECINIT3_I]] // float16x4_t test_vmov_n_f16(float16_t a) { return vmov_n_f16(a); @@ -2213,15 +2205,15 @@ // CHECK-LABEL: define {{[^@]+}}@test_vmovq_n_f16 // CHECK-SAME: (half noundef [[A:%.*]]) #[[ATTR1]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <8 x half> undef, half [[A]], i32 0 -// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[A]], i32 1 -// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[A]], i32 2 -// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[A]], i32 3 -// CHECK-NEXT: [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[A]], i32 4 -// CHECK-NEXT: [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[A]], i32 5 -// CHECK-NEXT: [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[A]], i32 6 -// CHECK-NEXT: [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[A]], i32 7 -// CHECK-NEXT: ret <8 x half> [[VECINIT7]] +// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x half> undef, half [[A]], i32 0 +// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x half> [[VECINIT_I]], half [[A]], i32 1 +// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x half> [[VECINIT1_I]], half [[A]], i32 2 +// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x half> [[VECINIT2_I]], half [[A]], i32 3 +// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x half> [[VECINIT3_I]], half [[A]], i32 4 +// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x half> [[VECINIT4_I]], half [[A]], i32 5 +// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x half> [[VECINIT5_I]], half [[A]], i32 6 +// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x half> [[VECINIT6_I]], half [[A]], i32 7 +// CHECK-NEXT: ret <8 x half> [[VECINIT7_I]] // float16x8_t test_vmovq_n_f16(float16_t a) { return vmovq_n_f16(a); @@ -2230,11 +2222,11 @@ // CHECK-LABEL: define {{[^@]+}}@test_vdup_n_f16 // CHECK-SAME: (half noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <4 x half> undef, half [[A]], i32 0 -// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <4 x half> [[VECINIT]], half [[A]], i32 1 -// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <4 x half> [[VECINIT1]], half [[A]], i32 2 -// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <4 x half> [[VECINIT2]], half [[A]], i32 3 -// CHECK-NEXT: ret <4 x half> [[VECINIT3]] +// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x half> undef, half [[A]], i32 0 +// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x half> [[VECINIT_I]], half [[A]], i32 1 +// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x half> [[VECINIT1_I]], half [[A]], i32 2 +// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x half> [[VECINIT2_I]], half [[A]], i32 3 +// CHECK-NEXT: ret <4 x half> [[VECINIT3_I]] // float16x4_t test_vdup_n_f16(float16_t a) { return vdup_n_f16(a); @@ -2243,15 +2235,15 @@ // CHECK-LABEL: define {{[^@]+}}@test_vdupq_n_f16 // CHECK-SAME: (half noundef [[A:%.*]]) #[[ATTR1]] { // CHECK-NEXT: entry: -// CHECK-NEXT: [[VECINIT:%.*]] = insertelement <8 x half> undef, half [[A]], i32 0 -// CHECK-NEXT: [[VECINIT1:%.*]] = insertelement <8 x half> [[VECINIT]], half [[A]], i32 1 -// CHECK-NEXT: [[VECINIT2:%.*]] = insertelement <8 x half> [[VECINIT1]], half [[A]], i32 2 -// CHECK-NEXT: [[VECINIT3:%.*]] = insertelement <8 x half> [[VECINIT2]], half [[A]], i32 3 -// CHECK-NEXT: [[VECINIT4:%.*]] = insertelement <8 x half> [[VECINIT3]], half [[A]], i32 4 -// CHECK-NEXT: [[VECINIT5:%.*]] = insertelement <8 x half> [[VECINIT4]], half [[A]], i32 5 -// CHECK-NEXT: [[VECINIT6:%.*]] = insertelement <8 x half> [[VECINIT5]], half [[A]], i32 6 -// CHECK-NEXT: [[VECINIT7:%.*]] = insertelement <8 x half> [[VECINIT6]], half [[A]], i32 7 -// CHECK-NEXT: ret <8 x half> [[VECINIT7]] +// CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x half> undef, half [[A]], i32 0 +// CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x half> [[VECINIT_I]], half [[A]], i32 1 +// CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x half> [[VECINIT1_I]], half [[A]], i32 2 +// CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x half> [[VECINIT2_I]], half [[A]], i32 3 +// CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x half> [[VECINIT3_I]], half [[A]], i32 4 +// CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x half> [[VECINIT4_I]], half [[A]], i32 5 +// CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x half> [[VECINIT5_I]], half [[A]], i32 6 +// CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x half> [[VECINIT6_I]], half [[A]], i32 7 +// CHECK-NEXT: ret <8 x half> [[VECINIT7_I]] // float16x8_t test_vdupq_n_f16(float16_t a) { return vdupq_n_f16(a); Index: clang/test/CodeGen/aarch64-v8.5a-neon-frint3264-intrinsic.c =================================================================== --- clang/test/CodeGen/aarch64-v8.5a-neon-frint3264-intrinsic.c +++ clang/test/CodeGen/aarch64-v8.5a-neon-frint3264-intrinsic.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +v8.5a\ -// RUN: -flax-vector-conversions=none -S -disable-O0-optnone -emit-llvm -o - %s \ +// RUN: -flax-vector-conversions=none -S -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s \ // RUN: | opt -S -mem2reg \ // RUN: | FileCheck %s Index: clang/test/CodeGen/arm-aapcs-vfp.c =================================================================== --- clang/test/CodeGen/arm-aapcs-vfp.c +++ clang/test/CodeGen/arm-aapcs-vfp.c @@ -2,17 +2,17 @@ // RUN: -target-abi aapcs \ // RUN: -target-cpu cortex-a8 \ // RUN: -mfloat-abi hard \ -// RUN: -ffreestanding \ +// RUN: -ffreestanding -fallow-half-arguments-and-returns \ // RUN: -emit-llvm -w -o - %s | FileCheck %s // RUN: %clang_cc1 -no-opaque-pointers -triple armv7-unknown-nacl-gnueabi \ // RUN: -target-cpu cortex-a8 \ // RUN: -mfloat-abi hard \ -// RUN: -ffreestanding \ +// RUN: -ffreestanding -fallow-half-arguments-and-returns \ // RUN: -emit-llvm -w -o - %s | FileCheck %s // RUN: %clang_cc1 -no-opaque-pointers -triple arm64-apple-darwin9 -target-feature +neon \ -// RUN: -ffreestanding \ +// RUN: -ffreestanding -fallow-half-arguments-and-returns \ // RUN: -emit-llvm -w -o - %s | FileCheck -check-prefix=CHECK64 %s // REQUIRES: arm-registered-target Index: clang/test/CodeGen/arm-bf16-convert-intrinsics.c =================================================================== --- clang/test/CodeGen/arm-bf16-convert-intrinsics.c +++ clang/test/CodeGen/arm-bf16-convert-intrinsics.c @@ -1,19 +1,19 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -no-opaque-pointers \ // RUN: -triple aarch64-arm-none-eabi -target-feature +neon -target-feature +bf16 \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s \ +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s \ // RUN: | opt -S -mem2reg \ // RUN: | FileCheck --check-prefixes=CHECK,CHECK-A64 %s // RUN: %clang_cc1 -no-opaque-pointers \ // RUN: -triple armv8.6a-arm-none-eabi -target-feature +neon \ // RUN: -target-feature +bf16 -mfloat-abi hard \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s \ +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s \ // RUN: | opt -S -mem2reg \ // RUN: | FileCheck --check-prefixes=CHECK,CHECK-A32-HARDFP %s // RUN: %clang_cc1 -no-opaque-pointers \ // RUN: -triple armv8.6a-arm-none-eabi -target-feature +neon \ // RUN: -target-feature +bf16 -mfloat-abi softfp \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s \ +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s \ // RUN: | opt -S -mem2reg \ // RUN: | FileCheck --check-prefixes=CHECK,CHECK-A32-SOFTFP %s Index: clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c =================================================================== --- clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c +++ clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -no-opaque-pointers -triple armv8-arm-none-eabi \ // RUN: -target-feature +neon -target-feature +bf16 -mfloat-abi soft \ -// RUN: -disable-O0-optnone -S -emit-llvm -o - %s \ +// RUN: -disable-O0-optnone -S -emit-llvm -fallow-half-arguments-and-returns -o - %s \ // RUN: | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -no-opaque-pointers -triple armv8-arm-none-eabi \ // RUN: -target-feature +neon -target-feature +bf16 -mfloat-abi hard \ -// RUN: -disable-O0-optnone -S -emit-llvm -o - %s \ +// RUN: -disable-O0-optnone -S -emit-llvm -fallow-half-arguments-and-returns -o - %s \ // RUN: | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/arm-bf16-getset-intrinsics.c =================================================================== --- clang/test/CodeGen/arm-bf16-getset-intrinsics.c +++ clang/test/CodeGen/arm-bf16-getset-intrinsics.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi hard \ -// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns %s -o - | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi soft \ -// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns %s -o - | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/arm-bf16-params-returns.c =================================================================== --- clang/test/CodeGen/arm-bf16-params-returns.c +++ clang/test/CodeGen/arm-bf16-params-returns.c @@ -1,7 +1,7 @@ -// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK32-HARD -// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK32-SOFTFP -// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefixes=CHECK64,CHECK64NEON -// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -target-feature -bf16 -target-feature +neon -DNONEON -emit-llvm -O2 -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK64 +// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi hard -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK32-HARD +// RUN: %clang_cc1 -triple armv8.6a-arm-none-eabi -target-abi aapcs -mfloat-abi softfp -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK32-SOFTFP +// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -target-feature +bf16 -target-feature +neon -emit-llvm -O2 -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefixes=CHECK64,CHECK64NEON +// RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-abi aapcs -target-feature -bf16 -target-feature +neon -DNONEON -emit-llvm -O2 -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg -sroa | FileCheck %s --check-prefix=CHECK64 // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c =================================================================== --- clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c +++ clang/test/CodeGen/arm-bf16-reinterpret-intrinsics.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple armv8.2a-arm-none-eabi -target-feature +neon -target-feature +bf16 -mfloat-abi hard \ -// RUN: -disable-O0-optnone -S -emit-llvm -o - %s \ +// RUN: -disable-O0-optnone -S -emit-llvm -fallow-half-arguments-and-returns -o - %s \ // RUN: | opt -S -instcombine \ // RUN: | FileCheck %s Index: clang/test/CodeGen/arm-neon-directed-rounding-constrained.c =================================================================== --- clang/test/CodeGen/arm-neon-directed-rounding-constrained.c +++ clang/test/CodeGen/arm-neon-directed-rounding-constrained.c @@ -1,37 +1,37 @@ // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 \ -// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: -ffreestanding -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns %s -o - | \ // RUN: opt -S -mem2reg | FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED %s // RUN: %clang_cc1 -triple arm64-linux-gnueabihf -target-feature +neon \ -// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: -ffreestanding -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns %s -o - | \ // RUN: opt -S -mem2reg | FileCheck -check-prefixes=COMMON,COMMONIR,UNCONSTRAINED %s // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 \ // RUN: -ffp-exception-behavior=strict \ // RUN: -fexperimental-strict-floating-point \ -// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: -ffreestanding -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns %s -o - | \ // RUN: opt -S -mem2reg | FileCheck -check-prefixes=COMMON,COMMONIR,CONSTRAINED %s // RUN: %clang_cc1 -triple arm64-linux-gnueabihf -target-feature +neon \ // RUN: -ffp-exception-behavior=strict \ // RUN: -fexperimental-strict-floating-point \ -// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: -ffreestanding -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns %s -o - | \ // RUN: opt -S -mem2reg | FileCheck -check-prefixes=COMMON,COMMONIR,CONSTRAINED %s // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 \ -// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: -ffreestanding -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns %s -o - | \ // RUN: opt -S -mem2reg | llc -o=- - | FileCheck -check-prefixes=COMMON,CHECK-ASM32 %s // RUN: %clang_cc1 -triple arm64-linux-gnueabihf -target-feature +neon \ -// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: -ffreestanding -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns %s -o - | \ // RUN: opt -S -mem2reg | llc -o=- - | FileCheck -check-prefixes=COMMON,CHECK-ASM64 %s // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 \ // RUN: -ffp-exception-behavior=strict \ // RUN: -fexperimental-strict-floating-point \ -// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: -ffreestanding -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns %s -o - | \ // RUN: opt -S -mem2reg | llc -o=- - | FileCheck -check-prefixes=COMMON,CHECK-ASM32 %s // RUN: %clang_cc1 -triple arm64-linux-gnueabihf -target-feature +neon \ // RUN: -ffp-exception-behavior=strict \ // RUN: -fexperimental-strict-floating-point \ -// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: -ffreestanding -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns %s -o - | \ // RUN: opt -S -mem2reg | llc -o=- - | FileCheck -check-prefixes=COMMON,CHECK-ASM64 %s // REQUIRES: arm-registered-target,aarch64-registered-target Index: clang/test/CodeGen/arm-neon-directed-rounding.c =================================================================== --- clang/test/CodeGen/arm-neon-directed-rounding.c +++ clang/test/CodeGen/arm-neon-directed-rounding.c @@ -1,8 +1,8 @@ // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 \ -// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: -ffreestanding -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns %s -o - | \ // RUN: opt -S -mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A32 %s // RUN: %clang_cc1 -triple arm64-linux-gnueabihf -target-feature +neon \ -// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \ +// RUN: -ffreestanding -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns %s -o - | \ // RUN: opt -S -mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A64 %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/arm-neon-dot-product.c =================================================================== --- clang/test/CodeGen/arm-neon-dot-product.c +++ clang/test/CodeGen/arm-neon-dot-product.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple armv8-linux-gnueabihf -target-cpu cortex-a75 -target-feature +dotprod \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -instcombine | FileCheck %s +// RUN: -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -instcombine | FileCheck %s // REQUIRES: arm-registered-target Index: clang/test/CodeGen/arm-neon-fma.c =================================================================== --- clang/test/CodeGen/arm-neon-fma.c +++ clang/test/CodeGen/arm-neon-fma.c @@ -3,7 +3,7 @@ // RUN: -target-abi aapcs \ // RUN: -target-cpu cortex-a7 \ // RUN: -mfloat-abi hard \ -// RUN: -ffreestanding \ +// RUN: -ffreestanding -fallow-half-arguments-and-returns \ // RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/arm-neon-misc.c =================================================================== --- clang/test/CodeGen/arm-neon-misc.c +++ clang/test/CodeGen/arm-neon-misc.c @@ -4,7 +4,7 @@ // RUN: -target-cpu cortex-a8 \ // RUN: -mfloat-abi soft \ // RUN: -target-feature +soft-float-abi \ -// RUN: -ffreestanding \ +// RUN: -ffreestanding -fallow-half-arguments-and-returns \ // RUN: -emit-llvm -w -o - %s | FileCheck %s #include Index: clang/test/CodeGen/arm-neon-numeric-maxmin.c =================================================================== --- clang/test/CodeGen/arm-neon-numeric-maxmin.c +++ clang/test/CodeGen/arm-neon-numeric-maxmin.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature -// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns %s -o - | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/arm-neon-range-checks.c =================================================================== --- clang/test/CodeGen/arm-neon-range-checks.c +++ clang/test/CodeGen/arm-neon-range-checks.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -triple arm64-none-eabi -target-feature +neon -target-feature +dotprod -target-feature +v8.1a -verify %s -// RUN: %clang_cc1 -triple armv8.1a-none-eabi -target-feature +neon -target-feature +dotprod -target-feature +v8.1a -verify %s +// RUN: %clang_cc1 -triple arm64-none-eabi -target-feature +neon -target-feature +dotprod -target-feature +v8.1a -fallow-half-arguments-and-returns -verify %s +// RUN: %clang_cc1 -triple armv8.1a-none-eabi -target-feature +neon -target-feature +dotprod -target-feature +v8.1a -fallow-half-arguments-and-returns -verify %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/arm-neon-shifts.c =================================================================== --- clang/test/CodeGen/arm-neon-shifts.c +++ clang/test/CodeGen/arm-neon-shifts.c @@ -2,7 +2,7 @@ // RUN: %clang_cc1 -triple thumbv7-apple-darwin \ // RUN: -disable-O0-optnone \ // RUN: -target-cpu cortex-a8 \ -// RUN: -ffreestanding \ +// RUN: -ffreestanding -fallow-half-arguments-and-returns \ // RUN: -emit-llvm -w -o - %s | opt -S -mem2reg | FileCheck %s #include Index: clang/test/CodeGen/arm-neon-vcadd.c =================================================================== --- clang/test/CodeGen/arm-neon-vcadd.c +++ clang/test/CodeGen/arm-neon-vcadd.c @@ -1,6 +1,6 @@ // REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple armv8.3a-arm-none-eabi -target-cpu generic \ -// RUN: -target-feature +fullfp16 -mfloat-abi soft -S -emit-llvm -o - %s | \ +// RUN: -target-feature +fullfp16 -mfloat-abi soft -S -emit-llvm -fallow-half-arguments-and-returns -o - %s | \ // RUN: opt -S -sroa -o - | FileCheck %s #include Index: clang/test/CodeGen/arm-neon-vcvtX.c =================================================================== --- clang/test/CodeGen/arm-neon-vcvtX.c +++ clang/test/CodeGen/arm-neon-vcvtX.c @@ -1,5 +1,5 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature -// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns %s -o - | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/arm-neon-vget.c =================================================================== --- clang/test/CodeGen/arm-neon-vget.c +++ clang/test/CodeGen/arm-neon-vget.c @@ -3,7 +3,7 @@ // RUN: -target-cpu cortex-a8 \ // RUN: -mfloat-abi soft \ // RUN: -target-feature +soft-float-abi \ -// RUN: -ffreestanding \ +// RUN: -ffreestanding -fallow-half-arguments-and-returns \ // RUN: -disable-O0-optnone -emit-llvm -w -o - %s | opt -S -mem2reg | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/arm-neon-vld.c =================================================================== --- clang/test/CodeGen/arm-neon-vld.c +++ clang/test/CodeGen/arm-neon-vld.c @@ -1,8 +1,8 @@ // RUN: %clang_cc1 -no-opaque-pointers -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \ +// RUN: -S -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | \ // RUN: FileCheck -check-prefixes=CHECK,CHECK-A64 %s // RUN: %clang_cc1 -no-opaque-pointers -triple armv8-none-linux-gnueabi -target-feature +neon \ -// RUN: -target-feature +fp16 -S -disable-O0-optnone -emit-llvm -o - %s | \ +// RUN: -target-feature +fp16 -S -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | \ // RUN: opt -S -mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A32 %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/arm-neon-vst.c =================================================================== --- clang/test/CodeGen/arm-neon-vst.c +++ clang/test/CodeGen/arm-neon-vst.c @@ -1,8 +1,8 @@ // RUN: %clang_cc1 -no-opaque-pointers -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \ +// RUN: -S -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | \ // RUN: FileCheck -check-prefixes=CHECK,CHECK-A64 %s // RUN: %clang_cc1 -no-opaque-pointers -triple armv8-none-linux-gnueabi -target-feature +neon \ -// RUN: -target-feature +fp16 -S -disable-O0-optnone -emit-llvm -o - %s | \ +// RUN: -target-feature +fp16 -S -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | \ // RUN: opt -S -mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A32 %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/arm-poly-add.c =================================================================== --- clang/test/CodeGen/arm-poly-add.c +++ clang/test/CodeGen/arm-poly-add.c @@ -1,7 +1,7 @@ // REQUIRES: arm-registered-target // RUN: %clang_cc1 -triple armv8.2a-arm-none-eabi \ // RUN: -target-feature +neon \ -// RUN: -mfloat-abi hard \ +// RUN: -mfloat-abi hard -fallow-half-arguments-and-returns \ // RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg \ // RUN: | FileCheck %s Index: clang/test/CodeGen/arm-poly64.c =================================================================== --- clang/test/CodeGen/arm-poly64.c +++ clang/test/CodeGen/arm-poly64.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple armv8.2a-arm-none-eabi -target-feature +neon \ -// RUN: -emit-llvm -o - %s | FileCheck %s +// RUN: -emit-llvm -fallow-half-arguments-and-returns -o - %s | FileCheck %s // Test that we can use the poly64 type on AArch32 Index: clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c =================================================================== --- clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c +++ clang/test/CodeGen/arm-v8.1a-neon-intrinsics.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // RUN: %clang_cc1 -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon \ -// RUN: -S -emit-llvm -o - %s -disable-O0-optnone | opt -mem2reg -dce -S \ +// RUN: -S -emit-llvm -fallow-half-arguments-and-returns -o - %s -disable-O0-optnone | opt -mem2reg -dce -S \ // RUN: | FileCheck %s --check-prefix=CHECK-ARM // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \ -// RUN: -target-feature +v8.1a -S -emit-llvm -o - %s -disable-O0-optnone | opt -mem2reg -dce -S \ +// RUN: -target-feature +v8.1a -S -emit-llvm -fallow-half-arguments-and-returns -o - %s -disable-O0-optnone | opt -mem2reg -dce -S \ // RUN: | FileCheck %s --check-prefix=CHECK-AARCH64 // REQUIRES: arm-registered-target,aarch64-registered-target Index: clang/test/CodeGen/arm-vector-align.c =================================================================== --- clang/test/CodeGen/arm-vector-align.c +++ clang/test/CodeGen/arm-vector-align.c @@ -4,7 +4,7 @@ // RUN: -target-cpu cortex-a8 \ // RUN: -mfloat-abi soft \ // RUN: -target-feature +soft-float-abi \ -// RUN: -ffreestanding \ +// RUN: -ffreestanding -fallow-half-arguments-and-returns \ // RUN: -emit-llvm -w -o - %s | FileCheck %s #include Index: clang/test/CodeGen/arm-vector-arguments.c =================================================================== --- clang/test/CodeGen/arm-vector-arguments.c +++ clang/test/CodeGen/arm-vector-arguments.c @@ -4,7 +4,7 @@ // RUN: -target-cpu cortex-a8 \ // RUN: -mfloat-abi soft \ // RUN: -target-feature +soft-float-abi \ -// RUN: -ffreestanding \ +// RUN: -ffreestanding -fallow-half-arguments-and-returns \ // RUN: -emit-llvm -w -o - %s | FileCheck %s #include Index: clang/test/CodeGen/arm64-arguments.c =================================================================== --- clang/test/CodeGen/arm64-arguments.c +++ clang/test/CodeGen/arm64-arguments.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -no-opaque-pointers -triple arm64-apple-ios7 -target-feature +neon -target-abi darwinpcs -ffreestanding -emit-llvm -w -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-LE -// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64_be-none-linux-gnu -target-feature +neon -target-abi darwinpcs -ffreestanding -emit-llvm -w -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-BE +// RUN: %clang_cc1 -no-opaque-pointers -triple arm64-apple-ios7 -target-feature +neon -target-abi darwinpcs -ffreestanding -emit-llvm -w -fallow-half-arguments-and-returns -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-LE +// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64_be-none-linux-gnu -target-feature +neon -target-abi darwinpcs -ffreestanding -emit-llvm -w -fallow-half-arguments-and-returns -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-BE // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/arm64-lanes.c =================================================================== --- clang/test/CodeGen/arm64-lanes.c +++ clang/test/CodeGen/arm64-lanes.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -// RUN: %clang_cc1 -triple aarch64_be-linux-gnu -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix CHECK-BE +// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple aarch64_be-linux-gnu -target-feature +neon -ffreestanding -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix CHECK-BE // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/arm64-vrnd-constrained.c =================================================================== --- clang/test/CodeGen/arm64-vrnd-constrained.c +++ clang/test/CodeGen/arm64-vrnd-constrained.c @@ -1,10 +1,10 @@ -// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -flax-vector-conversions=none -emit-llvm -o - %s \ +// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -flax-vector-conversions=none -emit-llvm -fallow-half-arguments-and-returns -o - %s \ // RUN: | FileCheck --check-prefix=COMMON --check-prefix=UNCONSTRAINED %s -// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -flax-vector-conversions=none -fexperimental-strict-floating-point -ffp-exception-behavior=strict -emit-llvm -o - %s \ +// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -flax-vector-conversions=none -fexperimental-strict-floating-point -ffp-exception-behavior=strict -emit-llvm -fallow-half-arguments-and-returns -o - %s \ // RUN: | FileCheck --check-prefix=COMMON --check-prefix=CONSTRAINED %s -// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -flax-vector-conversions=none -emit-llvm -o - %s | llc -o=- - \ +// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -flax-vector-conversions=none -emit-llvm -fallow-half-arguments-and-returns -o - %s | llc -o=- - \ // RUN: | FileCheck --check-prefix=COMMON --check-prefix=CHECK-ASM %s -// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -flax-vector-conversions=none -fexperimental-strict-floating-point -ffp-exception-behavior=strict -emit-llvm -o - %s | llc -o=- - \ +// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -flax-vector-conversions=none -fexperimental-strict-floating-point -ffp-exception-behavior=strict -emit-llvm -fallow-half-arguments-and-returns -o - %s | llc -o=- - \ // RUN: | FileCheck --check-prefix=COMMON --check-prefix=CHECK-ASM %s // REQUIRES: aarch64-registered-target Index: clang/test/CodeGen/arm64-vrnd.c =================================================================== --- clang/test/CodeGen/arm64-vrnd.c +++ clang/test/CodeGen/arm64-vrnd.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -flax-vector-conversions=none -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -flax-vector-conversions=none -emit-llvm -fallow-half-arguments-and-returns -o - %s | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/arm64_crypto.c =================================================================== --- clang/test/CodeGen/arm64_crypto.c +++ clang/test/CodeGen/arm64_crypto.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple arm64-apple-ios7.0 -target-feature +neon -target-feature +aes -target-feature +sha2 -ffreestanding -Os -S -o - %s | FileCheck %s +// RUN: %clang_cc1 -triple arm64-apple-ios7.0 -target-feature +neon -target-feature +aes -target-feature +sha2 -ffreestanding -Os -fallow-half-arguments-and-returns -S -o - %s | FileCheck %s // REQUIRES: aarch64-registered-target Index: clang/test/CodeGen/arm64_vcopy.c =================================================================== --- clang/test/CodeGen/arm64_vcopy.c +++ clang/test/CodeGen/arm64_vcopy.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -S -o - -disable-O0-optnone -emit-llvm %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -S -o - -disable-O0-optnone -emit-llvm -fallow-half-arguments-and-returns %s | opt -S -mem2reg | FileCheck %s // Test ARM64 SIMD copy vector element to vector element: vcopyq_lane* Index: clang/test/CodeGen/arm64_vcreate.c =================================================================== --- clang/test/CodeGen/arm64_vcreate.c +++ clang/test/CodeGen/arm64_vcreate.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -S -o - -emit-llvm %s | opt -S -mem2reg | FileCheck %s +// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -S -o - -emit-llvm -fallow-half-arguments-and-returns %s | opt -S -mem2reg | FileCheck %s // Test ARM64 SIMD vcreate intrinsics // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/arm64_vdup.c =================================================================== --- clang/test/CodeGen/arm64_vdup.c +++ clang/test/CodeGen/arm64_vdup.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -S -o - -emit-llvm %s | FileCheck %s +// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -fallow-half-arguments-and-returns -S -o - -emit-llvm %s | FileCheck %s // Test ARM64 SIMD duplicate lane and n intrinsics // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/armv7k-abi.c =================================================================== --- clang/test/CodeGen/armv7k-abi.c +++ clang/test/CodeGen/armv7k-abi.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -no-opaque-pointers -triple thumbv7k-apple-watchos2.0 -target-abi aapcs16 -target-cpu cortex-a7 %s -o - -emit-llvm | FileCheck %s +// RUN: %clang_cc1 -no-opaque-pointers -triple thumbv7k-apple-watchos2.0 -target-abi aapcs16 -target-cpu cortex-a7 %s -fallow-half-arguments-and-returns -o - -emit-llvm | FileCheck %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/neon-aapcs-align.c =================================================================== --- clang/test/CodeGen/neon-aapcs-align.c +++ clang/test/CodeGen/neon-aapcs-align.c @@ -1,10 +1,10 @@ -// RUN: %clang_cc1 -no-opaque-pointers -triple armv7a-none-eabi -target-feature +neon -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=AAPCS -// RUN: %clang_cc1 -no-opaque-pointers -triple armv7a-none-gnueabi -target-feature +neon -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=AAPCS -// RUN: %clang_cc1 -no-opaque-pointers -triple armv7a-none-freebsd -target-feature +neon -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=AAPCS +// RUN: %clang_cc1 -no-opaque-pointers -triple armv7a-none-eabi -target-feature +neon -emit-llvm -o - -fallow-half-arguments-and-returns %s | FileCheck %s -check-prefix=CHECK -check-prefix=AAPCS +// RUN: %clang_cc1 -no-opaque-pointers -triple armv7a-none-gnueabi -target-feature +neon -emit-llvm -o - -fallow-half-arguments-and-returns %s | FileCheck %s -check-prefix=CHECK -check-prefix=AAPCS +// RUN: %clang_cc1 -no-opaque-pointers -triple armv7a-none-freebsd -target-feature +neon -emit-llvm -o - -fallow-half-arguments-and-returns %s | FileCheck %s -check-prefix=CHECK -check-prefix=AAPCS -// RUN: %clang_cc1 -no-opaque-pointers -triple armv7a-apple-ios -target-feature +neon -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=DEFAULT -// RUN: %clang_cc1 -no-opaque-pointers -triple armv7a-none-android -target-feature +neon -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=DEFAULT -// RUN: %clang_cc1 -no-opaque-pointers -triple armv7a-none-androideabi -target-feature +neon -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK -check-prefix=DEFAULT +// RUN: %clang_cc1 -no-opaque-pointers -triple armv7a-apple-ios -target-feature +neon -emit-llvm -o - -fallow-half-arguments-and-returns %s | FileCheck %s -check-prefix=CHECK -check-prefix=DEFAULT +// RUN: %clang_cc1 -no-opaque-pointers -triple armv7a-none-android -target-feature +neon -emit-llvm -o - -fallow-half-arguments-and-returns %s | FileCheck %s -check-prefix=CHECK -check-prefix=DEFAULT +// RUN: %clang_cc1 -no-opaque-pointers -triple armv7a-none-androideabi -target-feature +neon -emit-llvm -o - -fallow-half-arguments-and-returns %s | FileCheck %s -check-prefix=CHECK -check-prefix=DEFAULT // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/neon-crypto.c =================================================================== --- clang/test/CodeGen/neon-crypto.c +++ clang/test/CodeGen/neon-crypto.c @@ -1,12 +1,12 @@ // RUN: %clang_cc1 -triple arm-none-linux-gnueabi -target-feature +neon \ // RUN: -target-feature +sha2 -target-feature +aes \ -// RUN: -target-cpu cortex-a57 -emit-llvm -O1 -o - %s | FileCheck %s +// RUN: -target-cpu cortex-a57 -fallow-half-arguments-and-returns -emit-llvm -O1 -o - %s | FileCheck %s // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ // RUN: -target-feature +sha2 -target-feature +aes \ -// RUN: -emit-llvm -O1 -o - %s | FileCheck %s +// RUN: -emit-llvm -O1 -fallow-half-arguments-and-returns -o - %s | FileCheck %s // RUN: not %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -S -O3 -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s +// RUN: -S -O3 -o -fallow-half-arguments-and-returns - %s 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGen/neon-immediate-ubsan.c =================================================================== --- clang/test/CodeGen/neon-immediate-ubsan.c +++ clang/test/CodeGen/neon-immediate-ubsan.c @@ -1,11 +1,11 @@ // RUN: %clang_cc1 -triple armv7s-linux-gnu -target-abi apcs-gnu -emit-llvm -o - %s \ // RUN: -target-feature +neon -target-cpu cortex-a8 \ -// RUN: -fsanitize=signed-integer-overflow \ +// RUN: -fsanitize=signed-integer-overflow -fallow-half-arguments-and-returns \ // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARMV7 // RUN: %clang_cc1 -triple aarch64-unknown-unknown -emit-llvm -o - %s \ // RUN: -target-feature +neon -target-cpu cortex-a53 \ -// RUN: -fsanitize=signed-integer-overflow \ +// RUN: -fsanitize=signed-integer-overflow -fallow-half-arguments-and-returns \ // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64 // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGenCXX/ARM/exception-alignment.cpp =================================================================== --- clang/test/CodeGenCXX/ARM/exception-alignment.cpp +++ clang/test/CodeGenCXX/ARM/exception-alignment.cpp @@ -1,8 +1,8 @@ // Bug: https://bugs.llvm.org/show_bug.cgi?id=42668 // REQUIRES: arm-registered-target -// RUN: %clang_cc1 -no-opaque-pointers -triple armv8-arm-none-eabi -emit-llvm -target-cpu generic -Os -fcxx-exceptions -o - -x c++ %s | FileCheck --check-prefixes=CHECK,A8 %s -// RUN: %clang_cc1 -no-opaque-pointers -triple armv8-unknown-linux-android -emit-llvm -target-cpu generic -Os -fcxx-exceptions -o - -x c++ %s | FileCheck --check-prefixes=CHECK,A16 %s +// RUN: %clang_cc1 -no-opaque-pointers -triple armv8-arm-none-eabi -emit-llvm -target-cpu generic -Os -fcxx-exceptions -fallow-half-arguments-and-returns -o - -x c++ %s | FileCheck --check-prefixes=CHECK,A8 %s +// RUN: %clang_cc1 -no-opaque-pointers -triple armv8-unknown-linux-android -emit-llvm -target-cpu generic -Os -fcxx-exceptions -fallow-half-arguments-and-returns -o - -x c++ %s | FileCheck --check-prefixes=CHECK,A16 %s // CHECK: [[E:%[A-z0-9]+]] = tail call i8* @__cxa_allocate_exception // CHECK-NEXT: [[BC:%[A-z0-9]+]] = bitcast i8* [[E]] to <2 x i64>* Index: clang/test/CodeGenCXX/aarch64-neon.cpp =================================================================== --- clang/test/CodeGenCXX/aarch64-neon.cpp +++ clang/test/CodeGenCXX/aarch64-neon.cpp @@ -1,8 +1,8 @@ // REQUIRES: aarch64-registered-target // RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \ -// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s +// RUN: -ffp-contract=fast -S -O3 -fallow-half-arguments-and-returns -o - %s | FileCheck %s // RUN: %clang_cc1 -triple arm64-none-netbsd-gnu -target-feature +neon \ -// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s +// RUN: -ffp-contract=fast -S -O3 -fallow-half-arguments-and-returns -o - %s | FileCheck %s // Test whether arm_neon.h works as expected in C++. Index: clang/test/CodeGenCXX/int64_uint64.cpp =================================================================== --- clang/test/CodeGenCXX/int64_uint64.cpp +++ clang/test/CodeGenCXX/int64_uint64.cpp @@ -1,9 +1,9 @@ // RUN: %clang_cc1 -triple arm-linux-guneabi \ -// RUN: -target-cpu cortex-a8 \ +// RUN: -target-cpu cortex-a8 -fallow-half-arguments-and-returns \ // RUN: -emit-llvm -w -O1 -o - %s | FileCheck --check-prefix=CHECK-ARM %s // RUN: %clang_cc1 -triple arm64-linux-gnueabi \ -// RUN: -target-feature +neon \ +// RUN: -target-feature +neon -fallow-half-arguments-and-returns \ // RUN: -emit-llvm -w -O1 -o - %s | FileCheck --check-prefix=CHECK-AARCH64 %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/CodeGenCXX/poly-unsigned.cpp =================================================================== --- clang/test/CodeGenCXX/poly-unsigned.cpp +++ clang/test/CodeGenCXX/poly-unsigned.cpp @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -triple arm64-apple-ios -target-feature +neon -ffreestanding -S -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-UNSIGNED-POLY %s -// RUN: %clang_cc1 -triple arm64-linux-gnu -target-feature +neon -ffreestanding -S -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-UNSIGNED-POLY %s -// RUN: %clang_cc1 -triple armv7-apple-ios -ffreestanding -target-cpu cortex-a8 -S -emit-llvm -o - %s | FileCheck --check-prefix=CHECK-SIGNED-POLY %s +// RUN: %clang_cc1 -triple arm64-apple-ios -target-feature +neon -ffreestanding -S -emit-llvm -fallow-half-arguments-and-returns -o - %s | FileCheck --check-prefix=CHECK-UNSIGNED-POLY %s +// RUN: %clang_cc1 -triple arm64-linux-gnu -target-feature +neon -ffreestanding -S -emit-llvm -fallow-half-arguments-and-returns -o - %s | FileCheck --check-prefix=CHECK-UNSIGNED-POLY %s +// RUN: %clang_cc1 -triple armv7-apple-ios -ffreestanding -target-cpu cortex-a8 -S -emit-llvm -fallow-half-arguments-and-returns -o - %s | FileCheck --check-prefix=CHECK-SIGNED-POLY %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/Headers/arm-neon-header.c =================================================================== --- clang/test/Headers/arm-neon-header.c +++ clang/test/Headers/arm-neon-header.c @@ -1,6 +1,6 @@ -// RUN: %clang_cc1 -triple thumbv7-apple-darwin10 -target-cpu cortex-a8 -fsyntax-only -Wvector-conversions -ffreestanding %s -// RUN: %clang_cc1 -triple thumbv7-apple-darwin10 -target-cpu cortex-a8 -fsyntax-only -flax-vector-conversions=none -ffreestanding %s -// RUN: %clang_cc1 -x c++ -triple thumbv7-apple-darwin10 -target-cpu cortex-a8 -fsyntax-only -Wvector-conversions -ffreestanding %s +// RUN: %clang_cc1 -triple thumbv7-apple-darwin10 -target-cpu cortex-a8 -fsyntax-only -Wvector-conversions -ffreestanding -fallow-half-arguments-and-returns %s +// RUN: %clang_cc1 -triple thumbv7-apple-darwin10 -target-cpu cortex-a8 -fsyntax-only -flax-vector-conversions=none -ffreestanding -fallow-half-arguments-and-returns %s +// RUN: %clang_cc1 -x c++ -triple thumbv7-apple-darwin10 -target-cpu cortex-a8 -fsyntax-only -Wvector-conversions -ffreestanding -fallow-half-arguments-and-returns %s // RUN: %clang -fsyntax-only -ffreestanding --target=aarch64-none-eabi -march=armv8.2-a+fp16 -std=c89 -xc %s // RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-none-eabi -march=armv8.2-a+fp16 -std=c99 -xc %s Index: clang/test/Modules/compiler_builtins_aarch64.m =================================================================== --- clang/test/Modules/compiler_builtins_aarch64.m +++ clang/test/Modules/compiler_builtins_aarch64.m @@ -1,5 +1,5 @@ // RUN: rm -rf %t -// RUN: %clang_cc1 -fsyntax-only -triple aarch64-unknown-unknown -target-feature +neon -fmodules -fimplicit-module-maps -fmodules-cache-path=%t -verify %s +// RUN: %clang_cc1 -fsyntax-only -triple aarch64-unknown-unknown -target-feature +neon -fmodules -fimplicit-module-maps -fmodules-cache-path=%t -verify -fallow-half-arguments-and-returns %s // expected-no-diagnostics // REQUIRES: aarch64-registered-target @import _Builtin_intrinsics.arm; Index: clang/test/Modules/compiler_builtins_arm.m =================================================================== --- clang/test/Modules/compiler_builtins_arm.m +++ clang/test/Modules/compiler_builtins_arm.m @@ -1,5 +1,5 @@ // RUN: rm -rf %t -// RUN: %clang_cc1 -fsyntax-only -triple thumbv7-none-linux-gnueabihf -target-abi aapcs -target-cpu cortex-a8 -mfloat-abi hard -std=c99 -fmodules -fimplicit-module-maps -fmodules-cache-path=%t -D__need_wint_t %s -verify +// RUN: %clang_cc1 -fsyntax-only -triple thumbv7-none-linux-gnueabihf -target-abi aapcs -target-cpu cortex-a8 -mfloat-abi hard -std=c99 -fmodules -fimplicit-module-maps -fmodules-cache-path=%t -D__need_wint_t %s -verify -fallow-half-arguments-and-returns // expected-no-diagnostics // REQUIRES: arm-registered-target @import _Builtin_intrinsics.arm.neon; Index: clang/test/Sema/aarch64-neon-bf16-ranges.c =================================================================== --- clang/test/Sema/aarch64-neon-bf16-ranges.c +++ clang/test/Sema/aarch64-neon-bf16-ranges.c @@ -1,6 +1,6 @@ // RUN: %clang_cc1 -fsyntax-only -verify \ // RUN: -triple aarch64-arm-none-eabi -target-feature +neon \ -// RUN: -target-feature +bf16 %s +// RUN: -target-feature +bf16 -fallow-half-arguments-and-returns %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/Sema/aarch64-neon-fp16-ranges.c =================================================================== --- clang/test/Sema/aarch64-neon-fp16-ranges.c +++ clang/test/Sema/aarch64-neon-fp16-ranges.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -triple arm64-linux-gnu -fallow-half-arguments-and-returns -target-feature +neon -target-feature +fullfp16 -ffreestanding -fsyntax-only -verify %s -// RUN: %clang_cc1 -triple aarch64-linux-gnu -fallow-half-arguments-and-returns -target-feature +fullfp16 -target-feature +neon -ffreestanding -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple arm64-linux-gnu -fallow-half-arguments-and-returns -target-feature +neon -target-feature +fullfp16 -ffreestanding -fsyntax-only -verify -fallow-half-arguments-and-returns %s +// RUN: %clang_cc1 -triple aarch64-linux-gnu -fallow-half-arguments-and-returns -target-feature +fullfp16 -target-feature +neon -ffreestanding -fsyntax-only -verify -fallow-half-arguments-and-returns %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/Sema/aarch64-neon-ranges.c =================================================================== --- clang/test/Sema/aarch64-neon-ranges.c +++ clang/test/Sema/aarch64-neon-ranges.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon -ffreestanding -fsyntax-only -verify %s -// RUN: %clang_cc1 -triple arm64-linux-gnu -target-feature +neon -ffreestanding -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon -ffreestanding -fsyntax-only -verify -fallow-half-arguments-and-returns %s +// RUN: %clang_cc1 -triple arm64-linux-gnu -target-feature +neon -ffreestanding -fsyntax-only -verify -fallow-half-arguments-and-returns %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/Sema/arm-bfloat.cpp =================================================================== --- clang/test/Sema/arm-bfloat.cpp +++ clang/test/Sema/arm-bfloat.cpp @@ -1,14 +1,14 @@ // RUN: %clang_cc1 -fsyntax-only -verify=scalar,neon -std=c++11 \ // RUN: -triple aarch64-arm-none-eabi -target-cpu cortex-a75 \ -// RUN: -target-feature +bf16 -target-feature +neon %s +// RUN: -target-feature +bf16 -target-feature +neon -fallow-half-arguments-and-returns %s // RUN: %clang_cc1 -fsyntax-only -verify=scalar,neon -std=c++11 \ // RUN: -triple arm-arm-none-eabi -target-cpu cortex-a53 \ -// RUN: -target-feature +bf16 -target-feature +neon %s +// RUN: -target-feature +bf16 -target-feature +neon -fallow-half-arguments-and-returns %s // The types should be available under AArch64 even without the bf16 feature // RUN: %clang_cc1 -fsyntax-only -verify=scalar -DNONEON -std=c++11 \ // RUN: -triple aarch64-arm-none-eabi -target-cpu cortex-a75 \ -// RUN: -target-feature -bf16 -target-feature +neon %s +// RUN: -target-feature -bf16 -target-feature +neon -fallow-half-arguments-and-returns %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/Sema/arm-neon-decl-after-stmt.c =================================================================== --- clang/test/Sema/arm-neon-decl-after-stmt.c +++ clang/test/Sema/arm-neon-decl-after-stmt.c @@ -1,5 +1,5 @@ // RUN: %clang_cc1 -triple armebv7-linux-gnueabihf -target-feature +neon \ -// RUN: -Wdeclaration-after-statement -fsyntax-only -verify %s +// RUN: -Wdeclaration-after-statement -fsyntax-only -verify -fallow-half-arguments-and-returns %s // REQUIRES: arm-registered-target // https://github.com/llvm/llvm-project/issues/54062 #include Index: clang/test/Sema/arm-neon-types.c =================================================================== --- clang/test/Sema/arm-neon-types.c +++ clang/test/Sema/arm-neon-types.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple thumbv7-apple-darwin10 -target-cpu cortex-a8 -fsyntax-only -Wvector-conversion -ffreestanding -verify %s +// RUN: %clang_cc1 -triple thumbv7-apple-darwin10 -target-cpu cortex-a8 -fsyntax-only -Wvector-conversion -ffreestanding -verify -fallow-half-arguments-and-returns %s // REQUIRES: aarch64-registered-target || arm-registered-target #ifndef INCLUDE Index: clang/test/Sema/arm64-neon-args.c =================================================================== --- clang/test/Sema/arm64-neon-args.c +++ clang/test/Sema/arm64-neon-args.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -triple arm64-apple-darwin -target-feature +neon -fsyntax-only -ffreestanding -verify %s -// RUN: %clang_cc1 -triple aarch64_be-none-linux-gnu -target-feature +neon -fsyntax-only -ffreestanding -verify %s +// RUN: %clang_cc1 -triple arm64-apple-darwin -target-feature +neon -fsyntax-only -ffreestanding -verify -fallow-half-arguments-and-returns %s +// RUN: %clang_cc1 -triple aarch64_be-none-linux-gnu -target-feature +neon -fsyntax-only -ffreestanding -verify -fallow-half-arguments-and-returns %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/Sema/arm64-neon-header.c =================================================================== --- clang/test/Sema/arm64-neon-header.c +++ clang/test/Sema/arm64-neon-header.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple arm64-apple-darwin -target-feature +neon -Wvector-conversion -fsyntax-only -ffreestanding -verify %s +// RUN: %clang_cc1 -triple arm64-apple-darwin -target-feature +neon -Wvector-conversion -fsyntax-only -ffreestanding -verify -fallow-half-arguments-and-returns %s // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/test/Sema/arm_vfma.c =================================================================== --- clang/test/Sema/arm_vfma.c +++ clang/test/Sema/arm_vfma.c @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -triple thumbv7-none-eabi -target-feature +neon -target-feature +vfp4 -fsyntax-only -verify %s +// RUN: %clang_cc1 -triple thumbv7-none-eabi -target-feature +neon -target-feature +vfp4 -fsyntax-only -verify -fallow-half-arguments-and-returns %s // REQUIRES: aarch64-registered-target || arm-registered-target #include Index: clang/test/Sema/big-endian-neon-initializers.c =================================================================== --- clang/test/Sema/big-endian-neon-initializers.c +++ clang/test/Sema/big-endian-neon-initializers.c @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 %s -triple aarch64_be -target-feature +neon -verify -fsyntax-only -ffreestanding -// RUN: %clang_cc1 %s -triple armebv7 -target-cpu cortex-a8 -verify -fsyntax-only -ffreestanding +// RUN: %clang_cc1 %s -triple aarch64_be -target-feature +neon -verify -fsyntax-only -ffreestanding -fallow-half-arguments-and-returns +// RUN: %clang_cc1 %s -triple armebv7 -target-cpu cortex-a8 -verify -fsyntax-only -ffreestanding -fallow-half-arguments-and-returns // REQUIRES: aarch64-registered-target || arm-registered-target Index: clang/utils/TableGen/NeonEmitter.cpp =================================================================== --- clang/utils/TableGen/NeonEmitter.cpp +++ clang/utils/TableGen/NeonEmitter.cpp @@ -395,11 +395,7 @@ // Pointer arguments need to use macros to avoid hiding aligned attributes // from the pointer type. - - // It is not permitted to pass or return an __fp16 by value, so intrinsics - // taking a scalar float16_t must be implemented as macros. - if (Type.isImmediate() || Type.isPointer() || - (Type.isScalar() && Type.isHalf())) + if (Type.isImmediate() || Type.isPointer()) UseMacro = true; } }