Index: llvm/lib/CodeGen/TypePromotion.cpp
===================================================================
--- llvm/lib/CodeGen/TypePromotion.cpp
+++ llvm/lib/CodeGen/TypePromotion.cpp
@@ -551,8 +551,11 @@
     }
 
     // Don't insert a trunc for a zext which can still legally promote.
+    // Nor insert a trunc for a zext with the same input type as output, this
+    // was a zext that was part of a promotion mutation and will be removed
+    // after.
     if (auto ZExt = dyn_cast<ZExtInst>(I))
-      if (ZExt->getType()->getScalarSizeInBits() > PromotedWidth)
+      if (ZExt->getType()->getScalarSizeInBits() >= PromotedWidth)
         continue;
 
     // Now handle the others.
Index: llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep.ll
===================================================================
--- llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep.ll
+++ llvm/test/Transforms/TypePromotion/AArch64/phi-zext-gep.ll
@@ -24,7 +24,6 @@
 ; CHECK-NEXT:    br label [[FOR_END]]
 ; CHECK:       for.end:
 ; CHECK-NEXT:    [[TAG_0_IN_LCSSA:%.*]] = phi i32 [ [[TMP0]], [[ENTRY:%.*]] ], [ [[TMP1]], [[FOR_END_LOOPEXIT]] ]
-; CHECK-NEXT:    [[TMP2:%.*]] = trunc i32 [[TAG_0_IN_LCSSA]] to i8
 ; CHECK-NEXT:    ret i32 [[TAG_0_IN_LCSSA]]
 ;
 entry:
Index: llvm/test/Transforms/TypePromotion/ARM/calls.ll
===================================================================
--- llvm/test/Transforms/TypePromotion/ARM/calls.ll
+++ llvm/test/Transforms/TypePromotion/ARM/calls.ll
@@ -216,12 +216,11 @@
 ; CHECK-NEXT:    [[TOBOOL:%.*]] = icmp eq i32 [[D_SROA_0_0]], 0
 ; CHECK-NEXT:    br i1 [[TOBOOL]], label [[FOR_COND_BACKEDGE]], label [[IF_THEN:%.*]]
 ; CHECK:       for.cond.backedge:
-; CHECK-NEXT:    [[D_SROA_0_0_BE]] = phi i32 [ [[TMP1:%.*]], [[IF_THEN]] ], [ 0, [[FOR_COND]] ]
+; CHECK-NEXT:    [[D_SROA_0_0_BE]] = phi i32 [ [[TMP0:%.*]], [[IF_THEN]] ], [ 0, [[FOR_COND]] ]
 ; CHECK-NEXT:    br label [[FOR_COND]]
 ; CHECK:       if.then:
-; CHECK-NEXT:    [[TMP0:%.*]] = trunc i32 [[D_SROA_0_0]] to i16
 ; CHECK-NEXT:    [[CALL:%.*]] = tail call zeroext i16 bitcast (i16 (...)* @f to i16 (i32)*)(i32 [[D_SROA_0_0]])
-; CHECK-NEXT:    [[TMP1]] = zext i16 [[CALL]] to i32
+; CHECK-NEXT:    [[TMP0]] = zext i16 [[CALL]] to i32
 ; CHECK-NEXT:    br label [[FOR_COND_BACKEDGE]]
 ;
 entry:
Index: llvm/test/Transforms/TypePromotion/ARM/casts.ll
===================================================================
--- llvm/test/Transforms/TypePromotion/ARM/casts.ll
+++ llvm/test/Transforms/TypePromotion/ARM/casts.ll
@@ -339,16 +339,15 @@
 ; CHECK-NEXT:    [[CAST:%.*]] = bitcast i32** [[__SIZE__I5_I_I]] to i32*
 ; CHECK-NEXT:    [[TMP3:%.*]] = load i32, i32* [[CAST]], align 4
 ; CHECK-NEXT:    [[TMP4:%.*]] = lshr i32 [[TMP1]], 1
-; CHECK-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
 ; CHECK-NEXT:    [[COND_I_I:%.*]] = select i1 [[TOBOOL_I_I_I_I]], i32 [[TMP4]], i32 [[TMP3]]
 ; CHECK-NEXT:    [[__SIZE__I_I_I_I_I:%.*]] = bitcast i32* [[THIS:%.*]] to i8*
-; CHECK-NEXT:    [[TMP6:%.*]] = load i8, i8* [[__SIZE__I_I_I_I_I]], align 4
-; CHECK-NEXT:    [[TMP7:%.*]] = zext i8 [[TMP6]] to i32
-; CHECK-NEXT:    [[TMP8:%.*]] = and i32 [[TMP7]], 1
-; CHECK-NEXT:    [[TOBOOL_I_I_I_I_I:%.*]] = icmp eq i32 [[TMP8]], 0
-; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr inbounds i8, i8* [[__SIZE__I_I_I_I]], i32 [[__POS1:%.*]]
-; CHECK-NEXT:    [[TMP10:%.*]] = getelementptr inbounds i8, i8* [[__SIZE__I_I_I_I]], i32 [[__POS2:%.*]]
-; CHECK-NEXT:    [[RES:%.*]] = select i1 [[TOBOOL_I_I_I_I_I]], i8* [[TMP9]], i8* [[TMP10]]
+; CHECK-NEXT:    [[TMP5:%.*]] = load i8, i8* [[__SIZE__I_I_I_I_I]], align 4
+; CHECK-NEXT:    [[TMP6:%.*]] = zext i8 [[TMP5]] to i32
+; CHECK-NEXT:    [[TMP7:%.*]] = and i32 [[TMP6]], 1
+; CHECK-NEXT:    [[TOBOOL_I_I_I_I_I:%.*]] = icmp eq i32 [[TMP7]], 0
+; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr inbounds i8, i8* [[__SIZE__I_I_I_I]], i32 [[__POS1:%.*]]
+; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr inbounds i8, i8* [[__SIZE__I_I_I_I]], i32 [[__POS2:%.*]]
+; CHECK-NEXT:    [[RES:%.*]] = select i1 [[TOBOOL_I_I_I_I_I]], i8* [[TMP8]], i8* [[TMP9]]
 ; CHECK-NEXT:    ret i8* [[RES]]
 ;
 entry:
@@ -1009,7 +1008,6 @@
 ; CHECK-NEXT:    [[OR:%.*]] = or i32 [[TMP4]], [[TMP2]]
 ; CHECK-NEXT:    [[TMP5:%.*]] = trunc i32 [[OR]] to i8
 ; CHECK-NEXT:    store i8 [[TMP5]], i8* [[B]], align 1
-; CHECK-NEXT:    [[TMP6:%.*]] = trunc i32 [[OR]] to i8
 ; CHECK-NEXT:    ret i32 [[OR]]
 ;
 entry:
@@ -1035,7 +1033,6 @@
 ; CHECK-NEXT:    [[TMP2:%.*]] = urem i32 535, [[TMP1]]
 ; CHECK-NEXT:    [[TMP3:%.*]] = and i32 [[TMP2]], 255
 ; CHECK-NEXT:    [[TMP4:%.*]] = udiv i32 [[TMP3]], 3
-; CHECK-NEXT:    [[TMP5:%.*]] = trunc i32 [[TMP4]] to i8
 ; CHECK-NEXT:    br label [[COND_END]]
 ; CHECK:       cond.end:
 ; CHECK-NEXT:    [[COND:%.*]] = phi i32 [ [[TMP4]], [[COND_FALSE]] ], [ 0, [[ENTRY:%.*]] ]