diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -8264,10 +8264,32 @@
 }
 
 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG) {
-  // fold (sub x, (select lhs, rhs, cc, 0, y)) ->
-  //      (select lhs, rhs, cc, x, (sub x, y))
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
+
+  // Prefer to make this 'add 0/1' rather than 'sub 0/1'
+  // sub constant(!0), 0/1 -> add constant - 1, 1/0
+  // NODE: constant == 0, No redundant instructions are generated.
+  // (sub constant, (setcc x, y, eq/neq)) ->
+  // (add (setcc x, y, neq/eq), constant - 1)
+  auto *Nnz0 = dyn_cast<ConstantSDNode>(N0);
+  if (Nnz0 && N1.getOpcode() == ISD::SETCC && N1.hasOneUse()) {
+    const auto *CC = cast<CondCodeSDNode>(N1->getOperand(2));
+    ISD::CondCode CCVal = CC->get();
+    if (!Nnz0->isZero() && isIntEqualitySetCC(CCVal)) {
+      EVT VT = N->getValueType(0);
+      const APInt &ImmVal = Nnz0->getAPIntValue();
+      SDValue CCInverse =
+          DAG.getCondCode(ISD::getSetCCInverse(CCVal, N0.getValueType()));
+      SDValue NewN0 = DAG.getNode(ISD::SETCC, SDLoc(N), VT, N1->getOperand(0),
+                                  N1->getOperand(1), CCInverse);
+      SDValue NewN1 = DAG.getConstant(ImmVal - 1, SDLoc(N), VT);
+      return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewN0, NewN1);
+    }
+  }
+
+  // fold (sub x, (select lhs, rhs, cc, 0, y)) ->
+  //      (select lhs, rhs, cc, x, (sub x, y))
   return combineSelectAndUse(N, N1, N0, DAG, /*AllOnes*/ false);
 }
 
diff --git a/llvm/test/CodeGen/RISCV/setcc-logic.ll b/llvm/test/CodeGen/RISCV/setcc-logic.ll
--- a/llvm/test/CodeGen/RISCV/setcc-logic.ll
+++ b/llvm/test/CodeGen/RISCV/setcc-logic.ll
@@ -118,3 +118,24 @@
   %r = and i1 %a, %b
   ret i1 %r
 }
+
+define i32 @bar(i32 %n) {
+; RV32I-LABEL: bar:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:    addi a0, a0, -9
+; RV32I-NEXT:    snez a0, a0
+; RV32I-NEXT:    addi a0, a0, 1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: bar:
+; RV64I:       # %bb.0: # %entry
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    addi a0, a0, -9
+; RV64I-NEXT:    snez a0, a0
+; RV64I-NEXT:    addi a0, a0, 1
+; RV64I-NEXT:    ret
+entry:
+  %cmp = icmp eq i32 %n, 9
+  %a = select i1 %cmp, i32 1, i32 2
+  ret i32 %a
+}