diff --git a/llvm/test/MC/RISCV/priv-rv64-valid.s b/llvm/test/MC/RISCV/priv-rv64-valid.s --- a/llvm/test/MC/RISCV/priv-rv64-valid.s +++ b/llvm/test/MC/RISCV/priv-rv64-valid.s @@ -9,30 +9,30 @@ # CHECK-INST: hlv.wu a0, (a1) # CHECK: encoding: [0x73,0xc5,0x15,0x68] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} hlv.wu a0, (a1) # CHECK-INST: hlv.wu a0, (a1) # CHECK: encoding: [0x73,0xc5,0x15,0x68] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} hlv.wu a0, 0(a1) # CHECK-INST: hlv.d a0, (a1) # CHECK: encoding: [0x73,0xc5,0x05,0x6c] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} hlv.d a0, (a1) # CHECK-INST: hlv.d a0, (a1) # CHECK: encoding: [0x73,0xc5,0x05,0x6c] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} hlv.d a0, 0(a1) # CHECK-INST: hsv.d a0, (a1) # CHECK: encoding: [0x73,0xc0,0xa5,0x6e] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} hsv.d a0, (a1) # CHECK-INST: hsv.d a0, (a1) # CHECK: encoding: [0x73,0xc0,0xa5,0x6e] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} hsv.d a0, 0(a1) diff --git a/llvm/test/MC/RISCV/rv32c-invalid.s b/llvm/test/MC/RISCV/rv32c-invalid.s --- a/llvm/test/MC/RISCV/rv32c-invalid.s +++ b/llvm/test/MC/RISCV/rv32c-invalid.s @@ -22,15 +22,15 @@ c.jr x0 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction c.jalr zero # CHECK: :[[@LINE]]:9: error: invalid operand for instruction c.addi x0, x0, 1 # CHECK: :[[@LINE]]:13: error: immediate must be zero -c.li zero, 2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions +c.li zero, 2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions{{$}} c.slli zero, zero, 4 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction -c.mv zero, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions +c.mv zero, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions{{$}} c.mv ra, x0 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction c.add ra, ra, x0 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction c.add zero, zero, sp # CHECK: :[[@LINE]]:14: error: invalid operand for instruction ## GPRNoX0X2 -c.lui x0, 4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions +c.lui x0, 4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions{{$}} c.lui x2, 4 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction ## SP @@ -55,7 +55,7 @@ c.andi a0, %hi(foo) # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31] ## simm6nonzero -c.addi t0, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions +c.addi t0, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions{{$}} c.addi t0, -33 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31] c.addi t0, 32 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31] c.addi t0, foo # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31] diff --git a/llvm/test/MC/RISCV/rv32c-only-valid.s b/llvm/test/MC/RISCV/rv32c-only-valid.s --- a/llvm/test/MC/RISCV/rv32c-only-valid.s +++ b/llvm/test/MC/RISCV/rv32c-only-valid.s @@ -17,7 +17,7 @@ # CHECK-OBJ: c.jal 0x7fe # CHECK-ASM: c.jal 2046 # CHECK-ASM: encoding: [0xfd,0x2f] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) -# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set -# CHECK-NO-RV32-AND-EXT: error: instruction requires the following: 'C' (Compressed Instructions), RV32I Base Instruction Set +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} +# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set{{$}} +# CHECK-NO-RV32-AND-EXT: error: instruction requires the following: 'C' (Compressed Instructions), RV32I Base Instruction Set{{$}} c.jal 2046 diff --git a/llvm/test/MC/RISCV/rv32c-valid.s b/llvm/test/MC/RISCV/rv32c-valid.s --- a/llvm/test/MC/RISCV/rv32c-valid.s +++ b/llvm/test/MC/RISCV/rv32c-valid.s @@ -17,147 +17,147 @@ # CHECK-ASM-AND-OBJ: c.lwsp ra, 0(sp) # CHECK-ASM: encoding: [0x82,0x40] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.lwsp ra, 0(sp) # CHECK-ASM-AND-OBJ: c.swsp ra, 252(sp) # CHECK-ASM: encoding: [0x86,0xdf] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.swsp ra, 252(sp) # CHECK-ASM-AND-OBJ: c.lw a2, 0(a0) # CHECK-ASM: encoding: [0x10,0x41] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.lw a2, 0(a0) # CHECK-ASM-AND-OBJ: c.sw a5, 124(a3) # CHECK-ASM: encoding: [0xfc,0xde] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.sw a5, 124(a3) # CHECK-ASM-AND-OBJ: c.lwsp s0, 0(sp) # CHECK-ASM: encoding: [0x02,0x44] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.lwsp x8, (x2) # CHECK-ASM-AND-OBJ: c.swsp s0, 0(sp) # CHECK-ASM: encoding: [0x22,0xc0] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.swsp x8, (x2) # CHECK-ASM-AND-OBJ: c.lw s0, 0(s1) # CHECK-ASM: encoding: [0x80,0x40] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.lw x8, (x9) # CHECK-ASM-AND-OBJ: c.sw s0, 0(s1) # CHECK-ASM: encoding: [0x80,0xc0] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.sw x8, (x9) # CHECK-OBJ: c.j 0xfffff810 # CHECK-ASM: c.j -2048 # CHECK-ASM: encoding: [0x01,0xb0] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.j -2048 # CHECK-ASM-AND-OBJ: c.jr a7 # CHECK-ASM: encoding: [0x82,0x88] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.jr a7 # CHECK-ASM-AND-OBJ: c.jalr a1 # CHECK-ASM: encoding: [0x82,0x95] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.jalr a1 # CHECK-OBJ: c.beqz a3, 0xffffff16 # CHECK-ASM: c.beqz a3, -256 # CHECK-ASM: encoding: [0x81,0xd2] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.beqz a3, -256 # CHECK-OBJ: c.bnez a5, 0x116 # CHECK-ASM: c.bnez a5, 254 # CHECK-ASM: encoding: [0xfd,0xef] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.bnez a5, 254 # CHECK-ASM-AND-OBJ: c.li a7, 31 # CHECK-ASM: encoding: [0xfd,0x48] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.li a7, 31 # CHECK-ASM-AND-OBJ: c.addi a3, -32 # CHECK-ASM: encoding: [0x81,0x16] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.addi a3, -32 # CHECK-ASM-AND-OBJ: c.addi16sp sp, -512 # CHECK-ASM: encoding: [0x01,0x71] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.addi16sp sp, -512 # CHECK-ASM-AND-OBJ: c.addi16sp sp, 496 # CHECK-ASM: encoding: [0x7d,0x61] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.addi16sp sp, 496 # CHECK-ASM-AND-OBJ: c.addi4spn a3, sp, 1020 # CHECK-ASM: encoding: [0xf4,0x1f] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.addi4spn a3, sp, 1020 # CHECK-ASM-AND-OBJ: c.addi4spn a3, sp, 4 # CHECK-ASM: encoding: [0x54,0x00] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.addi4spn a3, sp, 4 # CHECK-ASM-AND-OBJ: c.slli a1, 1 # CHECK-ASM: encoding: [0x86,0x05] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.slli a1, 1 # CHECK-ASM-AND-OBJ: c.srli a3, 31 # CHECK-ASM: encoding: [0xfd,0x82] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.srli a3, 31 # CHECK-ASM-AND-OBJ: c.srai a4, 2 # CHECK-ASM: encoding: [0x09,0x87] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.srai a4, 2 # CHECK-ASM-AND-OBJ: c.andi a5, 15 # CHECK-ASM: encoding: [0xbd,0x8b] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.andi a5, 15 # CHECK-ASM-AND-OBJ: c.mv a7, s0 # CHECK-ASM: encoding: [0xa2,0x88] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.mv a7, s0 # CHECK-ASM-AND-OBJ: c.and a1, a2 # CHECK-ASM: encoding: [0xf1,0x8d] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.and a1, a2 # CHECK-ASM-AND-OBJ: c.or a2, a3 # CHECK-ASM: encoding: [0x55,0x8e] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.or a2, a3 # CHECK-ASM-AND-OBJ: c.xor a3, a4 # CHECK-ASM: encoding: [0xb9,0x8e] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.xor a3, a4 # CHECK-ASM-AND-OBJ: c.sub a4, a5 # CHECK-ASM: encoding: [0x1d,0x8f] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.sub a4, a5 # CHECK-ASM-AND-OBJ: c.nop # CHECK-ASM: encoding: [0x01,0x00] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.nop # CHECK-ASM-AND-OBJ: c.ebreak # CHECK-ASM: encoding: [0x02,0x90] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.ebreak # CHECK-ASM-AND-OBJ: c.lui s0, 1 # CHECK-ASM: encoding: [0x05,0x64] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.lui s0, 1 # CHECK-ASM-AND-OBJ: c.lui s0, 31 # CHECK-ASM: encoding: [0x7d,0x64] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.lui s0, 31 # CHECK-ASM-AND-OBJ: c.lui s0, 1048544 # CHECK-ASM: encoding: [0x01,0x74] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.lui s0, 0xfffe0 # CHECK-ASM-AND-OBJ: c.lui s0, 1048575 # CHECK-ASM: encoding: [0x7d,0x74] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.lui s0, 0xfffff # CHECK-ASM-AND-OBJ: c.unimp # CHECK-ASM: encoding: [0x00,0x00] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.unimp diff --git a/llvm/test/MC/RISCV/rv32dc-valid.s b/llvm/test/MC/RISCV/rv32dc-valid.s --- a/llvm/test/MC/RISCV/rv32dc-valid.s +++ b/llvm/test/MC/RISCV/rv32dc-valid.s @@ -12,22 +12,22 @@ # CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp) # CHECK-ASM: encoding: [0x7e,0x34] -# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point) -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point) +# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fldsp fs0, 504(sp) # CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp) # CHECK-ASM: encoding: [0xc6,0xbf] -# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point) -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point) +# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fsdsp fa7, 504(sp) # CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5) # CHECK-ASM: encoding: [0xf4,0x3f] -# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point) -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point) +# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fld fa3, 248(a5) # CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1) # CHECK-ASM: encoding: [0xf0,0xbd] -# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point) -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point) +# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fsd fa2, 248(a1) diff --git a/llvm/test/MC/RISCV/rv32f-invalid.s b/llvm/test/MC/RISCV/rv32f-invalid.s --- a/llvm/test/MC/RISCV/rv32f-invalid.s +++ b/llvm/test/MC/RISCV/rv32f-invalid.s @@ -29,6 +29,6 @@ fnmsub.s f18, f19, f20, f21, 0b111 # CHECK: :[[@LINE]]:30: error: operand must be a valid floating point rounding mode mnemonic # Using 'D' instructions for an 'F'-only target -fadd.d ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'D' (Double-Precision Floating-Point) +fadd.d ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} # Using RV64F instructions for RV32 is tested in rv64f-valid.s diff --git a/llvm/test/MC/RISCV/rv32fc-valid.s b/llvm/test/MC/RISCV/rv32fc-valid.s --- a/llvm/test/MC/RISCV/rv32fc-valid.s +++ b/llvm/test/MC/RISCV/rv32fc-valid.s @@ -18,26 +18,26 @@ # CHECK-ASM-AND-OBJ: c.flwsp fs0, 252(sp) # CHECK-ASM: encoding: [0x7e,0x74] -# CHECK-NO-EXT-F: error: instruction requires the following: 'F' (Single-Precision Floating-Point) -# CHECK-NO-EXT-FC: error: instruction requires the following: 'C' (Compressed Instructions), 'F' (Single-Precision Floating-Point) -# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set +# CHECK-NO-EXT-F: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} +# CHECK-NO-EXT-FC: error: instruction requires the following: 'C' (Compressed Instructions), 'F' (Single-Precision Floating-Point){{$}} +# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set{{$}} c.flwsp fs0, 252(sp) # CHECK-ASM-AND-OBJ: c.fswsp fa7, 252(sp) # CHECK-ASM: encoding: [0xc6,0xff] -# CHECK-NO-EXT-F: error: instruction requires the following: 'F' (Single-Precision Floating-Point) -# CHECK-NO-EXT-FC: error: instruction requires the following: 'C' (Compressed Instructions), 'F' (Single-Precision Floating-Point) -# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set +# CHECK-NO-EXT-F: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} +# CHECK-NO-EXT-FC: error: instruction requires the following: 'C' (Compressed Instructions), 'F' (Single-Precision Floating-Point){{$}} +# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set{{$}} c.fswsp fa7, 252(sp) # CHECK-ASM-AND-OBJ: c.flw fa3, 124(a5) # CHECK-ASM: encoding: [0xf4,0x7f] -# CHECK-NO-EXT-F: error: instruction requires the following: 'F' (Single-Precision Floating-Point) -# CHECK-NO-EXT-FC: error: instruction requires the following: 'C' (Compressed Instructions), 'F' (Single-Precision Floating-Point) -# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set +# CHECK-NO-EXT-F: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} +# CHECK-NO-EXT-FC: error: instruction requires the following: 'C' (Compressed Instructions), 'F' (Single-Precision Floating-Point){{$}} +# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set{{$}} c.flw fa3, 124(a5) # CHECK-ASM-AND-OBJ: c.fsw fa2, 124(a1) # CHECK-ASM: encoding: [0xf0,0xfd] -# CHECK-NO-EXT-F: error: instruction requires the following: 'F' (Single-Precision Floating-Point) -# CHECK-NO-EXT-FC: error: instruction requires the following: 'C' (Compressed Instructions), 'F' (Single-Precision Floating-Point) -# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set +# CHECK-NO-EXT-F: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} +# CHECK-NO-EXT-FC: error: instruction requires the following: 'C' (Compressed Instructions), 'F' (Single-Precision Floating-Point){{$}} +# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set{{$}} c.fsw fa2, 124(a1) diff --git a/llvm/test/MC/RISCV/rv32i-aliases-invalid.s b/llvm/test/MC/RISCV/rv32i-aliases-invalid.s --- a/llvm/test/MC/RISCV/rv32i-aliases-invalid.s +++ b/llvm/test/MC/RISCV/rv32i-aliases-invalid.s @@ -9,9 +9,9 @@ li x0, -2147483649 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295] li t4, foo # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295] -negw x1, x2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -sext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -zext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +negw x1, x2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +sext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +zext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} sll x2, x3, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31] srl x2, x3, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31] diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s --- a/llvm/test/MC/RISCV/rv32i-invalid.s +++ b/llvm/test/MC/RISCV/rv32i-invalid.s @@ -151,8 +151,8 @@ slt x32, s0, s0 # CHECK: :[[@LINE]]:5: error: invalid operand for instruction # RV64I mnemonics -addiw a0, sp, 100 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -sraw t0, s2, zero # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +addiw a0, sp, 100 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +sraw t0, s2, zero # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} # Invalid operand types xori sp, 22, 220 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction @@ -169,19 +169,19 @@ xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Instruction not in the base ISA -div a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'M' (Integer Multiplication and Division) -amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions) +div a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'M' (Integer Multiplication and Division){{$}} +amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions){{$}} fadd.s ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} -fadd.h ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) -fadd.s a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfinx' (Float in Integer) -fadd.d a0, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer) -fadd.h a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer) +fadd.h ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}} +fadd.s a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfinx' (Float in Integer){{$}} +fadd.d a0, a2, a4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer){{$}} +fadd.h a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer){{$}} flh ft0, (a0) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}} -sh1add a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zba' (Address Generation Instructions) -clz a0, a1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation) -clmul a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbc' (Carry-Less Multiplication) -bset a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbs' (Single-Bit Instructions) -pause # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zihintpause' (Pause Hint) +sh1add a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zba' (Address Generation Instructions){{$}} +clz a0, a1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation){{$}} +clmul a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbc' (Carry-Less Multiplication) or 'Zbkc' (Carry-less multiply instructions for Cryptography){{$}} +bset a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbs' (Single-Bit Instructions){{$}} +pause # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zihintpause' (Pause Hint){{$}} # Using floating point registers when integer registers are expected addi a2, ft0, 24 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv32m-invalid.s b/llvm/test/MC/RISCV/rv32m-invalid.s --- a/llvm/test/MC/RISCV/rv32m-invalid.s +++ b/llvm/test/MC/RISCV/rv32m-invalid.s @@ -1,9 +1,9 @@ # RUN: not llvm-mc -triple riscv32 -mattr=+m < %s 2>&1 | FileCheck %s # RV64M instructions can't be used for RV32 -mulw ra, sp, gp # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -divw tp, t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -divuw t2, s0, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -remw a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -remuw a3, a4, a5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +mulw ra, sp, gp # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +divw tp, t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +divuw t2, s0, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +remw a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +remuw a3, a4, a5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} diff --git a/llvm/test/MC/RISCV/rv32zba-invalid.s b/llvm/test/MC/RISCV/rv32zba-invalid.s --- a/llvm/test/MC/RISCV/rv32zba-invalid.s +++ b/llvm/test/MC/RISCV/rv32zba-invalid.s @@ -6,8 +6,8 @@ sh2add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Too few operands sh3add t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -slli.uw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -sh1add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -sh2add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -sh3add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +slli.uw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +sh1add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +sh2add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +sh3add.uw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} diff --git a/llvm/test/MC/RISCV/rv32zbb-invalid.s b/llvm/test/MC/RISCV/rv32zbb-invalid.s --- a/llvm/test/MC/RISCV/rv32zbb-invalid.s +++ b/llvm/test/MC/RISCV/rv32zbb-invalid.s @@ -18,6 +18,6 @@ minu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Too few operands maxu t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -clzw t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -ctzw t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -cpopw t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +clzw t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +ctzw t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +cpopw t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} diff --git a/llvm/test/MC/RISCV/rv32zbbp-invalid.s b/llvm/test/MC/RISCV/rv32zbbp-invalid.s --- a/llvm/test/MC/RISCV/rv32zbbp-invalid.s +++ b/llvm/test/MC/RISCV/rv32zbbp-invalid.s @@ -15,7 +15,7 @@ # Immediate operand out of range rori t0, t1, 32 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] rori t0, t1, -1 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] -rolw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -rorw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -roriw t0, t1, 31 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -roriw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +rolw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +rorw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +roriw t0, t1, 31 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +roriw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} diff --git a/llvm/test/MC/RISCV/rv32zbe-invalid.s b/llvm/test/MC/RISCV/rv32zbe-invalid.s --- a/llvm/test/MC/RISCV/rv32zbe-invalid.s +++ b/llvm/test/MC/RISCV/rv32zbe-invalid.s @@ -4,5 +4,5 @@ bdecompress t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Too few operands bcompress t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -bdecompressw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -bcompressw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +bdecompressw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +bcompressw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} diff --git a/llvm/test/MC/RISCV/rv32zbf-invalid.s b/llvm/test/MC/RISCV/rv32zbf-invalid.s --- a/llvm/test/MC/RISCV/rv32zbf-invalid.s +++ b/llvm/test/MC/RISCV/rv32zbf-invalid.s @@ -2,4 +2,4 @@ # Too few operands bfp t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -bfpw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +bfpw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} diff --git a/llvm/test/MC/RISCV/rv32zbkc-invalid.s b/llvm/test/MC/RISCV/rv32zbkc-invalid.s --- a/llvm/test/MC/RISCV/rv32zbkc-invalid.s +++ b/llvm/test/MC/RISCV/rv32zbkc-invalid.s @@ -6,4 +6,4 @@ clmulh t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Undefined zbc instruction in zbkc -clmulr t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbc' (Carry-Less Multiplication) +clmulr t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbc' (Carry-Less Multiplication){{$}} diff --git a/llvm/test/MC/RISCV/rv32zbkx-invalid.s b/llvm/test/MC/RISCV/rv32zbkx-invalid.s --- a/llvm/test/MC/RISCV/rv32zbkx-invalid.s +++ b/llvm/test/MC/RISCV/rv32zbkx-invalid.s @@ -6,4 +6,4 @@ xperm4 t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Undefined Zbp instruction in Zbkx -xperm.h t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbp' (Permutation 'Zb' Instructions) +xperm.h t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbp' (Permutation 'Zb' Instructions){{$}} diff --git a/llvm/test/MC/RISCV/rv32zbp-invalid.s b/llvm/test/MC/RISCV/rv32zbp-invalid.s --- a/llvm/test/MC/RISCV/rv32zbp-invalid.s +++ b/llvm/test/MC/RISCV/rv32zbp-invalid.s @@ -40,12 +40,12 @@ xperm.b t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Too few operands xperm.h t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction -gorcw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -grevw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -gorciw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -greviw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -shflw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -unshflw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -packw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -packuw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -xperm.w t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +gorcw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +grevw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +gorciw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +greviw t0, t1, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +shflw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +unshflw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +packw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +packuw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +xperm.w t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} diff --git a/llvm/test/MC/RISCV/rv32zbr-invalid.s b/llvm/test/MC/RISCV/rv32zbr-invalid.s --- a/llvm/test/MC/RISCV/rv32zbr-invalid.s +++ b/llvm/test/MC/RISCV/rv32zbr-invalid.s @@ -12,5 +12,5 @@ crc32c.h t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction # Too many operands crc32c.w t0, t1, t2 # CHECK: :[[@LINE]]:18: error: invalid operand for instruction -crc32.d t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -crc32c.d t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +crc32.d t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +crc32c.d t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} diff --git a/llvm/test/MC/RISCV/rv32zbt-invalid.s b/llvm/test/MC/RISCV/rv32zbt-invalid.s --- a/llvm/test/MC/RISCV/rv32zbt-invalid.s +++ b/llvm/test/MC/RISCV/rv32zbt-invalid.s @@ -13,6 +13,6 @@ # Immediate operand out of range fsri t0, t1, t2, 32 # CHECK: :[[@LINE]]:18: error: immediate must be an integer in the range [0, 31] fsri t0, t1, t2, -1 # CHECK: :[[@LINE]]:18: error: immediate must be an integer in the range [0, 31] -fslw t0, t1, t2, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -fsrw t0, t1, t2, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -fsriw t0, t1, t2, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set +fslw t0, t1, t2, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +fsrw t0, t1, t2, t3 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} +fsriw t0, t1, t2, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} diff --git a/llvm/test/MC/RISCV/rv32zdinx-invalid.s b/llvm/test/MC/RISCV/rv32zdinx-invalid.s --- a/llvm/test/MC/RISCV/rv32zdinx-invalid.s +++ b/llvm/test/MC/RISCV/rv32zdinx-invalid.s @@ -4,8 +4,8 @@ fadd.d a0, a1, a2 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction # Not support float registers -flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point) -fadd.d fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'D' (Double-Precision Floating-Point) +flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} +fadd.d fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} # Invalid instructions fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv32zfhmin-invalid.s b/llvm/test/MC/RISCV/rv32zfhmin-invalid.s --- a/llvm/test/MC/RISCV/rv32zfhmin-invalid.s +++ b/llvm/test/MC/RISCV/rv32zfhmin-invalid.s @@ -22,4 +22,4 @@ fmv.h.x a8, ft2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction # Zfh instructions -fmadd.h f10, f11, f12, f13, dyn # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) +fmadd.h f10, f11, f12, f13, dyn # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}} diff --git a/llvm/test/MC/RISCV/rv32zfinx-invalid.s b/llvm/test/MC/RISCV/rv32zfinx-invalid.s --- a/llvm/test/MC/RISCV/rv32zfinx-invalid.s +++ b/llvm/test/MC/RISCV/rv32zfinx-invalid.s @@ -1,13 +1,13 @@ # RUN: not llvm-mc -triple riscv32 -mattr=+zfinx %s 2>&1 | FileCheck %s # Not support float registers -flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point) -fadd.s fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point) +flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} +fadd.s fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} # Invalid instructions fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction fmv.x.w s0, s1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction -fadd.d t1, t3, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer) +fadd.d t1, t3, t5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zdinx' (Double in Integer){{$}} # Invalid register names fadd.d a100, a2, a3 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv32zhinx-invalid.s b/llvm/test/MC/RISCV/rv32zhinx-invalid.s --- a/llvm/test/MC/RISCV/rv32zhinx-invalid.s +++ b/llvm/test/MC/RISCV/rv32zhinx-invalid.s @@ -1,8 +1,8 @@ # RUN: not llvm-mc -triple riscv32 -mattr=+zhinx %s 2>&1 | FileCheck %s # Not support float registers -flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point) -fadd.h fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) +flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} +fadd.h fa0, fa1, fa2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point){{$}} # Invalid instructions fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s b/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s --- a/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s +++ b/llvm/test/MC/RISCV/rv32zhinxmin-invalid.s @@ -1,8 +1,8 @@ # RUN: not llvm-mc -triple riscv32 -mattr=+zhinxmin %s 2>&1 | FileCheck %s # Not support float registers -flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point) -fcvt.h.s fa0, fa1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) +flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} +fcvt.h.s fa0, fa1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}} # Invalid instructions fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction @@ -12,4 +12,4 @@ fcvt.h.s a100, a1 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction # Valid in Zhinx -fmadd.h x10, x11, x12, x13, dyn # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer) +fmadd.h x10, x11, x12, x13, dyn # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zhinx' (Half Float in Integer){{$}} diff --git a/llvm/test/MC/RISCV/rv32zicbom-invalid.s b/llvm/test/MC/RISCV/rv32zicbom-invalid.s --- a/llvm/test/MC/RISCV/rv32zicbom-invalid.s +++ b/llvm/test/MC/RISCV/rv32zicbom-invalid.s @@ -21,7 +21,7 @@ # Instructions from other zicbo* extensions aren't available without enabling # the appropriate -mattr flag. -cbo.zero (t0) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicboz' (Cache-Block Zero Instructions) -prefetch.i 0(t3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbop' (Cache-Block Prefetch Instructions) -prefetch.r 0(t4) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbop' (Cache-Block Prefetch Instructions) -prefetch.w 0(t5) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbop' (Cache-Block Prefetch Instructions) +cbo.zero (t0) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicboz' (Cache-Block Zero Instructions){{$}} +prefetch.i 0(t3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbop' (Cache-Block Prefetch Instructions){{$}} +prefetch.r 0(t4) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbop' (Cache-Block Prefetch Instructions){{$}} +prefetch.w 0(t5) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbop' (Cache-Block Prefetch Instructions){{$}} diff --git a/llvm/test/MC/RISCV/rv32zicbop-invalid.s b/llvm/test/MC/RISCV/rv32zicbop-invalid.s --- a/llvm/test/MC/RISCV/rv32zicbop-invalid.s +++ b/llvm/test/MC/RISCV/rv32zicbop-invalid.s @@ -23,7 +23,7 @@ # Instructions from other zicbo* extensions aren't available without enabling # the appropriate -mattr flag. -cbo.clean (t0) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbom' (Cache-Block Management Instructions) -cbo.flush (t1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbom' (Cache-Block Management Instructions) -cbo.inval (t2) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbom' (Cache-Block Management Instructions) -cbo.zero (t0) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicboz' (Cache-Block Zero Instructions) +cbo.clean (t0) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbom' (Cache-Block Management Instructions){{$}} +cbo.flush (t1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbom' (Cache-Block Management Instructions){{$}} +cbo.inval (t2) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbom' (Cache-Block Management Instructions){{$}} +cbo.zero (t0) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicboz' (Cache-Block Zero Instructions){{$}} diff --git a/llvm/test/MC/RISCV/rv32zicboz-invalid.s b/llvm/test/MC/RISCV/rv32zicboz-invalid.s --- a/llvm/test/MC/RISCV/rv32zicboz-invalid.s +++ b/llvm/test/MC/RISCV/rv32zicboz-invalid.s @@ -11,9 +11,9 @@ # Instructions from other zicbo* extensions aren't available without enabling # the appropriate -mattr flag. -cbo.clean (t0) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbom' (Cache-Block Management Instructions) -cbo.flush (t1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbom' (Cache-Block Management Instructions) -cbo.inval (t2) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbom' (Cache-Block Management Instructions) -prefetch.i 0(t3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbop' (Cache-Block Prefetch Instructions) -prefetch.r 0(t4) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbop' (Cache-Block Prefetch Instructions) -prefetch.w 0(t5) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbop' (Cache-Block Prefetch Instructions) +cbo.clean (t0) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbom' (Cache-Block Management Instructions){{$}} +cbo.flush (t1) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbom' (Cache-Block Management Instructions){{$}} +cbo.inval (t2) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbom' (Cache-Block Management Instructions){{$}} +prefetch.i 0(t3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbop' (Cache-Block Prefetch Instructions){{$}} +prefetch.r 0(t4) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbop' (Cache-Block Prefetch Instructions){{$}} +prefetch.w 0(t5) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zicbop' (Cache-Block Prefetch Instructions){{$}} diff --git a/llvm/test/MC/RISCV/rv32zmmul-invaild.s b/llvm/test/MC/RISCV/rv32zmmul-invaild.s --- a/llvm/test/MC/RISCV/rv32zmmul-invaild.s +++ b/llvm/test/MC/RISCV/rv32zmmul-invaild.s @@ -1,14 +1,14 @@ # RUN: not llvm-mc %s -triple=riscv32 -mattr=+zmmul -riscv-no-aliases 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-ERROR %s -# CHECK-ERROR: 5:1: error: instruction requires the following: 'M' (Integer Multiplication and Division) +# CHECK-ERROR: 5:1: error: instruction requires the following: 'M' (Integer Multiplication and Division){{$}} div s0, s0, s0 -# CHECK-ERROR: 8:1: error: instruction requires the following: 'M' (Integer Multiplication and Division) +# CHECK-ERROR: 8:1: error: instruction requires the following: 'M' (Integer Multiplication and Division){{$}} divu gp, a0, a1 -# CHECK-ERROR: 11:1: error: instruction requires the following: 'M' (Integer Multiplication and Division) +# CHECK-ERROR: 11:1: error: instruction requires the following: 'M' (Integer Multiplication and Division){{$}} rem s2, s2, s8 -# CHECK-ERROR: 14:1: error: instruction requires the following: 'M' (Integer Multiplication and Division) +# CHECK-ERROR: 14:1: error: instruction requires the following: 'M' (Integer Multiplication and Division){{$}} remu x18, x18, x24 diff --git a/llvm/test/MC/RISCV/rv64a-valid.s b/llvm/test/MC/RISCV/rv64a-valid.s --- a/llvm/test/MC/RISCV/rv64a-valid.s +++ b/llvm/test/MC/RISCV/rv64a-valid.s @@ -9,183 +9,183 @@ # CHECK-ASM-AND-OBJ: lr.d t0, (t1) # CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} lr.d t0, (t1) # CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2) # CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} lr.d.aq t1, (t2) # CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3) # CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} lr.d.rl t2, (t3) # CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4) # CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} lr.d.aqrl t3, (t4) # CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4) # CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} sc.d t6, t5, (t4) # CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3) # CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} sc.d.aq t5, t4, (t3) # CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2) # CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} sc.d.rl t4, t3, (t2) # CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1) # CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} sc.d.aqrl t3, t2, (t1) # CHECK-ASM-AND-OBJ: amoswap.d a4, ra, (s0) # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x08] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoswap.d a4, ra, (s0) # CHECK-ASM-AND-OBJ: amoadd.d a1, a2, (a3) # CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x00] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoadd.d a1, a2, (a3) # CHECK-ASM-AND-OBJ: amoxor.d a2, a3, (a4) # CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x20] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoxor.d a2, a3, (a4) # CHECK-ASM-AND-OBJ: amoand.d a3, a4, (a5) # CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x60] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoand.d a3, a4, (a5) # CHECK-ASM-AND-OBJ: amoor.d a4, a5, (a6) # CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x40] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoor.d a4, a5, (a6) # CHECK-ASM-AND-OBJ: amomin.d a5, a6, (a7) # CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x81] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amomin.d a5, a6, (a7) # CHECK-ASM-AND-OBJ: amomax.d s7, s6, (s5) # CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa1] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amomax.d s7, s6, (s5) # CHECK-ASM-AND-OBJ: amominu.d s6, s5, (s4) # CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc1] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amominu.d s6, s5, (s4) # CHECK-ASM-AND-OBJ: amomaxu.d s5, s4, (s3) # CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe1] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amomaxu.d s5, s4, (s3) # CHECK-ASM-AND-OBJ: amoswap.d.aq a4, ra, (s0) # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0c] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoswap.d.aq a4, ra, (s0) # CHECK-ASM-AND-OBJ: amoadd.d.aq a1, a2, (a3) # CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x04] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoadd.d.aq a1, a2, (a3) # CHECK-ASM-AND-OBJ: amoxor.d.aq a2, a3, (a4) # CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x24] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoxor.d.aq a2, a3, (a4) # CHECK-ASM-AND-OBJ: amoand.d.aq a3, a4, (a5) # CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x64] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoand.d.aq a3, a4, (a5) # CHECK-ASM-AND-OBJ: amoor.d.aq a4, a5, (a6) # CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x44] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoor.d.aq a4, a5, (a6) # CHECK-ASM-AND-OBJ: amomin.d.aq a5, a6, (a7) # CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x85] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amomin.d.aq a5, a6, (a7) # CHECK-ASM-AND-OBJ: amomax.d.aq s7, s6, (s5) # CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa5] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amomax.d.aq s7, s6, (s5) # CHECK-ASM-AND-OBJ: amominu.d.aq s6, s5, (s4) # CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc5] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amominu.d.aq s6, s5, (s4) # CHECK-ASM-AND-OBJ: amomaxu.d.aq s5, s4, (s3) # CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe5] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amomaxu.d.aq s5, s4, (s3) # CHECK-ASM-AND-OBJ: amoswap.d.rl a4, ra, (s0) # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0a] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoswap.d.rl a4, ra, (s0) # CHECK-ASM-AND-OBJ: amoadd.d.rl a1, a2, (a3) # CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x02] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoadd.d.rl a1, a2, (a3) # CHECK-ASM-AND-OBJ: amoxor.d.rl a2, a3, (a4) # CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x22] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoxor.d.rl a2, a3, (a4) # CHECK-ASM-AND-OBJ: amoand.d.rl a3, a4, (a5) # CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x62] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoand.d.rl a3, a4, (a5) # CHECK-ASM-AND-OBJ: amoor.d.rl a4, a5, (a6) # CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x42] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoor.d.rl a4, a5, (a6) # CHECK-ASM-AND-OBJ: amomin.d.rl a5, a6, (a7) # CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x83] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amomin.d.rl a5, a6, (a7) # CHECK-ASM-AND-OBJ: amomax.d.rl s7, s6, (s5) # CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa3] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amomax.d.rl s7, s6, (s5) # CHECK-ASM-AND-OBJ: amominu.d.rl s6, s5, (s4) # CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc3] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amominu.d.rl s6, s5, (s4) # CHECK-ASM-AND-OBJ: amomaxu.d.rl s5, s4, (s3) # CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe3] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amomaxu.d.rl s5, s4, (s3) # CHECK-ASM-AND-OBJ: amoswap.d.aqrl a4, ra, (s0) # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0e] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoswap.d.aqrl a4, ra, (s0) # CHECK-ASM-AND-OBJ: amoadd.d.aqrl a1, a2, (a3) # CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x06] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoadd.d.aqrl a1, a2, (a3) # CHECK-ASM-AND-OBJ: amoxor.d.aqrl a2, a3, (a4) # CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x26] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoxor.d.aqrl a2, a3, (a4) # CHECK-ASM-AND-OBJ: amoand.d.aqrl a3, a4, (a5) # CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x66] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoand.d.aqrl a3, a4, (a5) # CHECK-ASM-AND-OBJ: amoor.d.aqrl a4, a5, (a6) # CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x46] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amoor.d.aqrl a4, a5, (a6) # CHECK-ASM-AND-OBJ: amomin.d.aqrl a5, a6, (a7) # CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x87] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amomin.d.aqrl a5, a6, (a7) # CHECK-ASM-AND-OBJ: amomax.d.aqrl s7, s6, (s5) # CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa7] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amomax.d.aqrl s7, s6, (s5) # CHECK-ASM-AND-OBJ: amominu.d.aqrl s6, s5, (s4) # CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc7] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amominu.d.aqrl s6, s5, (s4) # CHECK-ASM-AND-OBJ: amomaxu.d.aqrl s5, s4, (s3) # CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe7] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} amomaxu.d.aqrl s5, s4, (s3) diff --git a/llvm/test/MC/RISCV/rv64c-valid.s b/llvm/test/MC/RISCV/rv64c-valid.s --- a/llvm/test/MC/RISCV/rv64c-valid.s +++ b/llvm/test/MC/RISCV/rv64c-valid.s @@ -16,56 +16,56 @@ # CHECK-ASM-AND-OBJ: c.ldsp ra, 0(sp) # CHECK-ASM: encoding: [0x82,0x60] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) -# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} +# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}} c.ldsp ra, 0(sp) # CHECK-ASM-AND-OBJ: c.sdsp ra, 504(sp) # CHECK-ASM: encoding: [0x86,0xff] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) -# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} +# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}} c.sdsp ra, 504(sp) # CHECK-ASM-AND-OBJ: c.ld a4, 0(a3) # CHECK-ASM: encoding: [0x98,0x62] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) -# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} +# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}} c.ld a4, 0(a3) # CHECK-ASM-AND-OBJ: c.sd a5, 248(a3) # CHECK-ASM: encoding: [0xfc,0xfe] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) -# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} +# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}} c.sd a5, 248(a3) # CHECK-ASM-AND-OBJ: c.subw a3, a4 # CHECK-ASM: encoding: [0x99,0x9e] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) -# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} +# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}} c.subw a3, a4 # CHECK-ASM-AND-OBJ: c.addw a0, a2 # CHECK-ASM: encoding: [0x31,0x9d] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) -# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} +# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}} c.addw a0, a2 # CHECK-ASM-AND-OBJ: c.addiw a3, -32 # CHECK-ASM: encoding: [0x81,0x36] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) -# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} +# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}} c.addiw a3, -32 # CHECK-ASM-AND-OBJ: c.addiw a3, 31 # CHECK-ASM: encoding: [0xfd,0x26] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) -# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} +# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set{{$}} c.addiw a3, 31 # CHECK-ASM-AND-OBJ: c.slli s0, 63 # CHECK-ASM: encoding: [0x7e,0x14] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.slli s0, 63 # CHECK-ASM-AND-OBJ: c.srli a3, 63 # CHECK-ASM: encoding: [0xfd,0x92] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.srli a3, 63 # CHECK-ASM-AND-OBJ: c.srai a2, 63 # CHECK-ASM: encoding: [0x7d,0x96] -# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions) +# CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions){{$}} c.srai a2, 63 diff --git a/llvm/test/MC/RISCV/rv64d-valid.s b/llvm/test/MC/RISCV/rv64d-valid.s --- a/llvm/test/MC/RISCV/rv64d-valid.s +++ b/llvm/test/MC/RISCV/rv64d-valid.s @@ -9,43 +9,43 @@ # CHECK-ASM-AND-OBJ: fcvt.l.d a0, ft0, dyn # CHECK-ASM: encoding: [0x53,0x75,0x20,0xc2] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.l.d a0, ft0, dyn # CHECK-ASM-AND-OBJ: fcvt.lu.d a1, ft1, dyn # CHECK-ASM: encoding: [0xd3,0xf5,0x30,0xc2] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.lu.d a1, ft1, dyn # CHECK-ASM-AND-OBJ: fmv.x.d a2, ft2 # CHECK-ASM: encoding: [0x53,0x06,0x01,0xe2] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fmv.x.d a2, ft2 # CHECK-ASM-AND-OBJ: fcvt.d.l ft3, a3, dyn # CHECK-ASM: encoding: [0xd3,0xf1,0x26,0xd2] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.d.l ft3, a3, dyn # CHECK-ASM-AND-OBJ: fcvt.d.lu ft4, a4, dyn # CHECK-ASM: encoding: [0x53,0x72,0x37,0xd2] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.d.lu ft4, a4, dyn # CHECK-ASM-AND-OBJ: fmv.d.x ft5, a5 # CHECK-ASM: encoding: [0xd3,0x82,0x07,0xf2] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fmv.d.x ft5, a5 # Rounding modes # CHECK-ASM-AND-OBJ: fcvt.d.l ft3, a3, rne # CHECK-ASM: encoding: [0xd3,0x81,0x26,0xd2] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.d.l ft3, a3, rne # CHECK-ASM-AND-OBJ: fcvt.d.lu ft4, a4, rtz # CHECK-ASM: encoding: [0x53,0x12,0x37,0xd2] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.d.lu ft4, a4, rtz # CHECK-ASM-AND-OBJ: fcvt.l.d a0, ft0, rdn # CHECK-ASM: encoding: [0x53,0x25,0x20,0xc2] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.l.d a0, ft0, rdn # CHECK-ASM-AND-OBJ: fcvt.lu.d a1, ft1, rup # CHECK-ASM: encoding: [0xd3,0xb5,0x30,0xc2] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.lu.d a1, ft1, rup diff --git a/llvm/test/MC/RISCV/rv64dc-valid.s b/llvm/test/MC/RISCV/rv64dc-valid.s --- a/llvm/test/MC/RISCV/rv64dc-valid.s +++ b/llvm/test/MC/RISCV/rv64dc-valid.s @@ -12,22 +12,22 @@ # CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp) # CHECK-ASM: encoding: [0x7e,0x34] -# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point) -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point) +# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fldsp fs0, 504(sp) # CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp) # CHECK-ASM: encoding: [0xc6,0xbf] -# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point) -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point) +# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fsdsp fa7, 504(sp) # CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5) # CHECK-ASM: encoding: [0xf4,0x3f] -# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point) -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point) +# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fld fa3, 248(a5) # CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1) # CHECK-ASM: encoding: [0xf0,0xbd] -# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point) -# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point) +# CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} +# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point){{$}} c.fsd fa2, 248(a1) diff --git a/llvm/test/MC/RISCV/rv64f-valid.s b/llvm/test/MC/RISCV/rv64f-valid.s --- a/llvm/test/MC/RISCV/rv64f-valid.s +++ b/llvm/test/MC/RISCV/rv64f-valid.s @@ -9,31 +9,31 @@ # CHECK-ASM-AND-OBJ: fcvt.l.s a0, ft0, dyn # CHECK-ASM: encoding: [0x53,0x75,0x20,0xc0] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.l.s a0, ft0, dyn # CHECK-ASM-AND-OBJ: fcvt.lu.s a1, ft1, dyn # CHECK-ASM: encoding: [0xd3,0xf5,0x30,0xc0] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.lu.s a1, ft1, dyn # CHECK-ASM-AND-OBJ: fcvt.s.l ft2, a2, dyn # CHECK-ASM: encoding: [0x53,0x71,0x26,0xd0] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.s.l ft2, a2, dyn # CHECK-ASM-AND-OBJ: fcvt.s.lu ft3, a3, dyn # CHECK-ASM: encoding: [0xd3,0xf1,0x36,0xd0] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.s.lu ft3, a3, dyn # Rounding modes # CHECK-ASM-AND-OBJ: fcvt.l.s a4, ft4, rne -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.l.s a4, ft4, rne # CHECK-ASM-AND-OBJ: fcvt.lu.s a5, ft5, rtz -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.lu.s a5, ft5, rtz # CHECK-ASM-AND-OBJ: fcvt.s.l ft6, a6, rdn -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.s.l ft6, a6, rdn # CHECK-ASM-AND-OBJ: fcvt.s.lu ft7, a7, rup -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.s.lu ft7, a7, rup diff --git a/llvm/test/MC/RISCV/rv64i-aliases-invalid.s b/llvm/test/MC/RISCV/rv64i-aliases-invalid.s --- a/llvm/test/MC/RISCV/rv64i-aliases-invalid.s +++ b/llvm/test/MC/RISCV/rv64i-aliases-invalid.s @@ -5,9 +5,9 @@ li t5, 0x10000000000000000 # CHECK: :[[@LINE]]:8: error: unknown operand li t4, foo # CHECK: :[[@LINE]]:8: error: operand must be a constant 64-bit integer -rdinstreth x29 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set -rdcycleh x27 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set -rdtimeh x28 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set +rdinstreth x29 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set{{$}} +rdcycleh x27 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set{{$}} +rdtimeh x28 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set{{$}} sll x2, x3, 64 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63] srl x2, x3, 64 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63] diff --git a/llvm/test/MC/RISCV/rv64zdinx-invalid.s b/llvm/test/MC/RISCV/rv64zdinx-invalid.s --- a/llvm/test/MC/RISCV/rv64zdinx-invalid.s +++ b/llvm/test/MC/RISCV/rv64zdinx-invalid.s @@ -1,7 +1,7 @@ # RUN: not llvm-mc -triple riscv64 -mattr=+zdinx %s 2>&1 | FileCheck %s # Not support float registers -fld fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'D' (Double-Precision Floating-Point) +fld fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'D' (Double-Precision Floating-Point){{$}} ld a0, -2049(a1) # CHECK: :[[@LINE]]:8: error: operand must be a symbol with %lo/%pcrel_lo/%tprel_lo modifier or an integer in the range [-2048, 2047] # Invalid instructions diff --git a/llvm/test/MC/RISCV/rv64zfh-valid.s b/llvm/test/MC/RISCV/rv64zfh-valid.s --- a/llvm/test/MC/RISCV/rv64zfh-valid.s +++ b/llvm/test/MC/RISCV/rv64zfh-valid.s @@ -9,31 +9,31 @@ # CHECK-ASM-AND-OBJ: fcvt.l.h a0, ft0, dyn # CHECK-ASM: encoding: [0x53,0x75,0x20,0xc4] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.l.h a0, ft0, dyn # CHECK-ASM-AND-OBJ: fcvt.lu.h a1, ft1, dyn # CHECK-ASM: encoding: [0xd3,0xf5,0x30,0xc4] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.lu.h a1, ft1, dyn # CHECK-ASM-AND-OBJ: fcvt.h.l ft2, a2, dyn # CHECK-ASM: encoding: [0x53,0x71,0x26,0xd4] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.h.l ft2, a2, dyn # CHECK-ASM-AND-OBJ: fcvt.h.lu ft3, a3, dyn # CHECK-ASM: encoding: [0xd3,0xf1,0x36,0xd4] -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.h.lu ft3, a3, dyn # Rounding modes # CHECK-ASM-AND-OBJ: fcvt.l.h a4, ft4, rne -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.l.h a4, ft4, rne # CHECK-ASM-AND-OBJ: fcvt.lu.h a5, ft5, rtz -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.lu.h a5, ft5, rtz # CHECK-ASM-AND-OBJ: fcvt.h.l ft6, a6, rdn -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.h.l ft6, a6, rdn # CHECK-ASM-AND-OBJ: fcvt.h.lu ft7, a7, rup -# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.h.lu ft7, a7, rup diff --git a/llvm/test/MC/RISCV/rv64zfinx-invalid.s b/llvm/test/MC/RISCV/rv64zfinx-invalid.s --- a/llvm/test/MC/RISCV/rv64zfinx-invalid.s +++ b/llvm/test/MC/RISCV/rv64zfinx-invalid.s @@ -1,7 +1,7 @@ # RUN: not llvm-mc -triple riscv64 -mattr=+zfinx %s 2>&1 | FileCheck %s # Not support float registers -flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point) +flw fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point){{$}} # Invalid instructions fsw a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv64zfinx-valid.s b/llvm/test/MC/RISCV/rv64zfinx-valid.s --- a/llvm/test/MC/RISCV/rv64zfinx-valid.s +++ b/llvm/test/MC/RISCV/rv64zfinx-valid.s @@ -9,35 +9,35 @@ # CHECK-ASM-AND-OBJ: fcvt.l.s a0, t0, dyn # CHECK-ASM: encoding: [0x53,0xf5,0x22,0xc0] -# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.l.s a0, t0, dyn # CHECK-ASM-AND-OBJ: fcvt.lu.s a1, t1, dyn # CHECK-ASM: encoding: [0xd3,0x75,0x33,0xc0] -# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.lu.s a1, t1, dyn # CHECK-ASM-AND-OBJ: fcvt.s.l t2, a2, dyn # CHECK-ASM: encoding: [0xd3,0x73,0x26,0xd0] -# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.s.l t2, a2, dyn # CHECK-ASM-AND-OBJ: fcvt.s.lu t3, a3, dyn # CHECK-ASM: encoding: [0x53,0xfe,0x36,0xd0] -# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.s.lu t3, a3, dyn # Rounding modes # CHECK-ASM-AND-OBJ: fcvt.l.s a4, t4, rne # CHECK-ASM: encoding: [0x53,0x87,0x2e,0xc0] -# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.l.s a4, t4, rne # CHECK-ASM-AND-OBJ: fcvt.lu.s a5, t5, rtz # CHECK-ASM: encoding: [0xd3,0x17,0x3f,0xc0] -# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.lu.s a5, t5, rtz # CHECK-ASM-AND-OBJ: fcvt.s.l t6, a6, rdn # CHECK-ASM: encoding: [0xd3,0x2f,0x28,0xd0] -# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.s.l t6, a6, rdn # CHECK-ASM-AND-OBJ: fcvt.s.lu s7, a7, rup # CHECK-ASM: encoding: [0xd3,0xbb,0x38,0xd0] -# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.s.lu s7, a7, rup diff --git a/llvm/test/MC/RISCV/rv64zhinx-invalid.s b/llvm/test/MC/RISCV/rv64zhinx-invalid.s --- a/llvm/test/MC/RISCV/rv64zhinx-invalid.s +++ b/llvm/test/MC/RISCV/rv64zhinx-invalid.s @@ -1,7 +1,7 @@ # RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s # Not support float registers -flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) +flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}} # Invalid instructions fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv64zhinx-valid.s b/llvm/test/MC/RISCV/rv64zhinx-valid.s --- a/llvm/test/MC/RISCV/rv64zhinx-valid.s +++ b/llvm/test/MC/RISCV/rv64zhinx-valid.s @@ -9,35 +9,35 @@ # CHECK-ASM-AND-OBJ: fcvt.l.h a0, t0, dyn # CHECK-ASM: encoding: [0x53,0xf5,0x22,0xc4] -# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.l.h a0, t0, dyn # CHECK-ASM-AND-OBJ: fcvt.lu.h a1, t1, dyn # CHECK-ASM: encoding: [0xd3,0x75,0x33,0xc4] -# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.lu.h a1, t1, dyn # CHECK-ASM-AND-OBJ: fcvt.h.l t2, a2, dyn # CHECK-ASM: encoding: [0xd3,0x73,0x26,0xd4] -# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.h.l t2, a2, dyn # CHECK-ASM-AND-OBJ: fcvt.h.lu t3, a3, dyn # CHECK-ASM: encoding: [0x53,0xfe,0x36,0xd4] -# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.h.lu t3, a3, dyn # Rounding modes # CHECK-ASM-AND-OBJ: fcvt.l.h a4, t4, rne # CHECK-ASM: encoding: [0x53,0x87,0x2e,0xc4] -# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.l.h a4, t4, rne # CHECK-ASM-AND-OBJ: fcvt.lu.h a5, t5, rtz # CHECK-ASM: encoding: [0xd3,0x17,0x3f,0xc4] -# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.lu.h a5, t5, rtz # CHECK-ASM-AND-OBJ: fcvt.h.l t6, a6, rdn # CHECK-ASM: encoding: [0xd3,0x2f,0x28,0xd4] -# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.h.l t6, a6, rdn # CHECK-ASM-AND-OBJ: fcvt.h.lu s7, a7, rup # CHECK-ASM: encoding: [0xd3,0xbb,0x38,0xd4] -# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set +# CHECK-RV32: :[[#@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}} fcvt.h.lu s7, a7, rup diff --git a/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s b/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s --- a/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s +++ b/llvm/test/MC/RISCV/rv64zhinxmin-invalid.s @@ -1,7 +1,7 @@ # RUN: not llvm-mc -triple riscv64 -mattr=+zhinxmin %s 2>&1 | FileCheck %s # Not support float registers -flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) +flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}} # Invalid instructions fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv64zmmul-invalid.s b/llvm/test/MC/RISCV/rv64zmmul-invalid.s --- a/llvm/test/MC/RISCV/rv64zmmul-invalid.s +++ b/llvm/test/MC/RISCV/rv64zmmul-invalid.s @@ -1,14 +1,14 @@ # RUN: not llvm-mc %s -triple=riscv64 -mattr=+zmmul -riscv-no-aliases 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-ERROR %s -# CHECK-ERROR: 5:1: error: instruction requires the following: 'M' (Integer Multiplication and Division) +# CHECK-ERROR: 5:1: error: instruction requires the following: 'M' (Integer Multiplication and Division){{$}} divw tp, t0, t1 -# CHECK-ERROR: 8:1: error: instruction requires the following: 'M' (Integer Multiplication and Division) +# CHECK-ERROR: 8:1: error: instruction requires the following: 'M' (Integer Multiplication and Division){{$}} divuw t2, s0, s2 -# CHECK-ERROR: 11:1: error: instruction requires the following: 'M' (Integer Multiplication and Division) +# CHECK-ERROR: 11:1: error: instruction requires the following: 'M' (Integer Multiplication and Division){{$}} remw a0, a1, a2 -# CHECK-ERROR: 14:1: error: instruction requires the following: 'M' (Integer Multiplication and Division) +# CHECK-ERROR: 14:1: error: instruction requires the following: 'M' (Integer Multiplication and Division){{$}} remuw a3, a4, a5 diff --git a/llvm/test/MC/RISCV/rvv/add.s b/llvm/test/MC/RISCV/rvv/add.s --- a/llvm/test/MC/RISCV/rvv/add.s +++ b/llvm/test/MC/RISCV/rvv/add.s @@ -11,353 +11,353 @@ vadd.vv v8, v4, v20, v0.t # CHECK-INST: vadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 00 vadd.vv v8, v4, v20 # CHECK-INST: vadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 02 vadd.vx v8, v4, a0, v0.t # CHECK-INST: vadd.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 00 vadd.vx v8, v4, a0 # CHECK-INST: vadd.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 02 vadd.vi v8, v4, 15, v0.t # CHECK-INST: vadd.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 00 vadd.vi v8, v4, 15 # CHECK-INST: vadd.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 02 vwaddu.vv v8, v4, v20, v0.t # CHECK-INST: vwaddu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xc0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a c0 vwaddu.vv v8, v4, v20 # CHECK-INST: vwaddu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xc2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a c2 vwaddu.vx v8, v4, a0, v0.t # CHECK-INST: vwaddu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xc0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 c0 vwaddu.vx v8, v4, a0 # CHECK-INST: vwaddu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xc2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 c2 vwadd.vv v8, v4, v20, v0.t # CHECK-INST: vwadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xc4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a c4 vwadd.vv v8, v4, v20 # CHECK-INST: vwadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xc6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a c6 vwadd.vx v8, v4, a0, v0.t # CHECK-INST: vwadd.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xc4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 c4 vwadd.vx v8, v4, a0 # CHECK-INST: vwadd.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xc6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 c6 vwaddu.wv v8, v4, v20, v0.t # CHECK-INST: vwaddu.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xd0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a d0 vwaddu.wv v8, v4, v20 # CHECK-INST: vwaddu.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xd2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a d2 vwaddu.wx v8, v4, a0, v0.t # CHECK-INST: vwaddu.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xd0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 d0 vwaddu.wx v8, v4, a0 # CHECK-INST: vwaddu.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xd2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 d2 vwadd.wv v8, v4, v20, v0.t # CHECK-INST: vwadd.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xd4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a d4 vwadd.wv v8, v4, v20 # CHECK-INST: vwadd.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xd6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a d6 vwadd.wx v8, v4, a0, v0.t # CHECK-INST: vwadd.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xd4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 d4 vwadd.wx v8, v4, a0 # CHECK-INST: vwadd.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xd6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 d6 vadc.vvm v8, v4, v20, v0 # CHECK-INST: vadc.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x40] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 40 vadc.vvm v4, v4, v20, v0 # CHECK-INST: vadc.vvm v4, v4, v20, v0 # CHECK-ENCODING: [0x57,0x02,0x4a,0x40] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 02 4a 40 vadc.vvm v8, v4, v8, v0 # CHECK-INST: vadc.vvm v8, v4, v8, v0 # CHECK-ENCODING: [0x57,0x04,0x44,0x40] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 44 40 vadc.vxm v8, v4, a0, v0 # CHECK-INST: vadc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x40] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 40 vadc.vim v8, v4, 15, v0 # CHECK-INST: vadc.vim v8, v4, 15, v0 # CHECK-ENCODING: [0x57,0xb4,0x47,0x40] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 40 vmadc.vvm v8, v4, v20, v0 # CHECK-INST: vmadc.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x44] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 44 vmadc.vvm v4, v4, v20, v0 # CHECK-INST: vmadc.vvm v4, v4, v20, v0 # CHECK-ENCODING: [0x57,0x02,0x4a,0x44] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 02 4a 44 vmadc.vvm v8, v4, v8, v0 # CHECK-INST: vmadc.vvm v8, v4, v8, v0 # CHECK-ENCODING: [0x57,0x04,0x44,0x44] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 44 44 vmadc.vxm v8, v4, a0, v0 # CHECK-INST: vmadc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x44] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 44 vmadc.vim v8, v4, 15, v0 # CHECK-INST: vmadc.vim v8, v4, 15, v0 # CHECK-ENCODING: [0x57,0xb4,0x47,0x44] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 44 vmadc.vv v8, v4, v20 # CHECK-INST: vmadc.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x46] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 46 vmadc.vx v8, v4, a0 # CHECK-INST: vmadc.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x46] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 46 vmadc.vi v8, v4, 15 # CHECK-INST: vmadc.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x46] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 46 vsaddu.vv v8, v4, v20, v0.t # CHECK-INST: vsaddu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 80 vsaddu.vv v8, v4, v20 # CHECK-INST: vsaddu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x82] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 82 vsaddu.vx v8, v4, a0, v0.t # CHECK-INST: vsaddu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 80 vsaddu.vx v8, v4, a0 # CHECK-INST: vsaddu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x82] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 82 vsaddu.vi v8, v4, 15, v0.t # CHECK-INST: vsaddu.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 80 vsaddu.vi v8, v4, 15 # CHECK-INST: vsaddu.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x82] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 82 vsadd.vv v8, v4, v20, v0.t # CHECK-INST: vsadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x84] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 84 vsadd.vv v8, v4, v20 # CHECK-INST: vsadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x86] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 86 vsadd.vx v8, v4, a0, v0.t # CHECK-INST: vsadd.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x84] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 84 vsadd.vx v8, v4, a0 # CHECK-INST: vsadd.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x86] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 86 vsadd.vi v8, v4, 15, v0.t # CHECK-INST: vsadd.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x84] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 84 vsadd.vi v8, v4, 15 # CHECK-INST: vsadd.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x86] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 86 vaadd.vv v8, v4, v20, v0.t # CHECK-INST: vaadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x24] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 24 vaadd.vv v8, v4, v20 # CHECK-INST: vaadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x26] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 26 vaadd.vx v8, v4, a0, v0.t # CHECK-INST: vaadd.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x24] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 24 vaadd.vx v8, v4, a0 # CHECK-INST: vaadd.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x26] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 26 vaaddu.vv v8, v4, v20, v0.t # CHECK-INST: vaaddu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x20] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 20 vaaddu.vv v8, v4, v20 # CHECK-INST: vaaddu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 22 vaaddu.vx v8, v4, a0, v0.t # CHECK-INST: vaaddu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x20] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 20 vaaddu.vx v8, v4, a0 # CHECK-INST: vaaddu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 22 vwcvt.x.x.v v8, v4, v0.t # CHECK-INST: vwcvt.x.x.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x40,0xc4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 40 c4 vwcvt.x.x.v v8, v4 # CHECK-INST: vwcvt.x.x.v v8, v4 # CHECK-ENCODING: [0x57,0x64,0x40,0xc6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 40 c6 vwcvtu.x.x.v v8, v4, v0.t # CHECK-INST: vwcvtu.x.x.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x40,0xc0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 40 c0 vwcvtu.x.x.v v8, v4 # CHECK-INST: vwcvtu.x.x.v v8, v4 # CHECK-ENCODING: [0x57,0x64,0x40,0xc2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 40 c2 diff --git a/llvm/test/MC/RISCV/rvv/and.s b/llvm/test/MC/RISCV/rvv/and.s --- a/llvm/test/MC/RISCV/rvv/and.s +++ b/llvm/test/MC/RISCV/rvv/and.s @@ -11,35 +11,35 @@ vand.vv v8, v4, v20, v0.t # CHECK-INST: vand.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x24] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 24 vand.vv v8, v4, v20 # CHECK-INST: vand.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x26] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 26 vand.vx v8, v4, a0, v0.t # CHECK-INST: vand.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x24] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 24 vand.vx v8, v4, a0 # CHECK-INST: vand.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x26] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 26 vand.vi v8, v4, 15, v0.t # CHECK-INST: vand.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x24] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 24 vand.vi v8, v4, 15 # CHECK-INST: vand.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x26] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 26 diff --git a/llvm/test/MC/RISCV/rvv/clip.s b/llvm/test/MC/RISCV/rvv/clip.s --- a/llvm/test/MC/RISCV/rvv/clip.s +++ b/llvm/test/MC/RISCV/rvv/clip.s @@ -11,71 +11,71 @@ vnclipu.wv v8, v4, v20, v0.t # CHECK-INST: vnclipu.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xb8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a b8 vnclipu.wv v8, v4, v20 # CHECK-INST: vnclipu.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xba] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a ba vnclipu.wx v8, v4, a0, v0.t # CHECK-INST: vnclipu.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xb8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 b8 vnclipu.wx v8, v4, a0 # CHECK-INST: vnclipu.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xba] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 ba vnclipu.wi v8, v4, 31, v0.t # CHECK-INST: vnclipu.wi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f b8 vnclipu.wi v8, v4, 31 # CHECK-INST: vnclipu.wi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xba] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f ba vnclip.wv v8, v4, v20, v0.t # CHECK-INST: vnclip.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xbc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a bc vnclip.wv v8, v4, v20 # CHECK-INST: vnclip.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xbe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a be vnclip.wx v8, v4, a0, v0.t # CHECK-INST: vnclip.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xbc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 bc vnclip.wx v8, v4, a0 # CHECK-INST: vnclip.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xbe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 be vnclip.wi v8, v4, 31, v0.t # CHECK-INST: vnclip.wi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xbc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f bc vnclip.wi v8, v4, 31 # CHECK-INST: vnclip.wi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xbe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f be diff --git a/llvm/test/MC/RISCV/rvv/compare.s b/llvm/test/MC/RISCV/rvv/compare.s --- a/llvm/test/MC/RISCV/rvv/compare.s +++ b/llvm/test/MC/RISCV/rvv/compare.s @@ -11,367 +11,367 @@ vmslt.vv v0, v4, v20, v0.t # CHECK-INST: vmslt.vv v0, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x00,0x4a,0x6c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 00 4a 6c vmseq.vv v8, v4, v20, v0.t # CHECK-INST: vmseq.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x60] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 60 vmseq.vv v8, v4, v20 # CHECK-INST: vmseq.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 62 vmseq.vx v8, v4, a0, v0.t # CHECK-INST: vmseq.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x60] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 60 vmseq.vx v8, v4, a0 # CHECK-INST: vmseq.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 62 vmseq.vi v8, v4, 15, v0.t # CHECK-INST: vmseq.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x60] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 60 vmseq.vi v8, v4, 15 # CHECK-INST: vmseq.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 62 vmsne.vv v8, v4, v20, v0.t # CHECK-INST: vmsne.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x64] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 64 vmsne.vv v8, v4, v20 # CHECK-INST: vmsne.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x66] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 66 vmsne.vx v8, v4, a0, v0.t # CHECK-INST: vmsne.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x64] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 64 vmsne.vx v8, v4, a0 # CHECK-INST: vmsne.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x66] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 66 vmsne.vi v8, v4, 15, v0.t # CHECK-INST: vmsne.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x64] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 64 vmsne.vi v8, v4, 15 # CHECK-INST: vmsne.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x66] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 66 vmsltu.vv v8, v4, v20, v0.t # CHECK-INST: vmsltu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x68] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 68 vmsltu.vv v8, v4, v20 # CHECK-INST: vmsltu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x6a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 6a vmsltu.vx v8, v4, a0, v0.t # CHECK-INST: vmsltu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x68] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 68 vmsltu.vx v8, v4, a0 # CHECK-INST: vmsltu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x6a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 6a vmslt.vv v8, v4, v20, v0.t # CHECK-INST: vmslt.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x6c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 6c vmslt.vv v8, v4, v20 # CHECK-INST: vmslt.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 6e vmslt.vx v8, v4, a0, v0.t # CHECK-INST: vmslt.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x6c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 6c vmslt.vx v8, v4, a0 # CHECK-INST: vmslt.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 6e vmsleu.vv v8, v4, v20, v0.t # CHECK-INST: vmsleu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x70] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 70 vmsleu.vv v8, v4, v20 # CHECK-INST: vmsleu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x72] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 72 vmsleu.vx v8, v4, a0, v0.t # CHECK-INST: vmsleu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x70] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 70 vmsleu.vx v8, v4, a0 # CHECK-INST: vmsleu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x72] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 72 vmsleu.vi v8, v4, 15, v0.t # CHECK-INST: vmsleu.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x70] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 70 vmsleu.vi v8, v4, 15 # CHECK-INST: vmsleu.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x72] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 72 vmsle.vv v8, v4, v20, v0.t # CHECK-INST: vmsle.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x74] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 74 vmsle.vv v8, v4, v20 # CHECK-INST: vmsle.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 76 vmsle.vx v8, v4, a0, v0.t # CHECK-INST: vmsle.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x74] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 74 vmsle.vx v8, v4, a0 # CHECK-INST: vmsle.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 76 vmsle.vi v8, v4, 15, v0.t # CHECK-INST: vmsle.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x74] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 74 vmsle.vi v8, v4, 15 # CHECK-INST: vmsle.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 76 vmsgtu.vx v8, v4, a0, v0.t # CHECK-INST: vmsgtu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x78] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 78 vmsgtu.vx v8, v4, a0 # CHECK-INST: vmsgtu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x7a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 7a vmsgtu.vi v8, v4, 15, v0.t # CHECK-INST: vmsgtu.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x78] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 78 vmsgtu.vi v8, v4, 15 # CHECK-INST: vmsgtu.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x7a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 7a vmsgt.vx v8, v4, a0, v0.t # CHECK-INST: vmsgt.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x7c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 7c vmsgt.vx v8, v4, a0 # CHECK-INST: vmsgt.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x7e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 7e vmsgt.vi v8, v4, 15, v0.t # CHECK-INST: vmsgt.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x7c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 7c vmsgt.vi v8, v4, 15 # CHECK-INST: vmsgt.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x7e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 7e vmsgtu.vv v8, v20, v4, v0.t # CHECK-INST: vmsltu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x68] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 68 vmsgtu.vv v8, v20, v4 # CHECK-INST: vmsltu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x6a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 6a vmsgt.vv v8, v20, v4, v0.t # CHECK-INST: vmslt.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x6c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 6c vmsgt.vv v8, v20, v4 # CHECK-INST: vmslt.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 6e vmsgeu.vv v8, v20, v4, v0.t # CHECK-INST: vmsleu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x70] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 70 vmsgeu.vv v8, v20, v4 # CHECK-INST: vmsleu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x72] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 72 vmsge.vv v8, v20, v4, v0.t # CHECK-INST: vmsle.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x74] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 74 vmsge.vv v8, v20, v4 # CHECK-INST: vmsle.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 76 vmsltu.vi v8, v4, 16, v0.t # CHECK-INST: vmsleu.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x70] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 70 vmsltu.vi v8, v4, 16 # CHECK-INST: vmsleu.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x72] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 72 vmsltu.vi v8, v4, 0, v0.t # CHECK-INST: vmsne.vv v8, v4, v4, v0.t # CHECK-ENCODING: [0x57,0x04,0x42,0x64] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 42 64 vmsltu.vi v8, v4, 0 # CHECK-INST: vmsne.vv v8, v4, v4 # CHECK-ENCODING: [0x57,0x04,0x42,0x66] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 42 66 vmslt.vi v8, v4, 16, v0.t # CHECK-INST: vmsle.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x74] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 74 vmslt.vi v8, v4, 16 # CHECK-INST: vmsle.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 76 vmsgeu.vi v8, v4, 16, v0.t # CHECK-INST: vmsgtu.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x78] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 78 vmsgeu.vi v8, v4, 16 # CHECK-INST: vmsgtu.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x7a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 7a vmsgeu.vi v8, v4, 0, v0.t # CHECK-INST: vmseq.vv v8, v4, v4, v0.t # CHECK-ENCODING: [0x57,0x04,0x42,0x60] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 42 60 vmsgeu.vi v8, v4, 0 # CHECK-INST: vmseq.vv v8, v4, v4 # CHECK-ENCODING: [0x57,0x04,0x42,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 42 62 vmsge.vi v8, v4, 16, v0.t # CHECK-INST: vmsgt.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x7c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 7c vmsge.vi v8, v4, 16 # CHECK-INST: vmsgt.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x7e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 7e vmsgeu.vx v8, v4, a0 @@ -379,7 +379,7 @@ # CHECK-INST: vmnot.m v8, v8 # CHECK-ENCODING: [0x57,0x44,0x45,0x6a] # CHECK-ENCODING: [0x57,0x24,0x84,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 6a # CHECK-UNKNOWN: 57 24 84 76 @@ -388,7 +388,7 @@ # CHECK-INST: vmnot.m v0, v0 # CHECK-ENCODING: [0x57,0x40,0x45,0x6e] # CHECK-ENCODING: [0x57,0x20,0x00,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 40 45 6e # CHECK-UNKNOWN: 57 20 00 76 @@ -397,7 +397,7 @@ # CHECK-INST: vmnot.m v8, v8 # CHECK-ENCODING: [0x57,0x44,0x45,0x6e] # CHECK-ENCODING: [0x57,0x24,0x84,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 6e # CHECK-UNKNOWN: 57 24 84 76 @@ -406,7 +406,7 @@ # CHECK-INST: vmxor.mm v8, v8, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x68] # CHECK-ENCODING: [0x57,0x24,0x80,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 68 # CHECK-UNKNOWN: 57 24 80 6e @@ -415,7 +415,7 @@ # CHECK-INST: vmxor.mm v8, v8, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x6c] # CHECK-ENCODING: [0x57,0x24,0x80,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 6c # CHECK-UNKNOWN: 57 24 80 6e @@ -424,7 +424,7 @@ # CHECK-INST: vmandn.mm v0, v0, v2 # CHECK-ENCODING: [0x57,0x41,0x45,0x68] # CHECK-ENCODING: [0x57,0x20,0x01,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 41 45 68 # CHECK-UNKNOWN: 57 20 01 62 @@ -433,7 +433,7 @@ # CHECK-INST: vmandn.mm v0, v0, v2 # CHECK-ENCODING: [0x57,0x41,0x45,0x6c] # CHECK-ENCODING: [0x57,0x20,0x01,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 41 45 6c # CHECK-UNKNOWN: 57 20 01 62 @@ -446,7 +446,7 @@ # CHECK-ENCODING: [0x57,0x21,0x01,0x62] # CHECK-ENCODING: [0xd7,0x24,0x90,0x62] # CHECK-ENCODING: [0xd7,0xa4,0x24,0x6a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 41 45 6a # CHECK-UNKNOWN: 57 21 01 62 # CHECK-UNKNOWN: d7 24 90 62 @@ -461,7 +461,7 @@ # CHECK-ENCODING: [0x57,0x21,0x01,0x62] # CHECK-ENCODING: [0x57,0x24,0x80,0x62] # CHECK-ENCODING: [0x57,0x24,0x24,0x6a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 41 45 6e # CHECK-UNKNOWN: 57 21 01 62 # CHECK-UNKNOWN: 57 24 80 62 diff --git a/llvm/test/MC/RISCV/rvv/div.s b/llvm/test/MC/RISCV/rvv/div.s --- a/llvm/test/MC/RISCV/rvv/div.s +++ b/llvm/test/MC/RISCV/rvv/div.s @@ -11,95 +11,95 @@ vdivu.vv v8, v4, v20, v0.t # CHECK-INST: vdivu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 80 vdivu.vv v8, v4, v20 # CHECK-INST: vdivu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x82] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 82 vdivu.vx v8, v4, a0, v0.t # CHECK-INST: vdivu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 80 vdivu.vx v8, v4, a0 # CHECK-INST: vdivu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x82] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 82 vdiv.vv v8, v4, v20, v0.t # CHECK-INST: vdiv.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x84] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 84 vdiv.vv v8, v4, v20 # CHECK-INST: vdiv.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x86] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 86 vdiv.vx v8, v4, a0, v0.t # CHECK-INST: vdiv.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x84] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 84 vdiv.vx v8, v4, a0 # CHECK-INST: vdiv.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x86] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 86 vremu.vv v8, v4, v20, v0.t # CHECK-INST: vremu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x88] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 88 vremu.vv v8, v4, v20 # CHECK-INST: vremu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x8a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 8a vremu.vx v8, v4, a0, v0.t # CHECK-INST: vremu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x88] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 88 vremu.vx v8, v4, a0 # CHECK-INST: vremu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x8a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 8a vrem.vv v8, v4, v20, v0.t # CHECK-INST: vrem.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x8c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 8c vrem.vv v8, v4, v20 # CHECK-INST: vrem.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x8e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 8e vrem.vx v8, v4, a0, v0.t # CHECK-INST: vrem.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x8c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 8c vrem.vx v8, v4, a0 # CHECK-INST: vrem.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x8e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 8e diff --git a/llvm/test/MC/RISCV/rvv/ext.s b/llvm/test/MC/RISCV/rvv/ext.s --- a/llvm/test/MC/RISCV/rvv/ext.s +++ b/llvm/test/MC/RISCV/rvv/ext.s @@ -11,71 +11,71 @@ vzext.vf2 v8, v4, v0.t # CHECK-INST: vzext.vf2 v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x43,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 43 48 vzext.vf2 v8, v4 # CHECK-INST: vzext.vf2 v8, v4 # CHECK-ENCODING: [0x57,0x24,0x43,0x4a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 43 4a vsext.vf2 v8, v4, v0.t # CHECK-INST: vsext.vf2 v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x43,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 a4 43 48 vsext.vf2 v8, v4 # CHECK-INST: vsext.vf2 v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x43,0x4a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 a4 43 4a vzext.vf4 v8, v4, v0.t # CHECK-INST: vzext.vf4 v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x42,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 42 48 vzext.vf4 v8, v4 # CHECK-INST: vzext.vf4 v8, v4 # CHECK-ENCODING: [0x57,0x24,0x42,0x4a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 42 4a vsext.vf4 v8, v4, v0.t # CHECK-INST: vsext.vf4 v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x42,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 a4 42 48 vsext.vf4 v8, v4 # CHECK-INST: vsext.vf4 v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x42,0x4a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 a4 42 4a vzext.vf8 v8, v4, v0.t # CHECK-INST: vzext.vf8 v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x41,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 41 48 vzext.vf8 v8, v4 # CHECK-INST: vzext.vf8 v8, v4 # CHECK-ENCODING: [0x57,0x24,0x41,0x4a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 41 4a vsext.vf8 v8, v4, v0.t # CHECK-INST: vsext.vf8 v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x41,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 a4 41 48 vsext.vf8 v8, v4 # CHECK-INST: vsext.vf8 v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x41,0x4a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 a4 41 4a diff --git a/llvm/test/MC/RISCV/rvv/invalid-eew.s b/llvm/test/MC/RISCV/rvv/invalid-eew.s --- a/llvm/test/MC/RISCV/rvv/invalid-eew.s +++ b/llvm/test/MC/RISCV/rvv/invalid-eew.s @@ -2,193 +2,193 @@ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR vluxei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vluxei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vloxei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vloxei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsuxei64.v v24, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsuxei64.v v24, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsoxei64.v v24, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsoxei64.v v24, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vluxseg2ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vluxseg2ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vluxseg3ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vluxseg3ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vluxseg4ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vluxseg4ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vluxseg5ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vluxseg5ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vluxseg6ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vluxseg6ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vluxseg7ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vluxseg7ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vluxseg8ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vluxseg8ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vloxseg2ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vloxseg2ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vloxseg3ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vloxseg3ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vloxseg4ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vloxseg4ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vloxseg5ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vloxseg5ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vloxseg6ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vloxseg6ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vloxseg7ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vloxseg7ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vloxseg8ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vloxseg8ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsuxseg2ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsuxseg2ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsuxseg3ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsuxseg3ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsuxseg4ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsuxseg4ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsuxseg5ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsuxseg5ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsuxseg6ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsuxseg6ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsuxseg7ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsuxseg7ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsuxseg8ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsuxseg8ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsoxseg2ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsoxseg2ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsoxseg3ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsoxseg3ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsoxseg4ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsoxseg4ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsoxseg5ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsoxseg5ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsoxseg6ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsoxseg6ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsoxseg7ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsoxseg7ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsoxseg8ei64.v v8, (a0), v4, v0.t -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} vsoxseg8ei64.v v8, (a0), v4 -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors), RV64I Base Instruction Set{{$}} diff --git a/llvm/test/MC/RISCV/rvv/load.s b/llvm/test/MC/RISCV/rvv/load.s --- a/llvm/test/MC/RISCV/rvv/load.s +++ b/llvm/test/MC/RISCV/rvv/load.s @@ -11,347 +11,347 @@ vlm.v v0, (a0) # CHECK-INST: vlm.v v0, (a0) # CHECK-ENCODING: [0x07,0x00,0xb5,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 00 b5 02 vlm.v v8, (a0) # CHECK-INST: vlm.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0xb5,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 04 b5 02 vle8.v v8, (a0), v0.t # CHECK-INST: vle8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 04 05 00 vle8.v v8, (a0) # CHECK-INST: vle8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 04 05 02 vle16.v v8, (a0), v0.t # CHECK-INST: vle16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 54 05 00 vle16.v v8, (a0) # CHECK-INST: vle16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 54 05 02 vle32.v v8, (a0), v0.t # CHECK-INST: vle32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 64 05 00 vle32.v v8, (a0) # CHECK-INST: vle32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 64 05 02 vle64.v v8, (a0), v0.t # CHECK-INST: vle64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 74 05 00 vle64.v v8, (a0) # CHECK-INST: vle64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 74 05 02 vle8ff.v v8, (a0), v0.t # CHECK-INST: vle8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x01] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 04 05 01 vle8ff.v v8, (a0) # CHECK-INST: vle8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x03] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 04 05 03 vle16ff.v v8, (a0), v0.t # CHECK-INST: vle16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x01] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 54 05 01 vle16ff.v v8, (a0) # CHECK-INST: vle16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x03] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 54 05 03 vle32ff.v v8, (a0), v0.t # CHECK-INST: vle32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x01] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 64 05 01 vle32ff.v v8, (a0) # CHECK-INST: vle32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x03] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 64 05 03 vle64ff.v v8, (a0), v0.t # CHECK-INST: vle64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x01] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 74 05 01 vle64ff.v v8, (a0) # CHECK-INST: vle64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x03] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 74 05 03 vlse8.v v8, (a0), a1, v0.t # CHECK-INST: vlse8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 04 b5 08 vlse8.v v8, (a0), a1 # CHECK-INST: vlse8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 04 b5 0a vlse16.v v8, (a0), a1, v0.t # CHECK-INST: vlse16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 54 b5 08 vlse16.v v8, (a0), a1 # CHECK-INST: vlse16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 54 b5 0a vlse32.v v8, (a0), a1, v0.t # CHECK-INST: vlse32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 64 b5 08 vlse32.v v8, (a0), a1 # CHECK-INST: vlse32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 64 b5 0a vlse64.v v8, (a0), a1, v0.t # CHECK-INST: vlse64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 74 b5 08 vlse64.v v8, (a0), a1 # CHECK-INST: vlse64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 74 b5 0a vluxei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 04 45 04 vluxei8.v v8, (a0), v4 # CHECK-INST: vluxei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 04 45 06 vluxei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 54 45 04 vluxei16.v v8, (a0), v4 # CHECK-INST: vluxei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 54 45 06 vluxei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 64 45 04 vluxei32.v v8, (a0), v4 # CHECK-INST: vluxei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 64 45 06 vluxei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 74 45 04 vluxei64.v v8, (a0), v4 # CHECK-INST: vluxei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 74 45 06 vloxei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 04 45 0c vloxei8.v v8, (a0), v4 # CHECK-INST: vloxei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 04 45 0e vloxei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 54 45 0c vloxei16.v v8, (a0), v4 # CHECK-INST: vloxei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 54 45 0e vloxei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 64 45 0c vloxei32.v v8, (a0), v4 # CHECK-INST: vloxei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 64 45 0e vloxei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 74 45 0c vloxei64.v v8, (a0), v4 # CHECK-INST: vloxei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 74 45 0e vl1re8.v v8, (a0) # CHECK-INST: vl1re8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x85,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 04 85 02 vl1re16.v v8, (a0) # CHECK-INST: vl1re16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x85,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 54 85 02 vl1re32.v v8, (a0) # CHECK-INST: vl1re32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x85,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 64 85 02 vl1re64.v v8, (a0) # CHECK-INST: vl1re64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x85,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 74 85 02 vl2re8.v v8, (a0) # CHECK-INST: vl2re8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x85,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 04 85 22 vl2re16.v v8, (a0) # CHECK-INST: vl2re16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x85,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 54 85 22 vl2re32.v v8, (a0) # CHECK-INST: vl2re32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x85,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 64 85 22 vl2re64.v v8, (a0) # CHECK-INST: vl2re64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x85,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 74 85 22 vl4re8.v v8, (a0) # CHECK-INST: vl4re8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x85,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 04 85 62 vl4re16.v v8, (a0) # CHECK-INST: vl4re16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x85,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 54 85 62 vl4re32.v v8, (a0) # CHECK-INST: vl4re32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x85,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 64 85 62 vl4re64.v v8, (a0) # CHECK-INST: vl4re64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x85,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 74 85 62 vl8re8.v v8, (a0) # CHECK-INST: vl8re8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x85,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 04 85 e2 vl8re16.v v8, (a0) # CHECK-INST: vl8re16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x85,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 54 85 e2 vl8re32.v v8, (a0) # CHECK-INST: vl8re32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x85,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 64 85 e2 vl8re64.v v8, (a0) # CHECK-INST: vl8re64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x85,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 07 74 85 e2 diff --git a/llvm/test/MC/RISCV/rvv/macc.s b/llvm/test/MC/RISCV/rvv/macc.s --- a/llvm/test/MC/RISCV/rvv/macc.s +++ b/llvm/test/MC/RISCV/rvv/macc.s @@ -11,179 +11,179 @@ vmacc.vv v8, v20, v4, v0.t # CHECK-INST: vmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xb4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a b4 vmacc.vv v8, v20, v4 # CHECK-INST: vmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xb6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a b6 vmacc.vx v8, a0, v4, v0.t # CHECK-INST: vmacc.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xb4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 b4 vmacc.vx v8, a0, v4 # CHECK-INST: vmacc.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xb6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 b6 vnmsac.vv v8, v20, v4, v0.t # CHECK-INST: vnmsac.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xbc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a bc vnmsac.vv v8, v20, v4 # CHECK-INST: vnmsac.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xbe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a be vnmsac.vx v8, a0, v4, v0.t # CHECK-INST: vnmsac.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xbc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 bc vnmsac.vx v8, a0, v4 # CHECK-INST: vnmsac.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xbe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 be vmadd.vv v8, v20, v4, v0.t # CHECK-INST: vmadd.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xa4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a a4 vmadd.vv v8, v20, v4 # CHECK-INST: vmadd.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xa6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a a6 vmadd.vx v8, a0, v4, v0.t # CHECK-INST: vmadd.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xa4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 a4 vmadd.vx v8, a0, v4 # CHECK-INST: vmadd.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xa6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 a6 vnmsub.vv v8, v20, v4, v0.t # CHECK-INST: vnmsub.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xac] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a ac vnmsub.vv v8, v20, v4 # CHECK-INST: vnmsub.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xae] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a ae vnmsub.vx v8, a0, v4, v0.t # CHECK-INST: vnmsub.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xac] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 ac vnmsub.vx v8, a0, v4 # CHECK-INST: vnmsub.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xae] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 ae vwmaccu.vv v8, v20, v4, v0.t # CHECK-INST: vwmaccu.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xf0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a f0 vwmaccu.vv v8, v20, v4 # CHECK-INST: vwmaccu.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xf2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a f2 vwmaccu.vx v8, a0, v4, v0.t # CHECK-INST: vwmaccu.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xf0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 f0 vwmaccu.vx v8, a0, v4 # CHECK-INST: vwmaccu.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xf2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 f2 vwmacc.vv v8, v20, v4, v0.t # CHECK-INST: vwmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xf4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a f4 vwmacc.vv v8, v20, v4 # CHECK-INST: vwmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xf6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a f6 vwmacc.vx v8, a0, v4, v0.t # CHECK-INST: vwmacc.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xf4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 f4 vwmacc.vx v8, a0, v4 # CHECK-INST: vwmacc.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xf6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 f6 vwmaccsu.vv v8, v20, v4, v0.t # CHECK-INST: vwmaccsu.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xfc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a fc vwmaccsu.vv v8, v20, v4 # CHECK-INST: vwmaccsu.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xfe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a fe vwmaccsu.vx v8, a0, v4, v0.t # CHECK-INST: vwmaccsu.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xfc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 fc vwmaccsu.vx v8, a0, v4 # CHECK-INST: vwmaccsu.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xfe] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 fe vwmaccus.vx v8, a0, v4, v0.t # CHECK-INST: vwmaccus.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xf8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 f8 vwmaccus.vx v8, a0, v4 # CHECK-INST: vwmaccus.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xfa] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 fa diff --git a/llvm/test/MC/RISCV/rvv/mask.s b/llvm/test/MC/RISCV/rvv/mask.s --- a/llvm/test/MC/RISCV/rvv/mask.s +++ b/llvm/test/MC/RISCV/rvv/mask.s @@ -11,155 +11,155 @@ vmand.mm v8, v4, v20 # CHECK-INST: vmand.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x66] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 66 vmnand.mm v8, v4, v20 # CHECK-INST: vmnand.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 76 vmandn.mm v8, v4, v20 # CHECK-INST: vmandn.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 62 vmxor.mm v8, v4, v20 # CHECK-INST: vmxor.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 6e vmor.mm v8, v4, v20 # CHECK-INST: vmor.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x6a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 6a vmnor.mm v8, v4, v20 # CHECK-INST: vmnor.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x7a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 7a vmorn.mm v8, v4, v20 # CHECK-INST: vmorn.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x72] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 72 vmxnor.mm v8, v4, v20 # CHECK-INST: vmxnor.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x7e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 7e vcpop.m a2, v4, v0.t # CHECK-INST: vcpop.m a2, v4, v0.t # CHECK-ENCODING: [0x57,0x26,0x48,0x40] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 26 48 40 vcpop.m a2, v4 # CHECK-INST: vcpop.m a2, v4 # CHECK-ENCODING: [0x57,0x26,0x48,0x42] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 26 48 42 vfirst.m a2, v4, v0.t # CHECK-INST: vfirst.m a2, v4, v0.t # CHECK-ENCODING: [0x57,0xa6,0x48,0x40] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 a6 48 40 vfirst.m a2, v4 # CHECK-INST: vfirst.m a2, v4 # CHECK-ENCODING: [0x57,0xa6,0x48,0x42] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 a6 48 42 vmsbf.m v8, v4, v0.t # CHECK-INST: vmsbf.m v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x40,0x50] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 a4 40 50 vmsbf.m v8, v4 # CHECK-INST: vmsbf.m v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x40,0x52] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 a4 40 52 vmsif.m v8, v4, v0.t # CHECK-INST: vmsif.m v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x41,0x50] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 a4 41 50 vmsif.m v8, v4 # CHECK-INST: vmsif.m v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x41,0x52] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 a4 41 52 vmsof.m v8, v4, v0.t # CHECK-INST: vmsof.m v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x41,0x50] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 41 50 vmsof.m v8, v4 # CHECK-INST: vmsof.m v8, v4 # CHECK-ENCODING: [0x57,0x24,0x41,0x52] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 41 52 viota.m v8, v4, v0.t # CHECK-INST: viota.m v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x48,0x50] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 48 50 viota.m v8, v4 # CHECK-INST: viota.m v8, v4 # CHECK-ENCODING: [0x57,0x24,0x48,0x52] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 48 52 vid.v v8, v0.t # CHECK-INST: vid.v v8, v0.t # CHECK-ENCODING: [0x57,0xa4,0x08,0x50] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 a4 08 50 vid.v v8 # CHECK-INST: vid.v v8 # CHECK-ENCODING: [0x57,0xa4,0x08,0x52] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 a4 08 52 vmmv.m v8, v4 # CHECK-INST: vmmv.m v8, v4 # CHECK-ENCODING: [0x57,0x24,0x42,0x66] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 42 66 vmclr.m v8 # CHECK-INST: vmclr.m v8 # CHECK-ENCODING: [0x57,0x24,0x84,0x6e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 84 6e vmset.m v8 # CHECK-INST: vmset.m v8 # CHECK-ENCODING: [0x57,0x24,0x84,0x7e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 84 7e vmnot.m v8, v4 # CHECK-INST: vmnot.m v8, v4 # CHECK-ENCODING: [0x57,0x24,0x42,0x76] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 42 76 diff --git a/llvm/test/MC/RISCV/rvv/minmax.s b/llvm/test/MC/RISCV/rvv/minmax.s --- a/llvm/test/MC/RISCV/rvv/minmax.s +++ b/llvm/test/MC/RISCV/rvv/minmax.s @@ -11,95 +11,95 @@ vminu.vv v8, v4, v20, v0.t # CHECK-INST: vminu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x10] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 10 vminu.vv v8, v4, v20 # CHECK-INST: vminu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x12] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 12 vminu.vx v8, v4, a0, v0.t # CHECK-INST: vminu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x10] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 10 vminu.vx v8, v4, a0 # CHECK-INST: vminu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x12] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 12 vmin.vv v8, v4, v20, v0.t # CHECK-INST: vmin.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x14] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 14 vmin.vv v8, v4, v20 # CHECK-INST: vmin.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x16] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 16 vmin.vx v8, v4, a0, v0.t # CHECK-INST: vmin.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x14] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 14 vmin.vx v8, v4, a0 # CHECK-INST: vmin.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x16] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 16 vmaxu.vv v8, v4, v20, v0.t # CHECK-INST: vmaxu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x18] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 18 vmaxu.vv v8, v4, v20 # CHECK-INST: vmaxu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x1a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 1a vmaxu.vx v8, v4, a0, v0.t # CHECK-INST: vmaxu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x18] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 18 vmaxu.vx v8, v4, a0 # CHECK-INST: vmaxu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x1a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 1a vmax.vv v8, v4, v20, v0.t # CHECK-INST: vmax.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x1c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 1c vmax.vv v8, v4, v20 # CHECK-INST: vmax.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x1e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 1e vmax.vx v8, v4, a0, v0.t # CHECK-INST: vmax.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x1c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 1c vmax.vx v8, v4, a0 # CHECK-INST: vmax.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x1e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 1e diff --git a/llvm/test/MC/RISCV/rvv/mul.s b/llvm/test/MC/RISCV/rvv/mul.s --- a/llvm/test/MC/RISCV/rvv/mul.s +++ b/llvm/test/MC/RISCV/rvv/mul.s @@ -11,191 +11,191 @@ vmul.vv v8, v4, v20, v0.t # CHECK-INST: vmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x94] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 94 vmul.vv v8, v4, v20 # CHECK-INST: vmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x96] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 96 vmul.vx v8, v4, a0, v0.t # CHECK-INST: vmul.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x94] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 94 vmul.vx v8, v4, a0 # CHECK-INST: vmul.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x96] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 96 vmulh.vv v8, v4, v20, v0.t # CHECK-INST: vmulh.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x9c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 9c vmulh.vv v8, v4, v20 # CHECK-INST: vmulh.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 9e vmulh.vx v8, v4, a0, v0.t # CHECK-INST: vmulh.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x9c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 9c vmulh.vx v8, v4, a0 # CHECK-INST: vmulh.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 9e vmulhu.vv v8, v4, v20, v0.t # CHECK-INST: vmulhu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x90] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 90 vmulhu.vv v8, v4, v20 # CHECK-INST: vmulhu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x92] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 92 vmulhu.vx v8, v4, a0, v0.t # CHECK-INST: vmulhu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x90] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 90 vmulhu.vx v8, v4, a0 # CHECK-INST: vmulhu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x92] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 92 vmulhsu.vv v8, v4, v20, v0.t # CHECK-INST: vmulhsu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x98] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 98 vmulhsu.vv v8, v4, v20 # CHECK-INST: vmulhsu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x9a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 9a vmulhsu.vx v8, v4, a0, v0.t # CHECK-INST: vmulhsu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x98] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 98 vmulhsu.vx v8, v4, a0 # CHECK-INST: vmulhsu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x9a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 9a vwmul.vv v8, v4, v20, v0.t # CHECK-INST: vwmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xec] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a ec vwmul.vv v8, v4, v20 # CHECK-INST: vwmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xee] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a ee vwmul.vx v8, v4, a0, v0.t # CHECK-INST: vwmul.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xec] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 ec vwmul.vx v8, v4, a0 # CHECK-INST: vwmul.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xee] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 ee vwmulu.vv v8, v4, v20, v0.t # CHECK-INST: vwmulu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xe0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a e0 vwmulu.vv v8, v4, v20 # CHECK-INST: vwmulu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a e2 vwmulu.vx v8, v4, a0, v0.t # CHECK-INST: vwmulu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xe0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 e0 vwmulu.vx v8, v4, a0 # CHECK-INST: vwmulu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 e2 vwmulsu.vv v8, v4, v20, v0.t # CHECK-INST: vwmulsu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xe8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a e8 vwmulsu.vv v8, v4, v20 # CHECK-INST: vwmulsu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xea] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a ea vwmulsu.vx v8, v4, a0, v0.t # CHECK-INST: vwmulsu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xe8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 e8 vwmulsu.vx v8, v4, a0 # CHECK-INST: vwmulsu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xea] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 ea vsmul.vv v8, v4, v20, v0.t # CHECK-INST: vsmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x9c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 9c vsmul.vv v8, v4, v20 # CHECK-INST: vsmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 9e vsmul.vx v8, v4, a0, v0.t # CHECK-INST: vsmul.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x9c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 9c vsmul.vx v8, v4, a0 # CHECK-INST: vsmul.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 9e diff --git a/llvm/test/MC/RISCV/rvv/mv.s b/llvm/test/MC/RISCV/rvv/mv.s --- a/llvm/test/MC/RISCV/rvv/mv.s +++ b/llvm/test/MC/RISCV/rvv/mv.s @@ -11,53 +11,53 @@ vmv.v.v v8, v20 # CHECK-INST: vmv.v.v v8, v20 # CHECK-ENCODING: [0x57,0x04,0x0a,0x5e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 0a 5e vmv.v.x v8, a0 # CHECK-INST: vmv.v.x v8, a0 # CHECK-ENCODING: [0x57,0x44,0x05,0x5e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 05 5e vmv.v.i v8, 15 # CHECK-INST: vmv.v.i v8, 15 # CHECK-ENCODING: [0x57,0xb4,0x07,0x5e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 07 5e vmv.x.s a2, v4 # CHECK-INST: vmv.x.s a2, v4 # CHECK-ENCODING: [0x57,0x26,0x40,0x42] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 26 40 42 vmv.s.x v8, a0 # CHECK-INST: vmv.s.x v8, a0 # CHECK-ENCODING: [0x57,0x64,0x05,0x42] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 05 42 vmv1r.v v8, v4 # CHECK-INST: vmv1r.v v8, v4 # CHECK-ENCODING: [0x57,0x34,0x40,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 34 40 9e vmv2r.v v8, v4 # CHECK-INST: vmv2r.v v8, v4 # CHECK-ENCODING: [0x57,0xb4,0x40,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 40 9e vmv4r.v v8, v4 # CHECK-INST: vmv4r.v v8, v4 # CHECK-ENCODING: [0x57,0xb4,0x41,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 41 9e vmv8r.v v8, v24 # CHECK-INST: vmv8r.v v8, v24 # CHECK-ENCODING: [0x57,0xb4,0x83,0x9f] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 83 9f diff --git a/llvm/test/MC/RISCV/rvv/or.s b/llvm/test/MC/RISCV/rvv/or.s --- a/llvm/test/MC/RISCV/rvv/or.s +++ b/llvm/test/MC/RISCV/rvv/or.s @@ -11,35 +11,35 @@ vor.vv v8, v4, v20, v0.t # CHECK-INST: vor.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x28] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 28 vor.vv v8, v4, v20 # CHECK-INST: vor.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x2a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 2a vor.vx v8, v4, a0, v0.t # CHECK-INST: vor.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x28] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 28 vor.vx v8, v4, a0 # CHECK-INST: vor.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x2a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 2a vor.vi v8, v4, 15, v0.t # CHECK-INST: vor.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x28] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 28 vor.vi v8, v4, 15 # CHECK-INST: vor.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x2a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 2a diff --git a/llvm/test/MC/RISCV/rvv/others.s b/llvm/test/MC/RISCV/rvv/others.s --- a/llvm/test/MC/RISCV/rvv/others.s +++ b/llvm/test/MC/RISCV/rvv/others.s @@ -11,143 +11,143 @@ vmerge.vvm v8, v4, v20, v0 # CHECK-INST: vmerge.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x5c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 5c vmerge.vxm v8, v4, a0, v0 # CHECK-INST: vmerge.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x5c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 5c vmerge.vim v8, v4, 15, v0 # CHECK-INST: vmerge.vim v8, v4, 15, v0 # CHECK-ENCODING: [0x57,0xb4,0x47,0x5c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 5c vslideup.vx v8, v4, a0, v0.t # CHECK-INST: vslideup.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x38] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 38 vslideup.vx v8, v4, a0 # CHECK-INST: vslideup.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x3a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 3a vslideup.vi v8, v4, 31, v0.t # CHECK-INST: vslideup.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x38] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f 38 vslideup.vi v8, v4, 31 # CHECK-INST: vslideup.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x3a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f 3a vslidedown.vx v8, v4, a0, v0.t # CHECK-INST: vslidedown.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x3c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 3c vslidedown.vx v8, v4, a0 # CHECK-INST: vslidedown.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x3e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 3e vslidedown.vi v8, v4, 31, v0.t # CHECK-INST: vslidedown.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x3c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f 3c vslidedown.vi v8, v4, 31 # CHECK-INST: vslidedown.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x3e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f 3e vslide1up.vx v8, v4, a0, v0.t # CHECK-INST: vslide1up.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x38] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 38 vslide1up.vx v8, v4, a0 # CHECK-INST: vslide1up.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x3a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 3a vslide1down.vx v8, v4, a0, v0.t # CHECK-INST: vslide1down.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x3c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 3c vslide1down.vx v8, v4, a0 # CHECK-INST: vslide1down.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x3e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 3e vrgather.vv v8, v4, v20, v0.t # CHECK-INST: vrgather.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x30] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 30 vrgather.vv v8, v4, v20 # CHECK-INST: vrgather.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x32] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 32 vrgather.vx v8, v4, a0, v0.t # CHECK-INST: vrgather.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x30] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 30 vrgather.vx v8, v4, a0 # CHECK-INST: vrgather.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x32] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 32 vrgather.vi v8, v4, 31, v0.t # CHECK-INST: vrgather.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x30] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f 30 vrgather.vi v8, v4, 31 # CHECK-INST: vrgather.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x32] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f 32 vrgatherei16.vv v8, v4, v20, v0.t # CHECK-INST: vrgatherei16.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x38] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 38 vrgatherei16.vv v8, v4, v20 # CHECK-INST: vrgatherei16.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x3a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 3a vcompress.vm v8, v4, v20 # CHECK-INST: vcompress.vm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x5e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 5e diff --git a/llvm/test/MC/RISCV/rvv/reduction.s b/llvm/test/MC/RISCV/rvv/reduction.s --- a/llvm/test/MC/RISCV/rvv/reduction.s +++ b/llvm/test/MC/RISCV/rvv/reduction.s @@ -11,125 +11,125 @@ vredsum.vs v8, v4, v20, v0.t # CHECK-INST: vredsum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 00 vredsum.vs v8, v4, v20 # CHECK-INST: vredsum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 02 vredmaxu.vs v8, v4, v20, v0.t # CHECK-INST: vredmaxu.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x18] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 18 vredmaxu.vs v8, v4, v20 # CHECK-INST: vredmaxu.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x1a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 1a vredmax.vs v8, v4, v20, v0.t # CHECK-INST: vredmax.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x1c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 1c vredmax.vs v8, v4, v20 # CHECK-INST: vredmax.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x1e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 1e vredminu.vs v8, v4, v20, v0.t # CHECK-INST: vredminu.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x10] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 10 vredminu.vs v8, v4, v20 # CHECK-INST: vredminu.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x12] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 12 vredmin.vs v8, v4, v20, v0.t # CHECK-INST: vredmin.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x14] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 14 vredmin.vs v8, v4, v20 # CHECK-INST: vredmin.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x16] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 16 vredand.vs v8, v4, v20, v0.t # CHECK-INST: vredand.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 04 vredand.vs v8, v4, v20 # CHECK-INST: vredand.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 06 vredor.vs v8, v4, v20, v0.t # CHECK-INST: vredor.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 08 vredor.vs v8, v4, v20 # CHECK-INST: vredor.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 0a vredxor.vs v8, v4, v20, v0.t # CHECK-INST: vredxor.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 0c vredxor.vs v8, v4, v20 # CHECK-INST: vredxor.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 0e vwredsumu.vs v8, v4, v20, v0.t # CHECK-INST: vwredsumu.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xc0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a c0 vwredsumu.vs v8, v4, v20 # CHECK-INST: vwredsumu.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xc2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a c2 vwredsum.vs v8, v4, v20, v0.t # CHECK-INST: vwredsum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xc4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a c4 vwredsum.vs v8, v4, v20 # CHECK-INST: vwredsum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xc6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a c6 vredsum.vs v0, v4, v20, v0.t # CHECK-INST: vredsum.vs v0, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x20,0x4a,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 20 4a 00 diff --git a/llvm/test/MC/RISCV/rvv/shift.s b/llvm/test/MC/RISCV/rvv/shift.s --- a/llvm/test/MC/RISCV/rvv/shift.s +++ b/llvm/test/MC/RISCV/rvv/shift.s @@ -11,257 +11,257 @@ vsll.vv v8, v4, v20, v0.t # CHECK-INST: vsll.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x94] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 94 vsll.vv v8, v4, v20 # CHECK-INST: vsll.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x96] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 96 vsll.vx v8, v4, a0, v0.t # CHECK-INST: vsll.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x94] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 94 vsll.vx v8, v4, a0 # CHECK-INST: vsll.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x96] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 96 vsll.vi v8, v4, 31, v0.t # CHECK-INST: vsll.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x94] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f 94 vsll.vi v8, v4, 31 # CHECK-INST: vsll.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x96] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f 96 vsrl.vv v8, v4, v20, v0.t # CHECK-INST: vsrl.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xa0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a a0 vsrl.vv v8, v4, v20 # CHECK-INST: vsrl.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xa2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a a2 vsrl.vx v8, v4, a0, v0.t # CHECK-INST: vsrl.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xa0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 a0 vsrl.vx v8, v4, a0 # CHECK-INST: vsrl.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xa2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 a2 vsrl.vi v8, v4, 31, v0.t # CHECK-INST: vsrl.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f a0 vsrl.vi v8, v4, 31 # CHECK-INST: vsrl.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f a2 vsra.vv v8, v4, v20, v0.t # CHECK-INST: vsra.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xa4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a a4 vsra.vv v8, v4, v20 # CHECK-INST: vsra.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xa6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a a6 vsra.vx v8, v4, a0, v0.t # CHECK-INST: vsra.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xa4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 a4 vsra.vx v8, v4, a0 # CHECK-INST: vsra.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xa6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 a6 vsra.vi v8, v4, 31, v0.t # CHECK-INST: vsra.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f a4 vsra.vi v8, v4, 31 # CHECK-INST: vsra.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f a6 vnsrl.wv v8, v4, v20, v0.t # CHECK-INST: vnsrl.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xb0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a b0 vnsrl.wv v4, v4, v20, v0.t # CHECK-INST: vnsrl.wv v4, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x02,0x4a,0xb0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 02 4a b0 vnsrl.wv v8, v4, v20 # CHECK-INST: vnsrl.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xb2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a b2 vnsrl.wx v8, v4, a0, v0.t # CHECK-INST: vnsrl.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xb0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 b0 vnsrl.wx v8, v4, a0 # CHECK-INST: vnsrl.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xb2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 b2 vnsrl.wi v8, v4, 31, v0.t # CHECK-INST: vnsrl.wi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb0] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f b0 vnsrl.wi v8, v4, 31 # CHECK-INST: vnsrl.wi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f b2 vnsra.wv v8, v4, v20, v0.t # CHECK-INST: vnsra.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xb4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a b4 vnsra.wv v8, v4, v20 # CHECK-INST: vnsra.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xb6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a b6 vnsra.wx v8, v4, a0, v0.t # CHECK-INST: vnsra.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xb4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 b4 vnsra.wx v8, v4, a0 # CHECK-INST: vnsra.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xb6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 b6 vnsra.wi v8, v4, 31, v0.t # CHECK-INST: vnsra.wi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb4] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f b4 vnsra.wi v8, v4, 31 # CHECK-INST: vnsra.wi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb6] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f b6 vssrl.vv v8, v4, v20, v0.t # CHECK-INST: vssrl.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xa8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a a8 vssrl.vv v8, v4, v20 # CHECK-INST: vssrl.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xaa] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a aa vssrl.vx v8, v4, a0, v0.t # CHECK-INST: vssrl.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xa8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 a8 vssrl.vx v8, v4, a0 # CHECK-INST: vssrl.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xaa] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 aa vssrl.vi v8, v4, 31, v0.t # CHECK-INST: vssrl.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f a8 vssrl.vi v8, v4, 31 # CHECK-INST: vssrl.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xaa] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f aa vssra.vv v8, v4, v20, v0.t # CHECK-INST: vssra.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xac] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a ac vssra.vv v8, v4, v20 # CHECK-INST: vssra.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xae] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a ae vssra.vx v8, v4, a0, v0.t # CHECK-INST: vssra.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xac] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 ac vssra.vx v8, v4, a0 # CHECK-INST: vssra.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xae] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 ae vssra.vi v8, v4, 31, v0.t # CHECK-INST: vssra.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xac] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f ac vssra.vi v8, v4, 31 # CHECK-INST: vssra.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xae] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f ae diff --git a/llvm/test/MC/RISCV/rvv/store.s b/llvm/test/MC/RISCV/rvv/store.s --- a/llvm/test/MC/RISCV/rvv/store.s +++ b/llvm/test/MC/RISCV/rvv/store.s @@ -11,221 +11,221 @@ vsm.v v24, (a0) # CHECK-INST: vsm.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0xb5,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 0c b5 02 vse8.v v24, (a0), v0.t # CHECK-INST: vse8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 0c 05 00 vse8.v v24, (a0) # CHECK-INST: vse8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 0c 05 02 vse16.v v24, (a0), v0.t # CHECK-INST: vse16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 5c 05 00 vse16.v v24, (a0) # CHECK-INST: vse16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 5c 05 02 vse32.v v24, (a0), v0.t # CHECK-INST: vse32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 6c 05 00 vse32.v v24, (a0) # CHECK-INST: vse32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 6c 05 02 vse64.v v24, (a0), v0.t # CHECK-INST: vse64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0x00] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 7c 05 00 vse64.v v24, (a0) # CHECK-INST: vse64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 7c 05 02 vsse8.v v24, (a0), a1, v0.t # CHECK-INST: vsse8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 0c b5 08 vsse8.v v24, (a0), a1 # CHECK-INST: vsse8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 0c b5 0a vsse16.v v24, (a0), a1, v0.t # CHECK-INST: vsse16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 5c b5 08 vsse16.v v24, (a0), a1 # CHECK-INST: vsse16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 5c b5 0a vsse32.v v24, (a0), a1, v0.t # CHECK-INST: vsse32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 6c b5 08 vsse32.v v24, (a0), a1 # CHECK-INST: vsse32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 6c b5 0a vsse64.v v24, (a0), a1, v0.t # CHECK-INST: vsse64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 7c b5 08 vsse64.v v24, (a0), a1 # CHECK-INST: vsse64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 7c b5 0a vsuxei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 0c 45 04 vsuxei8.v v24, (a0), v4 # CHECK-INST: vsuxei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 0c 45 06 vsuxei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 5c 45 04 vsuxei16.v v24, (a0), v4 # CHECK-INST: vsuxei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 5c 45 06 vsuxei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 6c 45 04 vsuxei32.v v24, (a0), v4 # CHECK-INST: vsuxei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 6c 45 06 vsuxei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x04] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 7c 45 04 vsuxei64.v v24, (a0), v4 # CHECK-INST: vsuxei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x06] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 7c 45 06 vsoxei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 0c 45 0c vsoxei8.v v24, (a0), v4 # CHECK-INST: vsoxei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 0c 45 0e vsoxei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 5c 45 0c vsoxei16.v v24, (a0), v4 # CHECK-INST: vsoxei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 5c 45 0e vsoxei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 6c 45 0c vsoxei32.v v24, (a0), v4 # CHECK-INST: vsoxei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 6c 45 0e vsoxei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 7c 45 0c vsoxei64.v v24, (a0), v4 # CHECK-INST: vsoxei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 7c 45 0e vs1r.v v24, (a0) # CHECK-INST: vs1r.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x85,0x02] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 0c 85 02 vs2r.v v24, (a0) # CHECK-INST: vs2r.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x85,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 0c 85 22 vs4r.v v24, (a0) # CHECK-INST: vs4r.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x85,0x62] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 0c 85 62 vs8r.v v24, (a0) # CHECK-INST: vs8r.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x85,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 27 0c 85 e2 diff --git a/llvm/test/MC/RISCV/rvv/sub.s b/llvm/test/MC/RISCV/rvv/sub.s --- a/llvm/test/MC/RISCV/rvv/sub.s +++ b/llvm/test/MC/RISCV/rvv/sub.s @@ -11,299 +11,299 @@ vsub.vv v8, v4, v20, v0.t # CHECK-INST: vsub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 08 vsub.vv v8, v4, v20 # CHECK-INST: vsub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 0a vsub.vx v8, v4, a0, v0.t # CHECK-INST: vsub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x08] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 08 vsub.vx v8, v4, a0 # CHECK-INST: vsub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x0a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 0a vrsub.vx v8, v4, a0, v0.t # CHECK-INST: vrsub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 0c vrsub.vx v8, v4, a0 # CHECK-INST: vrsub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 0e vrsub.vi v8, v4, 15, v0.t # CHECK-INST: vrsub.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x0c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 0c vrsub.vi v8, v4, 15 # CHECK-INST: vrsub.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x0e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 0e vwsubu.vv v8, v4, v20, v0.t # CHECK-INST: vwsubu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xc8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a c8 vwsubu.vv v8, v4, v20 # CHECK-INST: vwsubu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xca] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a ca vwsubu.vx v8, v4, a0, v0.t # CHECK-INST: vwsubu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xc8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 c8 vwsubu.vx v8, v4, a0 # CHECK-INST: vwsubu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xca] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 ca vwsub.vv v8, v4, v20, v0.t # CHECK-INST: vwsub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xcc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a cc vwsub.vv v8, v4, v20 # CHECK-INST: vwsub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xce] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a ce vwsub.vx v8, v4, a0, v0.t # CHECK-INST: vwsub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xcc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 cc vwsub.vx v8, v4, a0 # CHECK-INST: vwsub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xce] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 ce vwsubu.wv v8, v4, v20, v0.t # CHECK-INST: vwsubu.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xd8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a d8 vwsubu.wv v8, v4, v20 # CHECK-INST: vwsubu.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xda] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a da vwsubu.wx v8, v4, a0, v0.t # CHECK-INST: vwsubu.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xd8] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 d8 vwsubu.wx v8, v4, a0 # CHECK-INST: vwsubu.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xda] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 da vwsub.wv v8, v4, v20, v0.t # CHECK-INST: vwsub.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xdc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a dc vwsub.wv v8, v4, v20 # CHECK-INST: vwsub.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xde] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a de vwsub.wx v8, v4, a0, v0.t # CHECK-INST: vwsub.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xdc] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 dc vwsub.wx v8, v4, a0 # CHECK-INST: vwsub.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xde] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 de vsbc.vvm v8, v4, v20, v0 # CHECK-INST: vsbc.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 48 vsbc.vvm v4, v4, v20, v0 # CHECK-INST: vsbc.vvm v4, v4, v20, v0 # CHECK-ENCODING: [0x57,0x02,0x4a,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 02 4a 48 vsbc.vvm v8, v4, v8, v0 # CHECK-INST: vsbc.vvm v8, v4, v8, v0 # CHECK-ENCODING: [0x57,0x04,0x44,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 44 48 vsbc.vxm v8, v4, a0, v0 # CHECK-INST: vsbc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x48] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 48 vmsbc.vvm v8, v4, v20, v0 # CHECK-INST: vmsbc.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x4c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 4c vmsbc.vvm v4, v4, v20, v0 # CHECK-INST: vmsbc.vvm v4, v4, v20, v0 # CHECK-ENCODING: [0x57,0x02,0x4a,0x4c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 02 4a 4c vmsbc.vvm v8, v4, v8, v0 # CHECK-INST: vmsbc.vvm v8, v4, v8, v0 # CHECK-ENCODING: [0x57,0x04,0x44,0x4c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 44 4c vmsbc.vxm v8, v4, a0, v0 # CHECK-INST: vmsbc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x4c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 4c vmsbc.vv v8, v4, v20 # CHECK-INST: vmsbc.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x4e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 4e vmsbc.vx v8, v4, a0 # CHECK-INST: vmsbc.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x4e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 4e vssubu.vv v8, v4, v20, v0.t # CHECK-INST: vssubu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x88] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 88 vssubu.vv v8, v4, v20 # CHECK-INST: vssubu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x8a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 8a vssubu.vx v8, v4, a0, v0.t # CHECK-INST: vssubu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x88] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 88 vssubu.vx v8, v4, a0 # CHECK-INST: vssubu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x8a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 8a vssub.vv v8, v4, v20, v0.t # CHECK-INST: vssub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x8c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 8c vssub.vv v8, v4, v20 # CHECK-INST: vssub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x8e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 8e vssub.vx v8, v4, a0, v0.t # CHECK-INST: vssub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x8c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 8c vssub.vx v8, v4, a0 # CHECK-INST: vssub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x8e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 8e vasub.vv v8, v4, v20, v0.t # CHECK-INST: vasub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x2c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 2c vasub.vv v8, v4, v20 # CHECK-INST: vasub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x2e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 2e vasub.vx v8, v4, a0, v0.t # CHECK-INST: vasub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x2c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 2c vasub.vx v8, v4, a0 # CHECK-INST: vasub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x2e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 2e vasubu.vv v8, v4, v20, v0.t # CHECK-INST: vasubu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x28] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 28 vasubu.vv v8, v4, v20 # CHECK-INST: vasubu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x2a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 24 4a 2a vasubu.vx v8, v4, a0, v0.t # CHECK-INST: vasubu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x28] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 28 vasubu.vx v8, v4, a0 # CHECK-INST: vasubu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x2a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 64 45 2a diff --git a/llvm/test/MC/RISCV/rvv/vsetvl.s b/llvm/test/MC/RISCV/rvv/vsetvl.s --- a/llvm/test/MC/RISCV/rvv/vsetvl.s +++ b/llvm/test/MC/RISCV/rvv/vsetvl.s @@ -12,150 +12,150 @@ vsetvli a2, a0, 0x224 # CHECK-INST: vsetvli a2, a0, 548 # CHECK-ENCODING: [0x57,0x76,0x45,0x22] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 45 22 vsetvli a2, a0, 0xd0 # CHECK-INST: vsetvli a2, a0, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 05 0d vsetvli a2, a0, 0xd1 # CHECK-INST: vsetvli a2, a0, e32, m2, ta, ma # CHECK-ENCODING: [0x57,0x76,0x15,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 15 0d vsetvli a2, a0, 0x50 # CHECK-INST: vsetvli a2, a0, e32, m1, ta, mu # CHECK-ENCODING: [0x57,0x76,0x05,0x05] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 05 05 vsetvli a2, a0, 0x90 # CHECK-INST: vsetvli a2, a0, e32, m1, tu, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x09] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 05 09 vsetvli a2, a0, 144 # CHECK-INST: vsetvli a2, a0, e32, m1, tu, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x09] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 05 09 vsetvli a2, a0, e32, m1, ta, ma # CHECK-INST: vsetvli a2, a0, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 05 0d vsetvli a2, a0, e32, m2, ta, ma # CHECK-INST: vsetvli a2, a0, e32, m2, ta, ma # CHECK-ENCODING: [0x57,0x76,0x15,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 15 0d vsetvli a2, a0, e32, m4, ta, ma # CHECK-INST: vsetvli a2, a0, e32, m4, ta, ma # CHECK-ENCODING: [0x57,0x76,0x25,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 25 0d vsetvli a2, a0, e32, m8, ta, ma # CHECK-INST: vsetvli a2, a0, e32, m8, ta, ma # CHECK-ENCODING: [0x57,0x76,0x35,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 35 0d vsetvli a2, a0, e32, mf2, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma # CHECK-ENCODING: [0x57,0x76,0x75,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 75 0d vsetvli a2, a0, e32, mf4, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf4, ta, ma # CHECK-ENCODING: [0x57,0x76,0x65,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 65 0d vsetvli a2, a0, e32, mf8, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf8, ta, ma # CHECK-ENCODING: [0x57,0x76,0x55,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 55 0d vsetvli a2, a0, e32, m1, ta, ma # CHECK-INST: vsetvli a2, a0, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x0d] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 05 0d vsetvli a2, a0, e32, m1, tu, ma # CHECK-INST: vsetvli a2, a0, e32, m1, tu, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x09] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 05 09 vsetvli a2, a0, e32, m1, ta, mu # CHECK-INST: vsetvli a2, a0, e32, m1, ta, mu # CHECK-ENCODING: [0x57,0x76,0x05,0x05] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 05 05 vsetvli a2, a0, e32, m1, tu, mu # CHECK-INST: vsetvli a2, a0, e32, m1 # CHECK-ENCODING: [0x57,0x76,0x05,0x01] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 05 01 vsetvl a2, a0, a1 # CHECK-INST: vsetvl a2, a0, a1 # CHECK-ENCODING: [0x57,0x76,0xb5,0x80] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 b5 80 # reserved filed: vlmul[2:0]=4, vsew[2:0]=0b1xx, non-zero bits 8/9/10. vsetivli a2, 0, 0x224 # CHECK-INST: vsetivli a2, 0, 548 # CHECK-ENCODING: [0x57,0x76,0x40,0xe2] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 40 e2 vsetivli a2, 0, 0xd0 # CHECK-INST: vsetivli a2, 0, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0x76,0x00,0xcd] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 00 cd vsetivli a2, 15, 0xd0 # CHECK-INST: vsetivli a2, 15, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0xf6,0x07,0xcd] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 f6 07 cd vsetivli a2, 15, 208 # CHECK-INST: vsetivli a2, 15, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0xf6,0x07,0xcd] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 f6 07 cd vsetivli a2, 0, e32, m1, ta, ma # CHECK-INST: vsetivli a2, 0, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0x76,0x00,0xcd] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 76 00 cd vsetivli a2, 15, e32, m1, ta, ma # CHECK-INST: vsetivli a2, 15, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0xf6,0x07,0xcd] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 f6 07 cd vsetivli a2, 31, e32, m1, ta, ma # CHECK-INST: vsetivli a2, 31, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0xf6,0x0f,0xcd] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 f6 0f cd diff --git a/llvm/test/MC/RISCV/rvv/xor.s b/llvm/test/MC/RISCV/rvv/xor.s --- a/llvm/test/MC/RISCV/rvv/xor.s +++ b/llvm/test/MC/RISCV/rvv/xor.s @@ -11,47 +11,47 @@ vxor.vv v8, v4, v20, v0.t # CHECK-INST: vxor.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x2c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 2c vxor.vv v8, v4, v20 # CHECK-INST: vxor.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x2e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 04 4a 2e vxor.vx v8, v4, a0, v0.t # CHECK-INST: vxor.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x2c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 2c vxor.vx v8, v4, a0 # CHECK-INST: vxor.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x2e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 44 45 2e vxor.vi v8, v4, 15, v0.t # CHECK-INST: vxor.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x2c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 2c vxor.vi v8, v4, 15 # CHECK-INST: vxor.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x2e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 47 2e vnot.v v8, v4, v0.t # CHECK-INST: vnot.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x2c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f 2c vnot.v v8, v4 # CHECK-INST: vnot.v v8, v4 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x2e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} # CHECK-UNKNOWN: 57 b4 4f 2e