diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ve-basic.ll b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ve-basic.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ve-basic.ll
@@ -0,0 +1,30 @@
+;; Check that the function regex for VE works as expected.
+; RUN: llc -mtriple=ve -exception-model=sjlj -relocation-model=static < %s | FileCheck %s
+
+;; Check that we accept .Ldsolocal$local: below the function label.
+; RUN: llc -mtriple=ve -exception-model=sjlj -relocation-model=pic < %s | FileCheck %s --check-prefix=PIC
+
+
+@gv0 = dso_local global i32 0, align 4
+@gv1 = dso_preemptable global i32 0, align 4
+
+define hidden i32 @"_Z54bar$ompvariant$bar"() {
+entry:
+  ret i32 2
+}
+
+define dso_local i32 @dsolocal() {
+entry:
+  call void @ext()
+  ret i32 2
+}
+
+declare void @ext()
+
+define i32 @load() {
+entry:
+  %a = load i32, i32* @gv0
+  %b = load i32, i32* @gv1
+  %c = add i32 %a, %b
+  ret i32 %c
+}
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ve-basic.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ve-basic.ll.expected
new file mode 100644
--- /dev/null
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/ve-basic.ll.expected
@@ -0,0 +1,92 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+;; Check that the function regex for VE works as expected.
+; RUN: llc -mtriple=ve -exception-model=sjlj -relocation-model=static < %s | FileCheck %s
+
+;; Check that we accept .Ldsolocal$local: below the function label.
+; RUN: llc -mtriple=ve -exception-model=sjlj -relocation-model=pic < %s | FileCheck %s --check-prefix=PIC
+
+
+@gv0 = dso_local global i32 0, align 4
+@gv1 = dso_preemptable global i32 0, align 4
+
+define hidden i32 @"_Z54bar$ompvariant$bar"() {
+entry:
+  ret i32 2
+}
+
+define dso_local i32 @dsolocal() {
+; CHECK-LABEL: dsolocal:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    st %s9, (, %s11)
+; CHECK-NEXT:    st %s10, 8(, %s11)
+; CHECK-NEXT:    or %s9, 0, %s11
+; CHECK-NEXT:    lea %s11, -240(, %s11)
+; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB1_2
+; CHECK-NEXT:  # %bb.1: # %entry
+; CHECK-NEXT:    ld %s61, 24(, %s14)
+; CHECK-NEXT:    or %s62, 0, %s0
+; CHECK-NEXT:    lea %s63, 315
+; CHECK-NEXT:    shm.l %s63, (%s61)
+; CHECK-NEXT:    shm.l %s8, 8(%s61)
+; CHECK-NEXT:    shm.l %s11, 16(%s61)
+; CHECK-NEXT:    monc
+; CHECK-NEXT:    or %s0, 0, %s62
+; CHECK-NEXT:  .LBB1_2: # %entry
+; CHECK-NEXT:    lea %s0, ext@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s12, ext@hi(, %s0)
+; CHECK-NEXT:    bsic %s10, (, %s12)
+; CHECK-NEXT:    or %s0, 2, (0)1
+; CHECK-NEXT:    or %s11, 0, %s9
+; CHECK-NEXT:    ld %s10, 8(, %s11)
+; CHECK-NEXT:    ld %s9, (, %s11)
+; CHECK-NEXT:    b.l.t (, %s10)
+entry:
+  call void @ext()
+  ret i32 2
+}
+
+declare void @ext()
+
+define i32 @load() {
+; CHECK-LABEL: load:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lea %s0, gv0@lo
+; CHECK-NEXT:    and %s0, %s0, (32)0
+; CHECK-NEXT:    lea.sl %s0, gv0@hi(, %s0)
+; CHECK-NEXT:    ldl.sx %s0, (, %s0)
+; CHECK-NEXT:    lea %s1, gv1@lo
+; CHECK-NEXT:    and %s1, %s1, (32)0
+; CHECK-NEXT:    lea.sl %s1, gv1@hi(, %s1)
+; CHECK-NEXT:    ldl.sx %s1, (, %s1)
+; CHECK-NEXT:    adds.w.sx %s0, %s0, %s1
+; CHECK-NEXT:    b.l.t (, %s10)
+;
+; PIC-LABEL: load:
+; PIC:       # %bb.0: # %entry
+; PIC-NEXT:    st %s15, 24(, %s11)
+; PIC-NEXT:    st %s16, 32(, %s11)
+; PIC-NEXT:    lea %s15, _GLOBAL_OFFSET_TABLE_@pc_lo(-24)
+; PIC-NEXT:    and %s15, %s15, (32)0
+; PIC-NEXT:    sic %s16
+; PIC-NEXT:    lea.sl %s15, _GLOBAL_OFFSET_TABLE_@pc_hi(%s16, %s15)
+; PIC-NEXT:    lea %s0, gv0@got_lo
+; PIC-NEXT:    and %s0, %s0, (32)0
+; PIC-NEXT:    lea.sl %s0, gv0@got_hi(, %s0)
+; PIC-NEXT:    ld %s0, (%s0, %s15)
+; PIC-NEXT:    lea %s1, gv1@got_lo
+; PIC-NEXT:    and %s1, %s1, (32)0
+; PIC-NEXT:    lea.sl %s1, gv1@got_hi(, %s1)
+; PIC-NEXT:    ld %s1, (%s1, %s15)
+; PIC-NEXT:    ldl.sx %s0, (, %s0)
+; PIC-NEXT:    ldl.sx %s1, (, %s1)
+; PIC-NEXT:    adds.w.sx %s0, %s0, %s1
+; PIC-NEXT:    ld %s16, 32(, %s11)
+; PIC-NEXT:    ld %s15, 24(, %s11)
+; PIC-NEXT:    b.l.t (, %s10)
+entry:
+  %a = load i32, i32* @gv0
+  %b = load i32, i32* @gv1
+  %c = add i32 %a, %b
+  ret i32 %c
+}
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/ve-basic.test b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/ve-basic.test
new file mode 100644
--- /dev/null
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/ve-basic.test
@@ -0,0 +1,5 @@
+# REQUIRES: ve-registered-target
+## Check that the function regex for VE works as expected.
+
+# RUN: cp -f %S/Inputs/ve-basic.ll %t.ll && %update_llc_test_checks %t.ll
+# RUN: diff -u %S/Inputs/ve-basic.ll.expected %t.ll