Index: flang/test/Lower/OpenMP/simd.f90
===================================================================
--- flang/test/Lower/OpenMP/simd.f90
+++ flang/test/Lower/OpenMP/simd.f90
@@ -1,6 +1,7 @@
 ! Tests for 2.9.3.1 Simd
 
 ! RUN: bbc -fopenmp -emit-fir %s -o - | FileCheck %s
+! RUN: bbc -fopenmp -emit-fir %s -o - | tco | FileCheck %s --check-prefixes="LLVMIR"
 
 !CHECK-LABEL: func @_QPsimdloop()
 subroutine simdloop
@@ -89,3 +90,29 @@
   end do
   !$OMP END SIMD
 end subroutine
+
+! LLVMIR-LABEL:  define void @_QPsimdloop_with_nested_loop()
+subroutine simdloop_with_nested_loop
+integer :: i, j
+integer :: a(10)
+! check if nested loop is handled correctly
+! LLVMIR-LABEL: omp_loop.preheader
+! LLVMIR-LABEL: omp_loop.header
+! LLVMIR-LABEL: omp_loop.cond
+! LLVMIR-LABEL: omp_loop.body
+! LLVMIR-LABEL: omp.simdloop.region3
+! LLVMIR-LABEL: omp.simdloop.region2
+! LLVMIR-LABEL: omp.simdloop.region1
+! LLVMIR-LABEL: omp.simdloop.region
+! LLVMIR-LABEL: omp.region.cont
+! LLVMIR-LABEL: omp_loop.inc
+! LLVMIR-LABEL: omp_loop.exit
+! LLVMIR-LABEL: omp_loop.after
+  !$OMP SIMD
+  do i=1, 10
+  do j=1, 10
+    a(i) = i
+  end do
+  end do
+  !$OMP END SIMD
+end subroutine
Index: mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
===================================================================
--- mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
+++ mlir/lib/Conversion/OpenMPToLLVM/OpenMPToLLVM.cpp
@@ -97,13 +97,13 @@
 void mlir::configureOpenMPToLLVMConversionLegality(
     ConversionTarget &target, LLVMTypeConverter &typeConverter) {
   target.addDynamicallyLegalOp<mlir::omp::CriticalOp, mlir::omp::ParallelOp,
-                               mlir::omp::WsLoopOp, mlir::omp::MasterOp,
-                               mlir::omp::SectionsOp, mlir::omp::SingleOp>(
-      [&](Operation *op) {
-        return typeConverter.isLegal(&op->getRegion(0)) &&
-               typeConverter.isLegal(op->getOperandTypes()) &&
-               typeConverter.isLegal(op->getResultTypes());
-      });
+                               mlir::omp::WsLoopOp, mlir::omp::SimdLoopOp,
+                               mlir::omp::MasterOp, mlir::omp::SectionsOp,
+                               mlir::omp::SingleOp>([&](Operation *op) {
+    return typeConverter.isLegal(&op->getRegion(0)) &&
+           typeConverter.isLegal(op->getOperandTypes()) &&
+           typeConverter.isLegal(op->getResultTypes());
+  });
   target
       .addDynamicallyLegalOp<mlir::omp::AtomicReadOp, mlir::omp::AtomicWriteOp,
                              mlir::omp::FlushOp, mlir::omp::ThreadprivateOp>(
@@ -123,6 +123,7 @@
       RegionOpConversion<omp::MasterOp>, ReductionOpConversion,
       RegionOpConversion<omp::MasterOp>, RegionOpConversion<omp::ParallelOp>,
       RegionOpConversion<omp::WsLoopOp>, RegionOpConversion<omp::SectionsOp>,
+      RegionOpConversion<omp::SimdLoopOp>, RegionOpConversion<omp::SectionsOp>,
       RegionOpConversion<omp::SingleOp>,
       RegionLessOpWithVarOperandsConversion<omp::AtomicReadOp>,
       RegionLessOpWithVarOperandsConversion<omp::AtomicWriteOp>,