diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2538,7 +2538,12 @@
     else
       return false;
 
-    PredsToUpdate.push_back(std::make_pair(&(UseMI->getOperand(0)), Pred));
+    // Convert the comparison and its user to a compare against zero with the
+    // appropriate predicate on the branch. Zero comparison might provide
+    // optimization opportunities post-RA (see optimization in
+    // PPCPreEmitPeephole.cpp).
+    UseMI->getOperand(0).setImm(Pred);
+    CmpInstr.getOperand(2).setImm(0);
   }
 
   // Search for Sub.
diff --git a/llvm/test/CodeGen/PowerPC/common-chain.ll b/llvm/test/CodeGen/PowerPC/common-chain.ll
--- a/llvm/test/CodeGen/PowerPC/common-chain.ll
+++ b/llvm/test/CodeGen/PowerPC/common-chain.ll
@@ -35,8 +35,8 @@
 define i64 @two_chain_same_offset_succ(i8* %p, i64 %offset, i64 %base1, i64 %n) {
 ; CHECK-LABEL: two_chain_same_offset_succ:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpdi r6, 1
-; CHECK-NEXT:    blt cr0, .LBB0_4
+; CHECK-NEXT:    cmpdi r6, 0
+; CHECK-NEXT:    ble cr0, .LBB0_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    sldi r7, r4, 1
 ; CHECK-NEXT:    mtctr r6
@@ -140,9 +140,9 @@
 define i64 @not_perfect_chain_all_same_offset_fail(i8* %p, i64 %offset, i64 %base1, i64 %n) {
 ; CHECK-LABEL: not_perfect_chain_all_same_offset_fail:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpdi r6, 1
+; CHECK-NEXT:    cmpdi r6, 0
 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-NEXT:    blt cr0, .LBB1_4
+; CHECK-NEXT:    ble cr0, .LBB1_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    sldi r7, r4, 1
 ; CHECK-NEXT:    sldi r9, r4, 2
@@ -245,8 +245,8 @@
 define i64 @no_enough_elements_fail(i8* %p, i64 %offset, i64 %base1, i64 %n) {
 ; CHECK-LABEL: no_enough_elements_fail:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpdi r6, 1
-; CHECK-NEXT:    blt cr0, .LBB2_4
+; CHECK-NEXT:    cmpdi r6, 0
+; CHECK-NEXT:    ble cr0, .LBB2_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    sldi r7, r4, 1
 ; CHECK-NEXT:    mtctr r6
@@ -333,8 +333,8 @@
 define i64 @no_reuseable_offset_fail(i8* %p, i64 %offset, i64 %base1, i64 %n) {
 ; CHECK-LABEL: no_reuseable_offset_fail:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpdi r6, 1
-; CHECK-NEXT:    blt cr0, .LBB3_4
+; CHECK-NEXT:    cmpdi r6, 0
+; CHECK-NEXT:    ble cr0, .LBB3_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    sldi r9, r4, 3
 ; CHECK-NEXT:    mtctr r6
@@ -440,11 +440,11 @@
 define i64 @not_same_offset_fail(i8* %p, i64 %offset, i64 %base1, i64 %n) {
 ; CHECK-LABEL: not_same_offset_fail:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpdi r6, 1
+; CHECK-NEXT:    cmpdi r6, 0
 ; CHECK-NEXT:    std r28, -32(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
-; CHECK-NEXT:    blt cr0, .LBB4_3
+; CHECK-NEXT:    ble cr0, .LBB4_3
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    mulli r11, r4, 10
 ; CHECK-NEXT:    sldi r8, r4, 2
@@ -564,8 +564,8 @@
 define i64 @two_chain_different_offsets_succ(i8* %p, i64 %offset, i64 %base1, i64 %n) {
 ; CHECK-LABEL: two_chain_different_offsets_succ:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpdi r6, 1
-; CHECK-NEXT:    blt cr0, .LBB5_4
+; CHECK-NEXT:    cmpdi r6, 0
+; CHECK-NEXT:    ble cr0, .LBB5_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    sldi r8, r4, 2
 ; CHECK-NEXT:    add r7, r5, r4
@@ -666,8 +666,8 @@
 define i64 @two_chain_two_bases_succ(i8* %p, i64 %offset, i64 %base1, i64 %base2, i64 %n) {
 ; CHECK-LABEL: two_chain_two_bases_succ:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpdi r7, 1
-; CHECK-NEXT:    blt cr0, .LBB6_4
+; CHECK-NEXT:    cmpdi r7, 0
+; CHECK-NEXT:    ble cr0, .LBB6_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    add r6, r6, r4
 ; CHECK-NEXT:    add r5, r5, r4
@@ -751,7 +751,7 @@
 define signext i32 @spill_reduce_succ(double* %input1, double* %input2, double* %output, i64 %m, i64 %inc1, i64 %inc2, i64 %inc3, i64 %inc4, i64 %inc) {
 ; CHECK-LABEL: spill_reduce_succ:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpdi r6, 1
+; CHECK-NEXT:    cmpdi r6, 0
 ; CHECK-NEXT:    std r14, -144(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r15, -136(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r16, -128(r1) # 8-byte Folded Spill
@@ -774,7 +774,7 @@
 ; CHECK-NEXT:    std r9, -160(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r8, -176(r1) # 8-byte Folded Spill
 ; CHECK-NEXT:    std r7, -168(r1) # 8-byte Folded Spill
-; CHECK-NEXT:    blt cr0, .LBB7_7
+; CHECK-NEXT:    ble cr0, .LBB7_7
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    sldi r6, r6, 2
 ; CHECK-NEXT:    li r7, 1
diff --git a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll
--- a/llvm/test/CodeGen/PowerPC/f128-aggregates.ll
+++ b/llvm/test/CodeGen/PowerPC/f128-aggregates.ll
@@ -545,7 +545,7 @@
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    std r4, 40(r1)
 ; CHECK-NEXT:    addis r4, r2, .LCPI17_0@toc@ha
-; CHECK-NEXT:    cmpwi r3, 1
+; CHECK-NEXT:    cmpwi r3, 0
 ; CHECK-NEXT:    std r5, 48(r1)
 ; CHECK-NEXT:    addi r4, r4, .LCPI17_0@toc@l
 ; CHECK-NEXT:    std r6, 56(r1)
@@ -554,7 +554,7 @@
 ; CHECK-NEXT:    lxv v2, 0(r4)
 ; CHECK-NEXT:    std r9, 80(r1)
 ; CHECK-NEXT:    std r10, 88(r1)
-; CHECK-NEXT:    bltlr cr0
+; CHECK-NEXT:    blelr cr0
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    addi r3, r1, 40
 ; CHECK-NEXT:    addi r4, r1, 72
@@ -569,7 +569,7 @@
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    std r4, 56(r1)
 ; CHECK-BE-NEXT:    addis r4, r2, .LCPI17_0@toc@ha
-; CHECK-BE-NEXT:    cmpwi r3, 1
+; CHECK-BE-NEXT:    cmpwi r3, 0
 ; CHECK-BE-NEXT:    std r5, 64(r1)
 ; CHECK-BE-NEXT:    addi r4, r4, .LCPI17_0@toc@l
 ; CHECK-BE-NEXT:    std r6, 72(r1)
@@ -578,7 +578,7 @@
 ; CHECK-BE-NEXT:    lxv v2, 0(r4)
 ; CHECK-BE-NEXT:    std r9, 96(r1)
 ; CHECK-BE-NEXT:    std r10, 104(r1)
-; CHECK-BE-NEXT:    bltlr cr0
+; CHECK-BE-NEXT:    blelr cr0
 ; CHECK-BE-NEXT:  # %bb.1: # %if.end
 ; CHECK-BE-NEXT:    addi r3, r1, 56
 ; CHECK-BE-NEXT:    addi r4, r1, 88
@@ -599,7 +599,7 @@
 ; CHECK-P8-NEXT:    std r0, 16(r1)
 ; CHECK-P8-NEXT:    stdu r1, -64(r1)
 ; CHECK-P8-NEXT:    addis r11, r2, .LCPI17_0@toc@ha
-; CHECK-P8-NEXT:    cmpwi r3, 1
+; CHECK-P8-NEXT:    cmpwi r3, 0
 ; CHECK-P8-NEXT:    std r4, 104(r1)
 ; CHECK-P8-NEXT:    std r5, 112(r1)
 ; CHECK-P8-NEXT:    std r6, 120(r1)
@@ -610,7 +610,7 @@
 ; CHECK-P8-NEXT:    std r9, 144(r1)
 ; CHECK-P8-NEXT:    std r10, 152(r1)
 ; CHECK-P8-NEXT:    xxswapd v3, vs0
-; CHECK-P8-NEXT:    blt cr0, .LBB17_2
+; CHECK-P8-NEXT:    ble cr0, .LBB17_2
 ; CHECK-P8-NEXT:  # %bb.1: # %if.end
 ; CHECK-P8-NEXT:    addi r30, r1, 104
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r30
diff --git a/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll b/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
--- a/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
+++ b/llvm/test/CodeGen/PowerPC/loop-instr-form-prepare.ll
@@ -793,8 +793,8 @@
 define float @test_ds_float(i8* %0, i32 signext %1) {
 ; CHECK-LABEL: test_ds_float:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpwi r4, 1
-; CHECK-NEXT:    blt cr0, .LBB7_4
+; CHECK-NEXT:    cmpwi r4, 0
+; CHECK-NEXT:    ble cr0, .LBB7_4
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    clrldi r4, r4, 32
 ; CHECK-NEXT:    addi r3, r3, 4002
@@ -875,8 +875,8 @@
 define float @test_ds_combine_float_int(i8* %0, i32 signext %1) {
 ; CHECK-LABEL: test_ds_combine_float_int:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpwi r4, 1
-; CHECK-NEXT:    blt cr0, .LBB8_4
+; CHECK-NEXT:    cmpwi r4, 0
+; CHECK-NEXT:    ble cr0, .LBB8_4
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    clrldi r4, r4, 32
 ; CHECK-NEXT:    addi r3, r3, 4002
@@ -958,8 +958,8 @@
 define i64 @test_ds_lwa_prep(i8* %0, i32 signext %1) {
 ; CHECK-LABEL: test_ds_lwa_prep:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpwi r4, 1
-; CHECK-NEXT:    blt cr0, .LBB9_4
+; CHECK-NEXT:    cmpwi r4, 0
+; CHECK-NEXT:    ble cr0, .LBB9_4
 ; CHECK-NEXT:  # %bb.1: # %.preheader
 ; CHECK-NEXT:    mtctr r4
 ; CHECK-NEXT:    addi r5, r3, 2
diff --git a/llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll b/llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
--- a/llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
+++ b/llvm/test/CodeGen/PowerPC/loop-instr-prep-non-const-increasement.ll
@@ -17,8 +17,8 @@
 define i64 @foo(i8* %p, i32 signext %n, i32 signext %count) {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpwi r4, 1
-; CHECK-NEXT:    blt cr0, .LBB0_4
+; CHECK-NEXT:    cmpwi r4, 0
+; CHECK-NEXT:    ble cr0, .LBB0_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    addi r6, r3, 5
 ; CHECK-NEXT:    addi r3, r4, -1
@@ -84,8 +84,8 @@
 define zeroext i8 @foo1(i8* %p, i32 signext %n, i32 signext %count) {
 ; CHECK-LABEL: foo1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpwi r4, 1
-; CHECK-NEXT:    blt cr0, .LBB1_4
+; CHECK-NEXT:    cmpwi r4, 0
+; CHECK-NEXT:    ble cr0, .LBB1_4
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    sub r3, r3, r5
 ; CHECK-NEXT:    addi r6, r3, 1000
diff --git a/llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll b/llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
--- a/llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
+++ b/llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll
@@ -15,8 +15,8 @@
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    ld r5, 0(r3)
-; CHECK-NEXT:    cmpdi r5, 1
-; CHECK-NEXT:    bltlr cr0
+; CHECK-NEXT:    cmpdi r5, 0
+; CHECK-NEXT:    blelr cr0
 ; CHECK-NEXT:  # %bb.1: # %_loop_1_do_.lr.ph
 ; CHECK-NEXT:    addi r3, r4, 1
 ; CHECK-NEXT:    addi r4, r5, -1
@@ -42,8 +42,8 @@
 ; CHECK-BE-LABEL: foo:
 ; CHECK-BE:       # %bb.0: # %entry
 ; CHECK-BE-NEXT:    ld r5, 0(r3)
-; CHECK-BE-NEXT:    cmpdi r5, 1
-; CHECK-BE-NEXT:    bltlr cr0
+; CHECK-BE-NEXT:    cmpdi r5, 0
+; CHECK-BE-NEXT:    blelr cr0
 ; CHECK-BE-NEXT:  # %bb.1: # %_loop_1_do_.lr.ph
 ; CHECK-BE-NEXT:    addi r3, r4, 1
 ; CHECK-BE-NEXT:    addi r4, r5, -1
diff --git a/llvm/test/CodeGen/PowerPC/pr47373.ll b/llvm/test/CodeGen/PowerPC/pr47373.ll
--- a/llvm/test/CodeGen/PowerPC/pr47373.ll
+++ b/llvm/test/CodeGen/PowerPC/pr47373.ll
@@ -20,8 +20,8 @@
 ; CHECK-NEXT:    mr r30, r3
 ; CHECK-NEXT:    bl b
 ; CHECK-NEXT:    nop
-; CHECK-NEXT:    cmpwi r30, 1
-; CHECK-NEXT:    blt cr0, .LBB0_9
+; CHECK-NEXT:    cmpwi r30, 0
+; CHECK-NEXT:    ble cr0, .LBB0_9
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    cmplwi r30, 4
 ; CHECK-NEXT:    clrldi r4, r30, 32
diff --git a/llvm/test/CodeGen/PowerPC/shrink-wrap.ll b/llvm/test/CodeGen/PowerPC/shrink-wrap.ll
--- a/llvm/test/CodeGen/PowerPC/shrink-wrap.ll
+++ b/llvm/test/CodeGen/PowerPC/shrink-wrap.ll
@@ -1,6 +1,6 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 | FileCheck  %s --check-prefixes=CHECK,CHECK64
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr9 -mattr=-altivec | FileCheck  %s --check-prefixes=CHECK,CHECK32
-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr9 -mattr=-altivec | FileCheck  %s --check-prefixes=CHECK,CHECK64
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr9 -mattr=-altivec | FileCheck  %s --check-prefixes=CHECKAIX,CHECK64
 
 define signext i32 @shrinkwrapme(i32 signext %a, i32 signext %lim) {
 entry:
@@ -33,7 +33,8 @@
 
 ; CHECK32-COUNT-18:   stw
 
-; CHECK:              blt 0, {{.*}}BB0_3
+; CHECK:              ble 0, {{.*}}BB0_3
+; CHECKAIX:           blt 0, {{.*}}BB0_3
 ; CHECK:            # %bb.1:
 ; CHECK:              li
 ; CHECK:            {{.*}}BB0_2:
diff --git a/llvm/test/CodeGen/PowerPC/spe.ll b/llvm/test/CodeGen/PowerPC/spe.ll
--- a/llvm/test/CodeGen/PowerPC/spe.ll
+++ b/llvm/test/CodeGen/PowerPC/spe.ll
@@ -848,8 +848,8 @@
 ; EFPU2-NEXT:    stw 0, 4(1)
 ; EFPU2-NEXT:    stwu 1, -16(1)
 ; EFPU2-NEXT:    bl __gtdf2
-; EFPU2-NEXT:    cmpwi 3, 1
-; EFPU2-NEXT:    blt 0, .LBB37_2
+; EFPU2-NEXT:    cmpwi 3, 0
+; EFPU2-NEXT:    ble 0, .LBB37_2
 ; EFPU2-NEXT:  # %bb.1: # %tr
 ; EFPU2-NEXT:    li 3, 1
 ; EFPU2-NEXT:    b .LBB37_3
@@ -908,8 +908,8 @@
 ; EFPU2-NEXT:    stw 0, 4(1)
 ; EFPU2-NEXT:    stwu 1, -16(1)
 ; EFPU2-NEXT:    bl __ledf2
-; EFPU2-NEXT:    cmpwi 3, 1
-; EFPU2-NEXT:    blt 0, .LBB38_2
+; EFPU2-NEXT:    cmpwi 3, 0
+; EFPU2-NEXT:    ble 0, .LBB38_2
 ; EFPU2-NEXT:  # %bb.1: # %tr
 ; EFPU2-NEXT:    li 3, 1
 ; EFPU2-NEXT:    b .LBB38_3
@@ -1324,8 +1324,8 @@
 ; EFPU2-NEXT:    stw 0, 4(1)
 ; EFPU2-NEXT:    stwu 1, -16(1)
 ; EFPU2-NEXT:    bl __ltdf2
-; EFPU2-NEXT:    cmpwi 3, -1
-; EFPU2-NEXT:    bgt 0, .LBB45_2
+; EFPU2-NEXT:    cmpwi 3, 0
+; EFPU2-NEXT:    bge 0, .LBB45_2
 ; EFPU2-NEXT:  # %bb.1: # %tr
 ; EFPU2-NEXT:    li 3, 1
 ; EFPU2-NEXT:    b .LBB45_3
@@ -1384,8 +1384,8 @@
 ; EFPU2-NEXT:    stw 0, 4(1)
 ; EFPU2-NEXT:    stwu 1, -16(1)
 ; EFPU2-NEXT:    bl __gedf2
-; EFPU2-NEXT:    cmpwi 3, -1
-; EFPU2-NEXT:    bgt 0, .LBB46_2
+; EFPU2-NEXT:    cmpwi 3, 0
+; EFPU2-NEXT:    bge 0, .LBB46_2
 ; EFPU2-NEXT:  # %bb.1: # %tr
 ; EFPU2-NEXT:    li 3, 1
 ; EFPU2-NEXT:    b .LBB46_3
@@ -1782,10 +1782,10 @@
 ; CHECK-NEXT:    mflr 0
 ; CHECK-NEXT:    stw 0, 4(1)
 ; CHECK-NEXT:    stwu 1, -32(1)
-; CHECK-NEXT:    cmpwi 3, 1
+; CHECK-NEXT:    cmpwi 3, 0
 ; CHECK-NEXT:    evstdd 29, 8(1) # 8-byte Folded Spill
 ; CHECK-NEXT:    evstdd 30, 16(1) # 8-byte Folded Spill
-; CHECK-NEXT:    blt 0, .LBB56_3
+; CHECK-NEXT:    ble 0, .LBB56_3
 ; CHECK-NEXT:  # %bb.1: # %for.body.preheader
 ; CHECK-NEXT:    mr 30, 3
 ; CHECK-NEXT:    li 29, 0
diff --git a/llvm/test/CodeGen/PowerPC/store-constant.ll b/llvm/test/CodeGen/PowerPC/store-constant.ll
--- a/llvm/test/CodeGen/PowerPC/store-constant.ll
+++ b/llvm/test/CodeGen/PowerPC/store-constant.ll
@@ -196,8 +196,8 @@
 define void @SetArr(i32 signext %Len) {
 ; CHECK-LABEL: SetArr:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    cmpwi 3, 1
-; CHECK-NEXT:    bltlr 0
+; CHECK-NEXT:    cmpwi 3, 0
+; CHECK-NEXT:    blelr 0
 ; CHECK-NEXT:  # %bb.1: # %for.body.lr.ph
 ; CHECK-NEXT:    addis 4, 2, .LC5@toc@ha
 ; CHECK-NEXT:    addis 5, 2, .LC6@toc@ha