diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -44,6 +44,8 @@ // CHECK-NOT: __riscv_svpbmt // CHECK-NOT: __riscv_svinval // CHECK-NOT: __riscv_xventanacondops +// CHECK-NOT: __riscv_zca +// CHECK-NOT: __riscv_zcb // CHECK-NOT: __riscv_zcd // CHECK-NOT: __riscv_zcf // CHECK-NOT: __riscv_h @@ -464,6 +466,19 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-XTHEADVDOT-EXT %s // CHECK-XTHEADVDOT-EXT: __riscv_xtheadvdot 1000000{{$}} +// RUN: %clang -target riscv32 -march=rv32izca0p70 -menable-experimental-extensions \ +// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCA-EXT %s +// RUN: %clang -target riscv64 -march=rv64izca0p70 -menable-experimental-extensions \ +// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCA-EXT %s +// CHECK-ZCA-EXT: __riscv_zca 70000{{$}} + +// RUN: %clang -target riscv32 -march=rv32izcb0p70 -menable-experimental-extensions \ +// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCB-EXT %s +// RUN: %clang -target riscv64 -march=rv64izcb0p70 -menable-experimental-extensions \ +// RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCB-EXT %s +// CHECK-ZCB-EXT: __riscv_zca 70000{{$}} +// CHECK-ZCB-EXT: __riscv_zcb 70000{{$}} + // RUN: %clang -target riscv32 -march=rv32izcd0p70 -menable-experimental-extensions \ // RUN: -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-ZCD-EXT %s // RUN: %clang -target riscv64 -march=rv64izcd0p70 -menable-experimental-extensions \ diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -115,6 +115,7 @@ {"zihintntl", RISCVExtensionVersion{0, 2}}, {"zca", RISCVExtensionVersion{0, 70}}, + {"zcb", RISCVExtensionVersion{0, 70}}, {"zcd", RISCVExtensionVersion{0, 70}}, {"zcf", RISCVExtensionVersion{0, 70}}, {"zvfh", RISCVExtensionVersion{0, 1}}, @@ -826,6 +827,7 @@ static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"}; static const char *ImpliedExtsZvfh[] = {"zve32f"}; static const char *ImpliedExtsXTHeadVdot[] = {"v"}; +static const char *ImpliedExtsZcb[] = {"zca"}; struct ImpliedExtsEntry { StringLiteral Name; @@ -842,6 +844,7 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = { {{"v"}, {ImpliedExtsV}}, {{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}}, + {{"zcb"}, {ImpliedExtsZcb}}, {{"zdinx"}, {ImpliedExtsZdinx}}, {{"zfh"}, {ImpliedExtsZfh}}, {{"zfhmin"}, {ImpliedExtsZfhmin}}, diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -618,6 +618,16 @@ VK == RISCVMCExpr::VK_RISCV_None; } + bool isUImm2Lsb0() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) + return false; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isShiftedUInt<1, 1>(Imm) && + VK == RISCVMCExpr::VK_RISCV_None; + } + bool isUImm7Lsb00() const { if (!isImm()) return false; @@ -1151,6 +1161,9 @@ return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1); case Match_InvalidUImm2: return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 2) - 1); + case Match_InvalidUImm2Lsb0: + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 2, + "immediate must be one of"); case Match_InvalidUImm3: return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 3) - 1); case Match_InvalidUImm5: diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -299,6 +299,14 @@ "'Zca' (part of the C extension, excluding " "compressed floating point loads/stores)">; +def FeatureExtZcb + : SubtargetFeature<"experimental-zcb", "HasStdExtZcb", "true", + "'Zcb' (Shortened format for basic bit manipulation instructions)", + [FeatureExtZca]>; +def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">, + AssemblerPredicate<(all_of FeatureExtZcb), + "'Zcb' (Shortened format for basic bit manipulation instructions)">; + def FeatureExtZcd : SubtargetFeature<"experimental-zcd", "HasStdExtZcd", "true", "'Zcd' (Compressed Double-Precision Floating-Point Instructions)">; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1853,6 +1853,7 @@ include "RISCVInstrInfoD.td" include "RISCVInstrInfoC.td" include "RISCVInstrInfoZb.td" +include "RISCVInstrInfoZc.td" include "RISCVInstrInfoZk.td" include "RISCVInstrInfoV.td" include "RISCVInstrInfoZfh.td" diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -41,6 +41,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefix=RV32SVPBMT %s ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV32ZCA %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefix=RV32ZCB %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s @@ -87,6 +88,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV64ZCA %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefix=RV64ZCB %s ; RV32M: .attribute 5, "rv32i2p0_m2p0" ; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0" @@ -129,6 +131,7 @@ ; RV32SVPBMT: .attribute 5, "rv32i2p0_svpbmt1p0" ; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0" ; RV32ZCA: .attribute 5, "rv32i2p0_zca0p70" +; RV32ZCB: .attribute 5, "rv32i2p0_zca0p70_zcb0p70" ; RV64M: .attribute 5, "rv64i2p0_m2p0" ; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0" @@ -175,6 +178,7 @@ ; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0" ; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1" ; RV64ZCA: .attribute 5, "rv64i2p0_zca0p70" +; RV64ZCB: .attribute 5, "rv64i2p0_zca0p70_zcb0p70" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -179,6 +179,9 @@ .attribute arch, "rv32izca0p70" # CHECK: attribute 5, "rv32i2p0_zca0p70" +.attribute arch, "rv32izcb0p70" +# CHECK: attribute 5, "rv32i2p0_zca0p70_zcb0p70" + .attribute arch, "rv32izawrs1p0" # CHECK: attribute 5, "rv32i2p0_zawrs1p0"