diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -110,6 +110,7 @@ {"zbt", RISCVExtensionVersion{0, 93}}, {"zvfh", RISCVExtensionVersion{0, 1}}, {"zca", RISCVExtensionVersion{0, 70}}, + {"zcb", RISCVExtensionVersion{0, 70}}, }; static bool stripExperimentalPrefix(StringRef &Ext) { diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -618,6 +618,16 @@ VK == RISCVMCExpr::VK_RISCV_None; } + bool isUImm2Lsb0() const { + int64_t Imm; + RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; + if (!isImm()) + return false; + bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); + return IsConstantImm && isShiftedUInt<1, 1>(Imm) && + VK == RISCVMCExpr::VK_RISCV_None; + } + bool isUImm7Lsb00() const { if (!isImm()) return false; @@ -1151,6 +1161,9 @@ return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1); case Match_InvalidUImm2: return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 2) - 1); + case Match_InvalidUImm2Lsb0: + return generateImmOutOfRangeError(Operands, ErrorInfo, 0, 2, + "immediate must be one of"); case Match_InvalidUImm3: return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 3) - 1); case Match_InvalidUImm5: diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -340,6 +340,14 @@ "'C' (Compressed Instructions) or " "'Zca' (part of the C extension, excluding compressed floating point loads/stores)">; +def FeatureExtZcb + : SubtargetFeature<"experimental-zcb", "HasStdExtZcb", "true", + "'Zcb' (Shortened format for basic bit manipulation instructions)", + [FeatureExtZca]>; +def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">, + AssemblerPredicate<(all_of FeatureExtZcb), + "'Zcb' (Shortened format for basic bit manipulation instructions)">; + def FeatureNoRVCHints : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false", "Disable RVC Hint Instructions.">; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1677,5 +1677,6 @@ include "RISCVInstrInfoZb.td" include "RISCVInstrInfoZk.td" include "RISCVInstrInfoV.td" +include "RISCVInstrInfoZc.td" include "RISCVInstrInfoZfh.td" include "RISCVInstrInfoZicbo.td" diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td new file mode 100644 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td @@ -0,0 +1,154 @@ +//===-- RISCVInstrInfoZc.td - RISC-V 'Zc' instructions -----*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// This file describes the RISC-V instructions from the 'Zc' Code-size +/// reduction extension, version 0.24. +/// This version is still experimental as the 'Zc' extension hasn't been +/// ratified yet. +/// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Operand and SDNode transformation definitions. +//===----------------------------------------------------------------------===// + +def uimm2_zc : Operand, + ImmLeaf(Imm);}]> { + let ParserMatchClass = UImmAsmOperand<2>; + let DecoderMethod = "decodeUImmOperand<2>"; + let OperandType = "OPERAND_UIMM2"; + let OperandNamespace = "RISCVOp"; + let MCOperandPredicate = [{ + int64_t Imm; + if (!MCOp.evaluateAsConstantImm(Imm)) + return false; + return isUInt<2>(Imm); + }]; +} + +def uimm2_lsb0 : Operand, + ImmLeaf(Imm);}]> { + let ParserMatchClass = UImmAsmOperand<2, "Lsb0">; + let EncoderMethod = "getImmOpValue"; + let DecoderMethod = "decodeUImmOperand<2>"; + let MCOperandPredicate = [{ + int64_t Imm; + if (!MCOp.evaluateAsConstantImm(Imm)) + return false; + return isShiftedUInt<1, 1>(Imm); + }]; +} + +//===----------------------------------------------------------------------===// +// Instruction Class Templates +//===----------------------------------------------------------------------===// + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class RVZcArith_r funct2, bits<3> opcode, string opcodestr> + : RVInst16<(outs GPRC:$rs_wb), (ins GPRC:$rs), opcodestr, "$rs", [], InstFormatCB> { + bits<3> rs; + let Constraints = "$rs = $rs_wb"; + + let Inst{15-13} = 0b100; + let Inst{12-10} = 0b111; + let Inst{9-7} = rs; + let Inst{6-5} = funct2; + let Inst{4-2} = opcode; + let Inst{1-0} = 0b01; +} + +let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in +class RVZcArith_rr funct6,bits<2> funct2, bits<2> opcode, string opcodestr> + : RVInst16<(outs GPRC:$rs1_wb), (ins GPRC:$rs1, GPRC:$rs2), opcodestr, "$rs1, $rs2", [], InstFormatCB> { + bits<3> rs1; + bits<3> rs2; + let Constraints = "$rs1 = $rs1_wb"; + + let Inst{15-10} = funct6; + let Inst{9-7} = rs1; + let Inst{6-5} = funct2; + let Inst{4-2} = rs2; + let Inst{1-0} = opcode; +} + +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +class ZcLoad_ri funct3, bits<2> opcode, string opcodestr, + RegisterClass cls, DAGOperand opnd> + : RVInst16CL; + +let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in +class ZcStore_ri funct3, bits<2> opcode, string opcodestr, + RegisterClass cls, DAGOperand opnd> + : RVInst16CS; + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + +// ZCB + +let Predicates = [HasStdExtZcb, IsRV64] in { +def C_ZEXT_W : RVZcArith_r<0b11, 0b100 , "c.zext.w">, Sched<[]>; +} + +let Predicates = [HasStdExtZcb] in { +def C_ZEXT_B : RVZcArith_r<0b11, 0b000 , "c.zext.b">, Sched<[]>; +def C_ZEXT_H : RVZcArith_r<0b11, 0b010 , "c.zext.h">, Sched<[]>; + +def C_SEXT_B : RVZcArith_r<0b11, 0b001 , "c.sext.b">, Sched<[]>; +def C_SEXT_H : RVZcArith_r<0b11, 0b011 , "c.sext.h">, Sched<[]>; + +def C_MUL : RVZcArith_rr<0b100111, 0b10, 0b01, "c.mul">, Sched<[]>; + +def C_NOT_ZCE : RVZcArith_r<0b11, 0b101 , "c.not">, Sched<[]>; + +def C_LBU : ZcLoad_ri<0b100, 0b00, "c.lbu", GPRC, uimm2_zc>, + Sched<[]> { +bits<2> imm; + +let Inst{12-10} = 0b000; +let Inst{6-5} = imm{0,1}; +} + +def C_LHU : ZcLoad_ri<0b100, 0b00, "c.lhu", GPRC, uimm2_lsb0>, + Sched<[]> { +bits<2> imm; + +let Inst{12-10} = 0b001; +let Inst{6} = 0b0; +let Inst{5} = imm{1}; +} + +def C_LH : ZcLoad_ri<0b100, 0b00, "c.lh", GPRC, uimm2_lsb0>, + Sched<[]> { +bits<2> imm; + +let Inst{12-10} = 0b001; +let Inst{6} = 0b1; +let Inst{5} = imm{1}; +} + +def C_SB : ZcStore_ri<0b100, 0b00, "c.sb", GPRC, uimm2_zc>, + Sched<[]> { + bits<2> imm; + + let Inst{12-10} = 0b010; + let Inst{6-5} = imm{0,1}; +} + +def C_SH : ZcStore_ri<0b100, 0b00, "c.sh", GPRC, uimm2_lsb0>, + Sched<[]> { + bits<2> imm; + + let Inst{12-10} = 0b011; + let Inst{6} = 0b1; + let Inst{5} = imm{1}; +} +} diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -61,6 +61,7 @@ bool HasStdExtZbs = false; bool HasStdExtZbt = false; bool HasStdExtZca = false; + bool HasStdExtZcb = false; bool HasStdExtV = false; bool HasStdExtZve32x = false; bool HasStdExtZve32f = false; @@ -168,6 +169,7 @@ bool hasStdExtZvl() const { return ZvlLen != 0; } bool hasStdExtZvfh() const { return HasStdExtZvfh; } bool hasStdExtZca() const { return HasStdExtZca; } + bool hasStdExtZcb() const { return HasStdExtZcb; } bool hasStdExtZfhmin() const { return HasStdExtZfhmin; } bool hasStdExtZfh() const { return HasStdExtZfh; } bool hasStdExtZfinx() const { return HasStdExtZfinx; } diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -190,3 +190,6 @@ .attribute arch, "rv32izca0p70" # CHECK: attribute 5, "rv32i2p0_zca0p70" + +.attribute arch, "rv32izcb0p70" +# CHECK: attribute 5, "rv32i2p0_zcb0p70" diff --git a/llvm/test/MC/RISCV/rv32zcb-Invalid.s b/llvm/test/MC/RISCV/rv32zcb-Invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zcb-Invalid.s @@ -0,0 +1,17 @@ +# RUN: not llvm-mc -triple=riscv32 -mattr=experimental-zcb -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s + +# CHECK-ERROR: error: immediate must be an integer in the range [0, 3] +c.lbu a5, 10(a4) + +# CHECK-ERROR: error: immediate must be one of [0, 2] +c.lhu a5, 10(a4) + +# CHECK-ERROR: error: immediate must be one of [0, 2] +c.lh a5, 10(a4) + +# CHECK-ERROR: error: immediate must be an integer in the range [0, 3] +c.sb a5, 10(a4) + +# CHECK-ERROR: error: immediate must be one of [0, 2] +c.sh a5, 10(a4) diff --git a/llvm/test/MC/RISCV/rv32zcb-valid.s b/llvm/test/MC/RISCV/rv32zcb-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zcb-valid.s @@ -0,0 +1,25 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=experimental-zcb -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=experimental-zcb -mattr=m < %s \ +# RUN: | llvm-objdump --mattr=experimental-zcb --mattr=m -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: c.lbu a5, 2(a4) +# CHECK-ASM: encoding: [0x3c,0x83] +c.lbu a5, 2(a4) + +# CHECK-ASM-AND-OBJ: c.lhu a5, 2(a4) +# CHECK-ASM: encoding: [0x3c,0x87] +c.lhu a5, 2(a4) + +# CHECK-ASM-AND-OBJ: c.lh a5, 2(a4) +# CHECK-ASM: encoding: [0x7c,0x87] +c.lh a5, 2(a4) + +# CHECK-ASM-AND-OBJ: c.sb a5, 2(a4) +# CHECK-ASM: encoding: [0x3c,0x8b] +c.sb a5, 2(a4) + +# CHECK-ASM-AND-OBJ: c.sh a5, 2(a4) +# CHECK-ASM: encoding: [0x7c,0x8f] +c.sh a5, 2(a4) diff --git a/llvm/test/MC/RISCV/rv64zcb-Invalid.s b/llvm/test/MC/RISCV/rv64zcb-Invalid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zcb-Invalid.s @@ -0,0 +1,17 @@ +# RUN: not llvm-mc -triple=riscv64 -mattr=experimental-zcb -riscv-no-aliases -show-encoding < %s 2>&1 \ +# RUN: | FileCheck -check-prefixes=CHECK-ERROR %s + +# CHECK-ERROR: error: immediate must be an integer in the range [0, 3] +c.lbu a5, 10(a4) + +# CHECK-ERROR: error: immediate must be one of [0, 2] +c.lhu a5, 10(a4) + +# CHECK-ERROR: error: immediate must be one of [0, 2] +c.lh a5, 10(a4) + +# CHECK-ERROR: error: immediate must be an integer in the range [0, 3] +c.sb a5, 10(a4) + +# CHECK-ERROR: error: immediate must be one of [0, 2] +c.sh a5, 10(a4) diff --git a/llvm/test/MC/RISCV/rv64zcb-valid.s b/llvm/test/MC/RISCV/rv64zcb-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv64zcb-valid.s @@ -0,0 +1,53 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=experimental-zcb -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=experimental-zcb -mattr=m < %s \ +# RUN: | llvm-objdump --mattr=experimental-zcb --mattr=m -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefixes=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: c.zext.b s0 +# CHECK-ASM: encoding: [0x61,0x9c] +c.zext.b s0 + +# CHECK-ASM-AND-OBJ: c.sext.b s0 +# CHECK-ASM: encoding: [0x65,0x9c] +c.sext.b s0 + +# CHECK-ASM-AND-OBJ: c.zext.h s0 +# CHECK-ASM: encoding: [0x69,0x9c] +c.zext.h s0 + +# CHECK-ASM-AND-OBJ: c.sext.h s0 +# CHECK-ASM: encoding: [0x6d,0x9c] +c.sext.h s0 + +# CHECK-ASM-AND-OBJ: c.zext.w s0 +# CHECK-ASM: encoding: [0x71,0x9c] +c.zext.w s0 + +# CHECK-ASM-AND-OBJ: c.not s0 +# CHECK-ASM: encoding: [0x75,0x9c] +c.not s0 + +# CHECK-ASM-AND-OBJ: c.mul s0, s1 +# CHECK-ASM: encoding: [0x45,0x9c] +c.mul s0, s1 + +# CHECK-ASM-AND-OBJ: c.lbu a5, 2(a4) +# CHECK-ASM: encoding: [0x3c,0x83] +c.lbu a5, 2(a4) + +# CHECK-ASM-AND-OBJ: c.lhu a5, 2(a4) +# CHECK-ASM: encoding: [0x3c,0x87] +c.lhu a5, 2(a4) + +# CHECK-ASM-AND-OBJ: c.lh a5, 2(a4) +# CHECK-ASM: encoding: [0x7c,0x87] +c.lh a5, 2(a4) + +# CHECK-ASM-AND-OBJ: c.sb a5, 2(a4) +# CHECK-ASM: encoding: [0x3c,0x8b] +c.sb a5, 2(a4) + +# CHECK-ASM-AND-OBJ: c.sh a5, 2(a4) +# CHECK-ASM: encoding: [0x7c,0x8f] +c.sh a5, 2(a4)