diff --git a/llvm/test/CodeGen/RISCV/analyze-branch.ll b/llvm/test/CodeGen/RISCV/analyze-branch.ll
--- a/llvm/test/CodeGen/RISCV/analyze-branch.ll
+++ b/llvm/test/CodeGen/RISCV/analyze-branch.ll
@@ -12,8 +12,8 @@
 !0 = !{!"branch_weights", i32 64, i32 4}
 !1 = !{!"branch_weights", i32 4, i32 64}
 
-define void @test_bcc_fallthrough_taken(i32 %in) nounwind {
-; RV32I-LABEL: test_bcc_fallthrough_taken:
+define void @test_beq_fallthrough_taken(i32 %in) nounwind {
+; RV32I-LABEL: test_beq_fallthrough_taken:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
@@ -44,8 +44,8 @@
   ret void
 }
 
-define void @test_bcc_fallthrough_nottaken(i32 %in) nounwind {
-; RV32I-LABEL: test_bcc_fallthrough_nottaken:
+define void @test_beq_fallthrough_nottaken(i32 %in) nounwind {
+; RV32I-LABEL: test_beq_fallthrough_nottaken:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
@@ -76,4 +76,60 @@
   ret void
 }
 
-; TODO: how can we expand the coverage of the branch analysis functions?
+define void @test_beqz_fallthrough_taken(i32 %in) nounwind {
+; RV32I-LABEL: test_beqz_fallthrough_taken:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    bnez a0, .LBB2_3
+; RV32I-NEXT:  # %bb.1: # %true
+; RV32I-NEXT:    call test_true@plt
+; RV32I-NEXT:  .LBB2_2: # %true
+; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB2_3: # %false
+; RV32I-NEXT:    call test_false@plt
+; RV32I-NEXT:    j .LBB2_2
+  %tst = icmp eq i32 %in, 0
+  br i1 %tst, label %true, label %false, !prof !0
+
+; Expected layout order is: Entry, TrueBlock, FalseBlock
+
+true:
+  call void @test_true()
+  ret void
+
+false:
+  call void @test_false()
+  ret void
+}
+
+define void @test_beqz_fallthrough_nottaken(i32 %in) nounwind {
+; RV32I-LABEL: test_beqz_fallthrough_nottaken:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi sp, sp, -16
+; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT:    beqz a0, .LBB3_3
+; RV32I-NEXT:  # %bb.1: # %false
+; RV32I-NEXT:    call test_false@plt
+; RV32I-NEXT:  .LBB3_2: # %true
+; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB3_3: # %true
+; RV32I-NEXT:    call test_true@plt
+; RV32I-NEXT:    j .LBB3_2
+  %tst = icmp eq i32 %in, 0
+  br i1 %tst, label %true, label %false, !prof !1
+
+; Expected layout order is: Entry, FalseBlock, TrueBlock
+
+true:
+  call void @test_true()
+  ret void
+
+false:
+  call void @test_false()
+  ret void
+}