Index: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -1683,6 +1683,8 @@
     { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i16, 4 },
     { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
 
+    // Complex: to v4f64
+    { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i32,  4 },
 
     // LowerVectorFP_TO_INT
     { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 },
Index: llvm/test/Analysis/CostModel/AArch64/cast.ll
===================================================================
--- llvm/test/Analysis/CostModel/AArch64/cast.ll
+++ llvm/test/Analysis/CostModel/AArch64/cast.ll
@@ -397,7 +397,7 @@
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 9 for instruction: %r204 = uitofp <4 x i16> undef to <4 x double>
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 9 for instruction: %r205 = sitofp <4 x i16> undef to <4 x double>
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %r206 = uitofp <4 x i32> undef to <4 x double>
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %r207 = sitofp <4 x i32> undef to <4 x double>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %r207 = sitofp <4 x i32> undef to <4 x double>
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %r208 = uitofp <4 x i64> undef to <4 x double>
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %r209 = sitofp <4 x i64> undef to <4 x double>
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %r210 = uitofp <8 x i1> undef to <8 x float>
Index: llvm/test/CodeGen/AArch64/complex-int-to-fp.ll
===================================================================
--- llvm/test/CodeGen/AArch64/complex-int-to-fp.ll
+++ llvm/test/CodeGen/AArch64/complex-int-to-fp.ll
@@ -162,3 +162,14 @@
   %conv = uitofp <4 x i8> %v to <4 x float>
   ret <4 x float> %conv
 }
+
+define <4 x double> @test_signed_v4i32_to_v4f64(<4 x i32> %v) nounwind readnone {
+; CHECK-LABEL: test_signed_v4i32_to_v4f64:
+; CHECK:    sshll2.2d v1, v0, #0
+; CHECK:    sshll.2d v0, v0, #0
+; CHECK:    scvtf.2d v1, v1
+; CHECK:    scvtf.2d v0, v0
+
+  %conv = sitofp <4 x i32> %v to <4 x double>
+  ret <4 x double> %conv
+}
\ No newline at end of file