diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1406,18 +1406,31 @@
     }
   }
 
-  // Convert X > -1 to X >= 0.
-  if (CC == ISD::SETGT && isAllOnesConstant(RHS)) {
-    RHS = DAG.getConstant(0, DL, RHS.getValueType());
-    CC = ISD::SETGE;
-    return;
-  }
-  // Convert X < 1 to 0 >= X.
-  if (CC == ISD::SETLT && isOneConstant(RHS)) {
-    RHS = LHS;
-    LHS = DAG.getConstant(0, DL, RHS.getValueType());
-    CC = ISD::SETGE;
-    return;
+  if (auto *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
+    int64_t C = RHSC->getSExtValue();
+    switch (CC) {
+    default: break;
+    case ISD::SETGT:
+      // Convert X > -1 to X >= 0.
+      // Convert X > -2049 to X >= -2048.
+      // Or X > C to C >= C+1 if it could use LUI.
+      if (C == -1 ||
+          (!isInt<12>(C) && isInt<12>(C + 1)) ||
+          (isInt<32>(C + 1) && (C & 0xfff) == 0xfff)) {
+        RHS = DAG.getConstant(C + 1, DL, RHS.getValueType());
+        CC = ISD::SETGE;
+        return;
+      }
+      break;
+    case ISD::SETLT:
+      if (C == 1) {
+        RHS = LHS;
+        LHS = DAG.getConstant(0, DL, RHS.getValueType());
+        CC = ISD::SETGE;
+        return;
+      }
+      break;
+    }
   }
 
   switch (CC) {
diff --git a/llvm/test/CodeGen/RISCV/rv32zbt.ll b/llvm/test/CodeGen/RISCV/rv32zbt.ll
--- a/llvm/test/CodeGen/RISCV/rv32zbt.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbt.ll
@@ -346,9 +346,8 @@
 define i32 @cmov_sgt_i32_constant_neg_2049(i32 %a, i32 %b, i32 %c) nounwind {
 ; RV32I-LABEL: cmov_sgt_i32_constant_neg_2049:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a3, 1048575
-; RV32I-NEXT:    addi a3, a3, 2047
-; RV32I-NEXT:    blt a3, a1, .LBB17_2
+; RV32I-NEXT:    li a3, -2048
+; RV32I-NEXT:    bge a1, a3, .LBB17_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB17_2:
@@ -406,9 +405,8 @@
 define i32 @cmov_sge_i32_constant_neg_2048(i32 %a, i32 %b, i32 %c) nounwind {
 ; RV32I-LABEL: cmov_sge_i32_constant_neg_2048:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    lui a3, 1048575
-; RV32I-NEXT:    addi a3, a3, 2047
-; RV32I-NEXT:    blt a3, a1, .LBB20_2
+; RV32I-NEXT:    li a3, -2048
+; RV32I-NEXT:    bge a1, a3, .LBB20_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a0, a2
 ; RV32I-NEXT:  .LBB20_2:
diff --git a/llvm/test/CodeGen/RISCV/rv64zbt.ll b/llvm/test/CodeGen/RISCV/rv64zbt.ll
--- a/llvm/test/CodeGen/RISCV/rv64zbt.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbt.ll
@@ -414,9 +414,8 @@
 define i64 @cmov_sgt_i64_constant_neg_2049(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV64I-LABEL: cmov_sgt_i64_constant_neg_2049:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a3, 1048575
-; RV64I-NEXT:    addiw a3, a3, 2047
-; RV64I-NEXT:    blt a3, a1, .LBB21_2
+; RV64I-NEXT:    li a3, -2048
+; RV64I-NEXT:    bge a1, a3, .LBB21_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:  .LBB21_2:
@@ -474,9 +473,8 @@
 define i64 @cmov_sge_i64_constant_neg_2048(i64 %a, i64 %b, i64 %c) nounwind {
 ; RV64I-LABEL: cmov_sge_i64_constant_neg_2048:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a3, 1048575
-; RV64I-NEXT:    addiw a3, a3, 2047
-; RV64I-NEXT:    blt a3, a1, .LBB24_2
+; RV64I-NEXT:    li a3, -2048
+; RV64I-NEXT:    bge a1, a3, .LBB24_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:  .LBB24_2:
diff --git a/llvm/test/CodeGen/RISCV/select-cc.ll b/llvm/test/CodeGen/RISCV/select-cc.ll
--- a/llvm/test/CodeGen/RISCV/select-cc.ll
+++ b/llvm/test/CodeGen/RISCV/select-cc.ll
@@ -417,8 +417,7 @@
 ; RV32I-LABEL: select_sge_int16min:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a3, 1048560
-; RV32I-NEXT:    addi a3, a3, -1
-; RV32I-NEXT:    blt a3, a0, .LBB2_2
+; RV32I-NEXT:    bge a0, a3, .LBB2_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a1, a2
 ; RV32I-NEXT:  .LBB2_2:
@@ -436,8 +435,7 @@
 ; RV64I-LABEL: select_sge_int16min:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a3, 1048560
-; RV64I-NEXT:    addiw a3, a3, -1
-; RV64I-NEXT:    blt a3, a0, .LBB2_2
+; RV64I-NEXT:    bge a0, a3, .LBB2_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a1, a2
 ; RV64I-NEXT:  .LBB2_2:
@@ -490,8 +488,7 @@
 ; RV64I-LABEL: select_sge_int32min:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a3, 524288
-; RV64I-NEXT:    addi a3, a3, -1
-; RV64I-NEXT:    blt a3, a0, .LBB3_2
+; RV64I-NEXT:    bge a0, a3, .LBB3_2
 ; RV64I-NEXT:  # %bb.1:
 ; RV64I-NEXT:    mv a1, a2
 ; RV64I-NEXT:  .LBB3_2: