diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h
--- a/llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -450,9 +450,9 @@
 
   /// X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating
   /// point type down to the precision of the destination VT.  TRUNC is a
-  /// flag, which is always an integer that is zero or one.  If TRUNC is 0,
-  /// this is a normal rounding, if it is 1, this FP_ROUND is known to not
-  /// change the value of Y.
+  /// flag, which is always an ISD::Constant integer that is zero or one.  If
+  /// TRUNC is 0, this is a normal rounding, if it is 1, this FP_ROUND is known
+  /// to not change the value of Y.
   ///
   /// The TRUNC = 1 case is used in cases where we know that the value will
   /// not be modified by the node, because Y is not using any of the extra
@@ -840,8 +840,8 @@
 
   /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type
   /// down to the precision of the destination VT.  TRUNC is a flag, which is
-  /// always an integer that is zero or one.  If TRUNC is 0, this is a
-  /// normal rounding, if it is 1, this FP_ROUND is known to not change the
+  /// always an ISD::Constant integer that is zero or one.  If TRUNC is 0, this
+  /// is a normal rounding, if it is 1, this FP_ROUND is known to not change the
   /// value of Y.
   ///
   /// The TRUNC = 1 case is used in cases where we know that the value will
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -3500,20 +3500,16 @@
   // restricted set of legal types, this split can chain to build things up.
 
   if (N->isStrictFPOpcode()) {
-    SDValue Res = DAG.getNode(
-        ISD::STRICT_FP_ROUND, DL, {OutVT, MVT::Other},
-        {Chain, InterVec,
-         DAG.getTargetConstant(0, DL, TLI.getPointerTy(DAG.getDataLayout()))});
+    SDValue Res = DAG.getNode(ISD::STRICT_FP_ROUND, DL, {OutVT, MVT::Other},
+                              {Chain, InterVec, DAG.getIntPtrConstant(0, DL)});
     // Relink the chain
     ReplaceValueWith(SDValue(N, 1), SDValue(Res.getNode(), 1));
     return Res;
   }
 
-  return IsFloat
-             ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
-                           DAG.getTargetConstant(
-                               0, DL, TLI.getPointerTy(DAG.getDataLayout())))
-             : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
+  return IsFloat ? DAG.getNode(ISD::FP_ROUND, DL, OutVT, InterVec,
+                               DAG.getIntPtrConstant(0, DL))
+                 : DAG.getNode(ISD::TRUNCATE, DL, OutVT, InterVec);
 }
 
 SDValue DAGTypeLegalizer::SplitVecOp_VSETCC(SDNode *N) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6041,10 +6041,10 @@
       return N1;
     break;
   case ISD::FP_ROUND:
-    assert(VT.isFloatingPoint() &&
-           N1.getValueType().isFloatingPoint() &&
-           VT.bitsLE(N1.getValueType()) &&
-           N2C && (N2C->getZExtValue() == 0 || N2C->getZExtValue() == 1) &&
+    assert(VT.isFloatingPoint() && N1.getValueType().isFloatingPoint() &&
+           VT.bitsLE(N1.getValueType()) && N2C &&
+           N2C->getOpcode() == ISD::Constant &&
+           (N2C->getZExtValue() == 0 || N2C->getZExtValue() == 1) &&
            "Invalid FP_ROUND!");
     if (N1.getValueType() == VT) return N1;  // noop conversion.
     break;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -280,9 +280,8 @@
   if (PartEVT.isFloatingPoint() && ValueVT.isFloatingPoint()) {
     // FP_ROUND's are always exact here.
     if (ValueVT.bitsLT(Val.getValueType()))
-      return DAG.getNode(
-          ISD::FP_ROUND, DL, ValueVT, Val,
-          DAG.getTargetConstant(1, DL, TLI.getPointerTy(DAG.getDataLayout())));
+      return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val,
+                         DAG.getIntPtrConstant(1, DL));
 
     return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val);
   }
@@ -3426,8 +3425,7 @@
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   EVT DestVT = TLI.getValueType(DAG.getDataLayout(), I.getType());
   setValue(&I, DAG.getNode(ISD::FP_ROUND, dl, DestVT, N,
-                           DAG.getTargetConstant(
-                               0, dl, TLI.getPointerTy(DAG.getDataLayout()))));
+                           DAG.getIntPtrConstant(0, dl)));
 }
 
 void SelectionDAGBuilder::visitFPExt(const User &I) {
@@ -6369,10 +6367,9 @@
     SelectionDAG::FlagInserter FlagsInserter(DAG, Flags);
 
     SDValue Result;
-    Result = DAG.getNode(
-        ISD::FPTRUNC_ROUND, sdl, VT, getValue(I.getArgOperand(0)),
-        DAG.getTargetConstant((int)*RoundMode, sdl,
-                              TLI.getPointerTy(DAG.getDataLayout())));
+    Result =
+        DAG.getNode(ISD::FPTRUNC_ROUND, sdl, VT, getValue(I.getArgOperand(0)),
+                    DAG.getIntPtrConstant((int)*RoundMode, sdl));
     setValue(&I, Result);
 
     return;
@@ -6402,8 +6399,7 @@
     setValue(&I, DAG.getNode(ISD::BITCAST, sdl, MVT::i16,
                              DAG.getNode(ISD::FP_ROUND, sdl, MVT::f16,
                                          getValue(I.getArgOperand(0)),
-                                         DAG.getTargetConstant(0, sdl,
-                                                               MVT::i32))));
+                                         DAG.getIntPtrConstant(0, sdl))));
     return;
   case Intrinsic::convert_from_fp16:
     setValue(&I, DAG.getNode(ISD::FP_EXTEND, sdl,
@@ -7343,8 +7339,7 @@
   switch (Opcode) {
   default: break;
   case ISD::STRICT_FP_ROUND:
-    Opers.push_back(
-        DAG.getTargetConstant(0, sdl, TLI.getPointerTy(DAG.getDataLayout())));
+    Opers.push_back(DAG.getIntPtrConstant(0, sdl));
     break;
   case ISD::STRICT_FSETCC:
   case ISD::STRICT_FSETCCS: {
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -20896,7 +20896,7 @@
         Store->getMemoryVT().getVectorElementType());
     MemVT = MemVT.changeTypeToInteger();
     NewValue = DAG.getNode(AArch64ISD::FP_ROUND_MERGE_PASSTHRU, DL, TruncVT, Pg,
-                           NewValue, DAG.getTargetConstant(0, DL, MVT::i64),
+                           NewValue, DAG.getIntPtrConstant(0, DL),
                            DAG.getUNDEF(TruncVT));
     NewValue =
         getSVESafeBitCast(ContainerVT.changeTypeToInteger(), NewValue, DAG);
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1980,7 +1980,7 @@
 
   // FP_ROUND has an additional 'precise' flag which indicates the type of rounding.
   // This is ignored by the pattern below where it is matched by (i64 timm0_1)
-  def : Pat<(nxv2f16 (AArch64fcvtr_mt (nxv2i1 (SVEAllActive):$Pg), (nxv2f32 ZPR:$Zs), (i64 timm0_1), (nxv2f16 ZPR:$Zd))),
+  def : Pat<(nxv2f16 (AArch64fcvtr_mt (nxv2i1 (SVEAllActive):$Pg), (nxv2f32 ZPR:$Zs), (i64 imm0_1), (nxv2f16 ZPR:$Zd))),
             (FCVT_ZPmZ_StoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>;
 
   // Signed integer -> Floating-point 
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -368,17 +368,17 @@
 }
 
 // Used to match FP_ROUND_MERGE_PASSTHRU, which has an additional flag for the
-// type of rounding. This is matched by timm0_1 in pattern below and ignored.
+// type of rounding. This is matched by imm0_1 in pattern below and ignored.
 class SVE_1_Op_Passthru_Round_Pat<ValueType vtd, SDPatternOperator op, ValueType pg,
                                   ValueType vts, Instruction inst>
-: Pat<(vtd (op pg:$Op1, vts:$Op2, (i64 timm0_1), vtd:$Op3)),
+: Pat<(vtd (op pg:$Op1, vts:$Op2, (i64 imm0_1), vtd:$Op3)),
       (inst $Op3, $Op1, $Op2)>;
 
 multiclass SVE_1_Op_PassthruUndef_Round_Pat<ValueType vtd, SDPatternOperator op, ValueType pg,
                                   ValueType vts, Instruction inst>{
-  def : Pat<(vtd (op pg:$Op1, vts:$Op2, (i64 timm0_1), (vtd undef))),
+  def : Pat<(vtd (op pg:$Op1, vts:$Op2, (i64 imm0_1), (vtd undef))),
             (inst (IMPLICIT_DEF), $Op1, $Op2)>;
-  def : Pat<(vtd (op (pg (SVEAllActive:$Op1)), vts:$Op2, (i64 timm0_1), vtd:$Op3)),
+  def : Pat<(vtd (op (pg (SVEAllActive:$Op1)), vts:$Op2, (i64 imm0_1), vtd:$Op3)),
             (inst $Op3, $Op1, $Op2)>;
 }
 
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -8926,7 +8926,7 @@
   SDValue RcpSrc1 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, CvtSrc1);
   SDValue Quot = DAG.getNode(ISD::FMUL, SL, MVT::f32, CvtSrc0, RcpSrc1);
 
-  SDValue FPRoundFlag = DAG.getTargetConstant(0, SL, MVT::i32);
+  SDValue FPRoundFlag = DAG.getIntPtrConstant(0, SL);
   SDValue BestQuot = DAG.getNode(ISD::FP_ROUND, SL, MVT::f16, Quot, FPRoundFlag);
 
   return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f16, BestQuot, Src1, Src0);
@@ -9340,7 +9340,7 @@
       // For the f16 case, fold to a cast to f32 and then cast back to f16.
       if (ScalarVT != MVT::f32) {
         Cvt = DAG.getNode(ISD::FP_ROUND, DL, VT, Cvt,
-                          DAG.getTargetConstant(0, DL, MVT::i32));
+                          DAG.getIntPtrConstant(0, DL));
       }
       return Cvt;
     }
diff --git a/llvm/test/CodeGen/AArch64/sve-fcopysign.ll b/llvm/test/CodeGen/AArch64/sve-fcopysign.ll
--- a/llvm/test/CodeGen/AArch64/sve-fcopysign.ll
+++ b/llvm/test/CodeGen/AArch64/sve-fcopysign.ll
@@ -209,4 +209,19 @@
 
 declare <vscale x 8 x half> @llvm.copysign.v8f16(<vscale x 8 x half> %a, <vscale x 8 x half> %b) #0
 
+;========== FCOPYSIGN_EXTEND_ROUND
+
+define <vscale x 4 x half> @test_copysign_nxv4f32_nxv4f16(<vscale x 4 x float> %a, <vscale x 4 x float> %b) #0 {
+  %t1 = call <vscale x 4 x float> @llvm.copysign.v4f32(<vscale x 4 x float> %a, <vscale x 4 x float> %b)
+  %t2 = fptrunc <vscale x 4 x float> %t1 to <vscale x 4 x half>
+  ret <vscale x 4 x half> %t2
+}
+
+define <vscale x 2 x float> @test_copysign_nxv2f64_nxv2f32(<vscale x 2 x double> %a, <vscale x 2 x double> %b) #0 {
+  %t1 = call <vscale x 2 x double> @llvm.copysign.v2f64(<vscale x 2 x double> %a, <vscale x 2 x double> %b)
+  %t2 = fptrunc <vscale x 2 x double> %t1 to <vscale x 2 x float>
+  ret <vscale x 2 x float> %t2
+}
+
+
 attributes #0 = { nounwind }