Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td =================================================================== --- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -886,22 +886,22 @@ def : LD1RQPat; // continuous load with reg+reg addressing. - defm LD1B : sve_mem_cld_ss<0b0000, "ld1b", Z_b, ZPR8, GPR64NoXZRshifted8>; - defm LD1B_H : sve_mem_cld_ss<0b0001, "ld1b", Z_h, ZPR16, GPR64NoXZRshifted8>; - defm LD1B_S : sve_mem_cld_ss<0b0010, "ld1b", Z_s, ZPR32, GPR64NoXZRshifted8>; - defm LD1B_D : sve_mem_cld_ss<0b0011, "ld1b", Z_d, ZPR64, GPR64NoXZRshifted8>; - defm LD1SW_D : sve_mem_cld_ss<0b0100, "ld1sw", Z_d, ZPR64, GPR64NoXZRshifted32>; - defm LD1H : sve_mem_cld_ss<0b0101, "ld1h", Z_h, ZPR16, GPR64NoXZRshifted16>; - defm LD1H_S : sve_mem_cld_ss<0b0110, "ld1h", Z_s, ZPR32, GPR64NoXZRshifted16>; - defm LD1H_D : sve_mem_cld_ss<0b0111, "ld1h", Z_d, ZPR64, GPR64NoXZRshifted16>; - defm LD1SH_D : sve_mem_cld_ss<0b1000, "ld1sh", Z_d, ZPR64, GPR64NoXZRshifted16>; - defm LD1SH_S : sve_mem_cld_ss<0b1001, "ld1sh", Z_s, ZPR32, GPR64NoXZRshifted16>; - defm LD1W : sve_mem_cld_ss<0b1010, "ld1w", Z_s, ZPR32, GPR64NoXZRshifted32>; - defm LD1W_D : sve_mem_cld_ss<0b1011, "ld1w", Z_d, ZPR64, GPR64NoXZRshifted32>; - defm LD1SB_D : sve_mem_cld_ss<0b1100, "ld1sb", Z_d, ZPR64, GPR64NoXZRshifted8>; - defm LD1SB_S : sve_mem_cld_ss<0b1101, "ld1sb", Z_s, ZPR32, GPR64NoXZRshifted8>; - defm LD1SB_H : sve_mem_cld_ss<0b1110, "ld1sb", Z_h, ZPR16, GPR64NoXZRshifted8>; - defm LD1D : sve_mem_cld_ss<0b1111, "ld1d", Z_d, ZPR64, GPR64NoXZRshifted64>; + defm LD1B : sve_mem_cld_ss<0b0000, "ld1b", Z_b, ZPR8, GPR64shifted8>; + defm LD1B_H : sve_mem_cld_ss<0b0001, "ld1b", Z_h, ZPR16, GPR64shifted8>; + defm LD1B_S : sve_mem_cld_ss<0b0010, "ld1b", Z_s, ZPR32, GPR64shifted8>; + defm LD1B_D : sve_mem_cld_ss<0b0011, "ld1b", Z_d, ZPR64, GPR64shifted8>; + defm LD1SW_D : sve_mem_cld_ss<0b0100, "ld1sw", Z_d, ZPR64, GPR64shifted32>; + defm LD1H : sve_mem_cld_ss<0b0101, "ld1h", Z_h, ZPR16, GPR64shifted16>; + defm LD1H_S : sve_mem_cld_ss<0b0110, "ld1h", Z_s, ZPR32, GPR64shifted16>; + defm LD1H_D : sve_mem_cld_ss<0b0111, "ld1h", Z_d, ZPR64, GPR64shifted16>; + defm LD1SH_D : sve_mem_cld_ss<0b1000, "ld1sh", Z_d, ZPR64, GPR64shifted16>; + defm LD1SH_S : sve_mem_cld_ss<0b1001, "ld1sh", Z_s, ZPR32, GPR64shifted16>; + defm LD1W : sve_mem_cld_ss<0b1010, "ld1w", Z_s, ZPR32, GPR64shifted32>; + defm LD1W_D : sve_mem_cld_ss<0b1011, "ld1w", Z_d, ZPR64, GPR64shifted32>; + defm LD1SB_D : sve_mem_cld_ss<0b1100, "ld1sb", Z_d, ZPR64, GPR64shifted8>; + defm LD1SB_S : sve_mem_cld_ss<0b1101, "ld1sb", Z_s, ZPR32, GPR64shifted8>; + defm LD1SB_H : sve_mem_cld_ss<0b1110, "ld1sb", Z_h, ZPR16, GPR64shifted8>; + defm LD1D : sve_mem_cld_ss<0b1111, "ld1d", Z_d, ZPR64, GPR64shifted64>; } // End HasSVEorSME let Predicates = [HasSVE] in { @@ -1198,16 +1198,16 @@ defm ST1D_IMM : sve_mem_cst_si<0b11, 0b11, "st1d", Z_d, ZPR64>; // contiguous store with reg+reg addressing. - defm ST1B : sve_mem_cst_ss<0b0000, "st1b", Z_b, ZPR8, GPR64NoXZRshifted8>; - defm ST1B_H : sve_mem_cst_ss<0b0001, "st1b", Z_h, ZPR16, GPR64NoXZRshifted8>; - defm ST1B_S : sve_mem_cst_ss<0b0010, "st1b", Z_s, ZPR32, GPR64NoXZRshifted8>; - defm ST1B_D : sve_mem_cst_ss<0b0011, "st1b", Z_d, ZPR64, GPR64NoXZRshifted8>; - defm ST1H : sve_mem_cst_ss<0b0101, "st1h", Z_h, ZPR16, GPR64NoXZRshifted16>; - defm ST1H_S : sve_mem_cst_ss<0b0110, "st1h", Z_s, ZPR32, GPR64NoXZRshifted16>; - defm ST1H_D : sve_mem_cst_ss<0b0111, "st1h", Z_d, ZPR64, GPR64NoXZRshifted16>; - defm ST1W : sve_mem_cst_ss<0b1010, "st1w", Z_s, ZPR32, GPR64NoXZRshifted32>; - defm ST1W_D : sve_mem_cst_ss<0b1011, "st1w", Z_d, ZPR64, GPR64NoXZRshifted32>; - defm ST1D : sve_mem_cst_ss<0b1111, "st1d", Z_d, ZPR64, GPR64NoXZRshifted64>; + defm ST1B : sve_mem_cst_ss<0b0000, "st1b", Z_b, ZPR8, GPR64shifted8>; + defm ST1B_H : sve_mem_cst_ss<0b0001, "st1b", Z_h, ZPR16, GPR64shifted8>; + defm ST1B_S : sve_mem_cst_ss<0b0010, "st1b", Z_s, ZPR32, GPR64shifted8>; + defm ST1B_D : sve_mem_cst_ss<0b0011, "st1b", Z_d, ZPR64, GPR64shifted8>; + defm ST1H : sve_mem_cst_ss<0b0101, "st1h", Z_h, ZPR16, GPR64shifted16>; + defm ST1H_S : sve_mem_cst_ss<0b0110, "st1h", Z_s, ZPR32, GPR64shifted16>; + defm ST1H_D : sve_mem_cst_ss<0b0111, "st1h", Z_d, ZPR64, GPR64shifted16>; + defm ST1W : sve_mem_cst_ss<0b1010, "st1w", Z_s, ZPR32, GPR64shifted32>; + defm ST1W_D : sve_mem_cst_ss<0b1011, "st1w", Z_d, ZPR64, GPR64shifted32>; + defm ST1D : sve_mem_cst_ss<0b1111, "st1d", Z_d, ZPR64, GPR64shifted64>; } // End HasSVEorSME let Predicates = [HasSVE] in { Index: llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s =================================================================== --- llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s +++ llvm/test/MC/AArch64/SVE/ld1b-diagnostics.s @@ -90,23 +90,18 @@ // --------------------------------------------------------------------------// // Invalid scalar + scalar addressing modes -ld1b z0.b, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift -// CHECK-NEXT: ld1b z0.b, p0/z, [x0, xzr] -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - ld1b z0.b, p0/z, [x0, x0, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift // CHECK-NEXT: ld1b z0.b, p0/z, [x0, x0, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.b, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift // CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1b z0.b, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift // CHECK-NEXT: ld1b z0.b, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE/ld1b.s =================================================================== --- llvm/test/MC/AArch64/SVE/ld1b.s +++ llvm/test/MC/AArch64/SVE/ld1b.s @@ -140,3 +140,27 @@ // CHECK-ENCODING: [0xb7,0x4d,0x68,0xa4] // CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 4d 68 a4 + +ld1b { z0.b }, p0/z, [x0, xzr] +// CHECK-INST: ld1b { z0.b }, p0/z, [x0, xzr] +// CHECK-ENCODING: [0x00,0x40,0x1f,0xa4] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 1f a4 + +ld1b { z0.h }, p0/z, [x0, xzr] +// CHECK-INST: ld1b { z0.h }, p0/z, [x0, xzr] +// CHECK-ENCODING: [0x00,0x40,0x3f,0xa4] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 3f a4 + +ld1b { z0.s }, p0/z, [x0, xzr] +// CHECK-INST: ld1b { z0.s }, p0/z, [x0, xzr] +// CHECK-ENCODING: [0x00,0x40,0x5f,0xa4] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 5f a4 + +ld1b { z0.d }, p0/z, [x0, xzr] +// CHECK-INST: ld1b { z0.d }, p0/z, [x0, xzr] +// CHECK-ENCODING: [0x00,0x40,0x7f,0xa4] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 7f a4 Index: llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s =================================================================== --- llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s +++ llvm/test/MC/AArch64/SVE/ld1d-diagnostics.s @@ -46,27 +46,22 @@ // Invalid scalar + scalar addressing modes ld1d z0.d, p0/z, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: -ld1d z0.d, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' -// CHECK-NEXT: ld1d z0.d, p0/z, [x0, xzr] -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - ld1d z0.d, p0/z, [x0, x0, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, x0, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1d z0.d, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1d z0.d, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' // CHECK-NEXT: ld1d z0.d, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE/ld1d.s =================================================================== --- llvm/test/MC/AArch64/SVE/ld1d.s +++ llvm/test/MC/AArch64/SVE/ld1d.s @@ -44,3 +44,9 @@ // CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa5] // CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 4d e8 a5 + +ld1d { z0.d }, p0/z, [x0, xzr, lsl #3] +// CHECK-INST: ld1d { z0.d }, p0/z, [x0, xzr, lsl #3] +// CHECK-ENCODING: [0x00,0x40,0xff,0xa5] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 ff a5 Index: llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s =================================================================== --- llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s +++ llvm/test/MC/AArch64/SVE/ld1h-diagnostics.s @@ -76,27 +76,22 @@ // Invalid scalar + scalar addressing modes ld1h z0.h, p0/z, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: -ld1h z0.h, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' -// CHECK-NEXT: ld1h z0.h, p0/z, [x0, xzr] -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - ld1h z0.h, p0/z, [x0, x0, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK-NEXT: ld1h z0.h, p0/z, [x0, x0, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.h, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1h z0.h, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK-NEXT: ld1h z0.h, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE/ld1h.s =================================================================== --- llvm/test/MC/AArch64/SVE/ld1h.s +++ llvm/test/MC/AArch64/SVE/ld1h.s @@ -104,3 +104,21 @@ // CHECK-ENCODING: [0xb7,0x4d,0xe8,0xa4] // CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 4d e8 a4 + +ld1h { z0.h }, p0/z, [x0, xzr, lsl #1] +// CHECK-INST: ld1h { z0.h }, p0/z, [x0, xzr, lsl #1] +// CHECK-ENCODING: [0x00,0x40,0xbf,0xa4] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 bf a4 + +ld1h { z0.s }, p0/z, [x0, xzr, lsl #1] +// CHECK-INST: ld1h { z0.s }, p0/z, [x0, xzr, lsl #1] +// CHECK-ENCODING: [0x00,0x40,0xdf,0xa4] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 df a4 + +ld1h { z0.d }, p0/z, [x0, xzr, lsl #1] +// CHECK-INST: ld1h { z0.d }, p0/z, [x0, xzr, lsl #1] +// CHECK-ENCODING: [0x00,0x40,0xff,0xa4] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 ff a4 Index: llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s =================================================================== --- llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s +++ llvm/test/MC/AArch64/SVE/ld1sb-diagnostics.s @@ -89,23 +89,18 @@ // --------------------------------------------------------------------------// // Invalid scalar + scalar addressing modes -ld1sb z0.h, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift -// CHECK-NEXT: ld1sb z0.h, p0/z, [x0, xzr] -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - ld1sb z0.h, p0/z, [x0, x0, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, x0, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.h, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sb z0.h, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift // CHECK-NEXT: ld1sb z0.h, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE/ld1sb.s =================================================================== --- llvm/test/MC/AArch64/SVE/ld1sb.s +++ llvm/test/MC/AArch64/SVE/ld1sb.s @@ -110,3 +110,21 @@ // CHECK-ENCODING: [0xb7,0x4d,0x88,0xa5] // CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 4d 88 a5 + +ld1sb { z0.h }, p0/z, [x0, xzr] +// CHECK-INST: ld1sb { z0.h }, p0/z, [x0, xzr] +// CHECK-ENCODING: [0x00,0x40,0xdf,0xa5] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 df a5 + +ld1sb { z0.s }, p0/z, [x0, xzr] +// CHECK-INST: ld1sb { z0.s }, p0/z, [x0, xzr] +// CHECK-ENCODING: [0x00,0x40,0xbf,0xa5] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 bf a5 + +ld1sb { z0.d }, p0/z, [x0, xzr] +// CHECK-INST: ld1sb { z0.d }, p0/z, [x0, xzr] +// CHECK-ENCODING: [0x00,0x40,0x9f,0xa5] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 9f a5 Index: llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s =================================================================== --- llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s +++ llvm/test/MC/AArch64/SVE/ld1sh-diagnostics.s @@ -75,27 +75,22 @@ // Invalid scalar + scalar addressing modes ld1sh z0.s, p0/z, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: -ld1sh z0.s, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' -// CHECK-NEXT: ld1sh z0.s, p0/z, [x0, xzr] -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - ld1sh z0.s, p0/z, [x0, x0, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, x0, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.s, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sh z0.s, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK-NEXT: ld1sh z0.s, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE/ld1sh.s =================================================================== --- llvm/test/MC/AArch64/SVE/ld1sh.s +++ llvm/test/MC/AArch64/SVE/ld1sh.s @@ -74,3 +74,15 @@ // CHECK-ENCODING: [0xb7,0x4d,0x08,0xa5] // CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 4d 08 a5 + +ld1sh { z0.s }, p0/z, [x0, xzr, lsl #1] +// CHECK-INST: ld1sh { z0.s }, p0/z, [x0, xzr, lsl #1] +// CHECK-ENCODING: [0x00,0x40,0x3f,0xa5] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 3f a5 + +ld1sh { z0.d }, p0/z, [x0, xzr, lsl #1] +// CHECK-INST: ld1sh { z0.d }, p0/z, [x0, xzr, lsl #1] +// CHECK-ENCODING: [0x00,0x40,0x1f,0xa5] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 1f a5 Index: llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s =================================================================== --- llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s +++ llvm/test/MC/AArch64/SVE/ld1sw-diagnostics.s @@ -60,27 +60,22 @@ // Invalid scalar + scalar addressing modes ld1sw z0.d, p0/z, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: -ld1sw z0.d, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' -// CHECK-NEXT: ld1sw z0.d, p0/z, [x0, xzr] -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - ld1sw z0.d, p0/z, [x0, x0, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, x0, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1sw z0.d, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: ld1sw z0.d, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE/ld1sw.s =================================================================== --- llvm/test/MC/AArch64/SVE/ld1sw.s +++ llvm/test/MC/AArch64/SVE/ld1sw.s @@ -44,3 +44,9 @@ // CHECK-ENCODING: [0xb7,0x4d,0x88,0xa4] // CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 4d 88 a4 + +ld1sw { z0.d }, p0/z, [x0, xzr, lsl #2] +// CHECK-INST: ld1sw { z0.d }, p0/z, [x0, xzr, lsl #2] +// CHECK-ENCODING: [0x00,0x40,0x9f,0xa4] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 9f a4 Index: llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s =================================================================== --- llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s +++ llvm/test/MC/AArch64/SVE/ld1w-diagnostics.s @@ -61,27 +61,22 @@ // Invalid scalar + scalar addressing modes ld1w z0.s, p0/z, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: -ld1w z0.s, p0/z, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' -// CHECK-NEXT: ld1w z0.s, p0/z, [x0, xzr] -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - ld1w z0.s, p0/z, [x0, x0, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, x0, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.s, p0/z, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: ld1w z0.s, p0/z, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: ld1w z0.s, p0/z, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE/ld1w.s =================================================================== --- llvm/test/MC/AArch64/SVE/ld1w.s +++ llvm/test/MC/AArch64/SVE/ld1w.s @@ -74,3 +74,15 @@ // CHECK-ENCODING: [0xb7,0x4d,0x68,0xa5] // CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: b7 4d 68 a5 + +ld1w { z0.s }, p0/z, [x0, xzr, lsl #2] +// CHECK-INST: ld1w { z0.s }, p0/z, [x0, xzr, lsl #2] +// CHECK-ENCODING: [0x00,0x40,0x5f,0xa5] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 5f a5 + +ld1w { z0.d }, p0/z, [x0, xzr, lsl #2] +// CHECK-INST: ld1w { z0.d }, p0/z, [x0, xzr, lsl #2] +// CHECK-ENCODING: [0x00,0x40,0x7f,0xa5] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 7f a5 Index: llvm/test/MC/AArch64/SVE/st1b-diagnostics.s =================================================================== --- llvm/test/MC/AArch64/SVE/st1b-diagnostics.s +++ llvm/test/MC/AArch64/SVE/st1b-diagnostics.s @@ -98,23 +98,18 @@ // --------------------------------------------------------------------------// // Invalid scalar + scalar addressing modes -st1b z0.b, p0, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift -// CHECK-NEXT: st1b z0.b, p0, [x0, xzr] -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - st1b z0.b, p0, [x0, x0, lsl #1] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift // CHECK-NEXT: st1b z0.b, p0, [x0, x0, lsl #1] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1b z0.b, p0, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift // CHECK-NEXT: st1b z0.b, p0, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1b z0.b, p0, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 without shift +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, without shift // CHECK-NEXT: st1b z0.b, p0, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE/st1b.s =================================================================== --- llvm/test/MC/AArch64/SVE/st1b.s +++ llvm/test/MC/AArch64/SVE/st1b.s @@ -128,3 +128,27 @@ // CHECK-ENCODING: [0x00,0x40,0x60,0xe4] // CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 60 e4 + +st1b { z0.b }, p0, [x0, xzr] +// CHECK-INST: st1b { z0.b }, p0, [x0, xzr] +// CHECK-ENCODING: [0x00,0x40,0x1f,0xe4] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 1f e4 + +st1b { z0.h }, p0, [x0, xzr] +// CHECK-INST: st1b { z0.h }, p0, [x0, xzr] +// CHECK-ENCODING: [0x00,0x40,0x3f,0xe4] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 3f e4 + +st1b { z0.s }, p0, [x0, xzr] +// CHECK-INST: st1b { z0.s }, p0, [x0, xzr] +// CHECK-ENCODING: [0x00,0x40,0x5f,0xe4] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 5f e4 + +st1b { z0.d }, p0, [x0, xzr] +// CHECK-INST: st1b { z0.d }, p0, [x0, xzr] +// CHECK-ENCODING: [0x00,0x40,0x7f,0xe4] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 7f e4 Index: llvm/test/MC/AArch64/SVE/st1d-diagnostics.s =================================================================== --- llvm/test/MC/AArch64/SVE/st1d-diagnostics.s +++ llvm/test/MC/AArch64/SVE/st1d-diagnostics.s @@ -55,27 +55,22 @@ // Invalid scalar + scalar addressing modes st1d z0.d, p0, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' // CHECK-NEXT: st1d z0.d, p0, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: -st1d z0.d, p0, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' -// CHECK-NEXT: st1d z0.d, p0, [x0, xzr] -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - st1d z0.d, p0, [x0, x0, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' // CHECK-NEXT: st1d z0.d, p0, [x0, x0, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1d z0.d, p0, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' // CHECK-NEXT: st1d z0.d, p0, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1d z0.d, p0, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #3' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #3' // CHECK-NEXT: st1d z0.d, p0, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE/st1d.s =================================================================== --- llvm/test/MC/AArch64/SVE/st1d.s +++ llvm/test/MC/AArch64/SVE/st1d.s @@ -38,3 +38,9 @@ // CHECK-ENCODING: [0x00,0x40,0xe0,0xe5] // CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 e0 e5 + +st1d { z0.d }, p0, [x0, xzr, lsl #3] +// CHECK-INST: st1d { z0.d }, p0, [x0, xzr, lsl #3] +// CHECK-ENCODING: [0x00,0x40,0xff,0xe5] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 ff e5 Index: llvm/test/MC/AArch64/SVE/st1h-diagnostics.s =================================================================== --- llvm/test/MC/AArch64/SVE/st1h-diagnostics.s +++ llvm/test/MC/AArch64/SVE/st1h-diagnostics.s @@ -84,27 +84,22 @@ // Invalid scalar + scalar addressing modes st1h z0.h, p0, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK-NEXT: st1h z0.h, p0, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: -st1h z0.h, p0, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' -// CHECK-NEXT: st1h z0.h, p0, [x0, xzr] -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - st1h z0.h, p0, [x0, x0, lsl #2] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK-NEXT: st1h z0.h, p0, [x0, x0, lsl #2] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1h z0.h, p0, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK-NEXT: st1h z0.h, p0, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1h z0.h, p0, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #1' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #1' // CHECK-NEXT: st1h z0.h, p0, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE/st1h.s =================================================================== --- llvm/test/MC/AArch64/SVE/st1h.s +++ llvm/test/MC/AArch64/SVE/st1h.s @@ -98,3 +98,21 @@ // CHECK-ENCODING: [0x00,0x40,0xe0,0xe4] // CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 e0 e4 + +st1h { z0.h }, p0, [x0, xzr, lsl #1] +// CHECK-INST: st1h { z0.h }, p0, [x0, xzr, lsl #1] +// CHECK-ENCODING: [0x00,0x40,0xbf,0xe4] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 bf e4 + +st1h { z0.s }, p0, [x0, xzr, lsl #1] +// CHECK-INST: st1h { z0.s }, p0, [x0, xzr, lsl #1] +// CHECK-ENCODING: [0x00,0x40,0xdf,0xe4] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 df e4 + +st1h { z0.d }, p0, [x0, xzr, lsl #1] +// CHECK-INST: st1h { z0.d }, p0, [x0, xzr, lsl #1] +// CHECK-ENCODING: [0x00,0x40,0xff,0xe4] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 ff e4 Index: llvm/test/MC/AArch64/SVE/st1w-diagnostics.s =================================================================== --- llvm/test/MC/AArch64/SVE/st1w-diagnostics.s +++ llvm/test/MC/AArch64/SVE/st1w-diagnostics.s @@ -72,27 +72,22 @@ // Invalid scalar + scalar addressing modes st1w z0.s, p0, [x0, x0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: st1w z0.s, p0, [x0, x0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: -st1w z0.s, p0, [x0, xzr] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' -// CHECK-NEXT: st1w z0.s, p0, [x0, xzr] -// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: - st1w z0.s, p0, [x0, x0, lsl #3] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: st1w z0.s, p0, [x0, x0, lsl #3] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1w z0.s, p0, [x0, w0] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: st1w z0.s, p0, [x0, w0] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: st1w z0.s, p0, [x0, w0, uxtw] -// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 with required shift 'lsl #2' +// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: register must be x0..x30 or xzr, with required shift 'lsl #2' // CHECK-NEXT: st1w z0.s, p0, [x0, w0, uxtw] // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: Index: llvm/test/MC/AArch64/SVE/st1w.s =================================================================== --- llvm/test/MC/AArch64/SVE/st1w.s +++ llvm/test/MC/AArch64/SVE/st1w.s @@ -68,3 +68,15 @@ // CHECK-ENCODING: [0x00,0x40,0x60,0xe5] // CHECK-ERROR: instruction requires: sve or sme // CHECK-UNKNOWN: 00 40 60 e5 + +st1w { z0.s }, p0, [x0, xzr, lsl #2] +// CHECK-INST: st1w { z0.s }, p0, [x0, xzr, lsl #2] +// CHECK-ENCODING: [0x00,0x40,0x5f,0xe5] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 5f e5 + +st1w { z0.d }, p0, [x0, xzr, lsl #2] +// CHECK-INST: st1w { z0.d }, p0, [x0, xzr, lsl #2] +// CHECK-ENCODING: [0x00,0x40,0x7f,0xe5] +// CHECK-ERROR: instruction requires: sve or sme +// CHECK-UNKNOWN: 00 40 7f e5