diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -7316,8 +7316,7 @@
     if (ConstantSDNode *NegC = isConstOrConstSplat(Neg.getOperand(1))) {
       KnownBits Known = DAG.computeKnownBits(Neg.getOperand(0));
       unsigned Bits = Log2_64(EltSize);
-      if (NegC->getAPIntValue().getActiveBits() <= Bits &&
-          ((NegC->getAPIntValue() | Known.Zero).countTrailingOnes() >= Bits)) {
+      if ((NegC->getAPIntValue() | Known.Zero).countTrailingOnes() >= Bits) {
         Neg = Neg.getOperand(0);
         MaskLoBits = Bits;
       }
@@ -7337,9 +7336,8 @@
   if (MaskLoBits && Pos.getOpcode() == ISD::AND) {
     if (ConstantSDNode *PosC = isConstOrConstSplat(Pos.getOperand(1))) {
       KnownBits Known = DAG.computeKnownBits(Pos.getOperand(0));
-      if (PosC->getAPIntValue().getActiveBits() <= MaskLoBits &&
-          ((PosC->getAPIntValue() | Known.Zero).countTrailingOnes() >=
-           MaskLoBits))
+      if ((PosC->getAPIntValue() | Known.Zero).countTrailingOnes() >=
+          MaskLoBits)
         Pos = Pos.getOperand(0);
     }
   }
diff --git a/llvm/test/CodeGen/RISCV/rotl-rotr.ll b/llvm/test/CodeGen/RISCV/rotl-rotr.ll
--- a/llvm/test/CodeGen/RISCV/rotl-rotr.ll
+++ b/llvm/test/CodeGen/RISCV/rotl-rotr.ll
@@ -341,18 +341,12 @@
 ;
 ; RV32ZBB-LABEL: rotl_32_mask_1:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    sll a2, a0, a1
-; RV32ZBB-NEXT:    neg a1, a1
-; RV32ZBB-NEXT:    srl a0, a0, a1
-; RV32ZBB-NEXT:    or a0, a2, a0
+; RV32ZBB-NEXT:    rol a0, a0, a1
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotl_32_mask_1:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    sllw a2, a0, a1
-; RV64ZBB-NEXT:    negw a1, a1
-; RV64ZBB-NEXT:    srlw a0, a0, a1
-; RV64ZBB-NEXT:    or a0, a2, a0
+; RV64ZBB-NEXT:    rolw a0, a0, a1
 ; RV64ZBB-NEXT:    ret
   %a = and i32 %y, 63
   %b = shl i32 %x, %a
@@ -416,18 +410,12 @@
 ;
 ; RV32ZBB-LABEL: rotr_32_mask_1:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    srl a2, a0, a1
-; RV32ZBB-NEXT:    neg a1, a1
-; RV32ZBB-NEXT:    sll a0, a0, a1
-; RV32ZBB-NEXT:    or a0, a2, a0
+; RV32ZBB-NEXT:    ror a0, a0, a1
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotr_32_mask_1:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    srlw a2, a0, a1
-; RV64ZBB-NEXT:    negw a1, a1
-; RV64ZBB-NEXT:    sllw a0, a0, a1
-; RV64ZBB-NEXT:    or a0, a2, a0
+; RV64ZBB-NEXT:    rorw a0, a0, a1
 ; RV64ZBB-NEXT:    ret
   %a = and i32 %y, 63
   %b = lshr i32 %x, %a