Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -9671,6 +9671,20 @@ return XLen - EltBits + 1; break; } + case ISD::INTRINSIC_W_CHAIN: { + unsigned IntNo = Op.getConstantOperandVal(1); + switch (IntNo) { + default: + break; + case Intrinsic::riscv_masked_cmpxchg_i64: + // The output of the intrinsic is generated by performing an LR_W and + // ANDing the result with a mask. Therefore, the sign bits are the + // minimum of 33 (from the LR_W) and the number of sign bits in the mask + // operand. + unsigned Tmp = DAG.ComputeNumSignBits(Op.getOperand(5), Depth + 1); + return std::min(33u, Tmp); + } + } } return 1; Index: llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll =================================================================== --- llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll +++ llvm/test/CodeGen/RISCV/atomic-cmpxchg-branch-on-result.ll @@ -130,7 +130,6 @@ ; RV64IA-NEXT: .LBB2_5: # %do_cmpxchg ; RV64IA-NEXT: # in Loop: Header=BB2_1 Depth=1 ; RV64IA-NEXT: and a4, a4, a0 -; RV64IA-NEXT: sext.w a4, a4 ; RV64IA-NEXT: bne a1, a4, .LBB2_1 ; RV64IA-NEXT: # %bb.2: # %exit ; RV64IA-NEXT: ret @@ -207,7 +206,6 @@ ; RV64IA-NEXT: .LBB3_5: # %do_cmpxchg ; RV64IA-NEXT: # in Loop: Header=BB3_1 Depth=1 ; RV64IA-NEXT: and a4, a4, a0 -; RV64IA-NEXT: sext.w a4, a4 ; RV64IA-NEXT: beq a1, a4, .LBB3_1 ; RV64IA-NEXT: # %bb.2: # %exit ; RV64IA-NEXT: ret Index: llvm/test/CodeGen/RISCV/atomic-signext.ll =================================================================== --- llvm/test/CodeGen/RISCV/atomic-signext.ll +++ llvm/test/CodeGen/RISCV/atomic-signext.ll @@ -3904,7 +3904,6 @@ ; RV64IA-NEXT: bnez a5, .LBB48_1 ; RV64IA-NEXT: .LBB48_3: ; RV64IA-NEXT: and a0, a2, a4 -; RV64IA-NEXT: sext.w a0, a0 ; RV64IA-NEXT: xor a0, a1, a0 ; RV64IA-NEXT: seqz a0, a0 ; RV64IA-NEXT: ret @@ -4077,7 +4076,6 @@ ; RV64IA-NEXT: bnez a4, .LBB50_1 ; RV64IA-NEXT: .LBB50_3: ; RV64IA-NEXT: and a0, a2, a5 -; RV64IA-NEXT: sext.w a0, a0 ; RV64IA-NEXT: xor a0, a1, a0 ; RV64IA-NEXT: seqz a0, a0 ; RV64IA-NEXT: ret