diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1569,7 +1569,7 @@
 /// RV64 patterns
 
 let Predicates = [IsRV64, NotHasStdExtZba] in {
-def : Pat<(i64 (and GPR:$rs1, 0xffffffff)), (SRLI (SLLI GPR:$rs1, 32), 32)>;
+def : Pat<(i64 (and GPR:$rs1, 0xffffffff)), (ADDIW GPR:$rs1, 0)>;
 
 // If we're shifting a 32-bit zero extended value left by 0-31 bits, use 2
 // shifts instead of 3. This can occur when unsigned is used to index an array.
diff --git a/llvm/test/CodeGen/RISCV/aext-to-sext.ll b/llvm/test/CodeGen/RISCV/aext-to-sext.ll
--- a/llvm/test/CodeGen/RISCV/aext-to-sext.ll
+++ b/llvm/test/CodeGen/RISCV/aext-to-sext.ll
@@ -81,13 +81,13 @@
 define i64 @sext_phi_constants(i32 signext %c) {
 ; RV64I-LABEL: sext_phi_constants:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, -1
-; RV64I-NEXT:    bnez a0, .LBB2_2
-; RV64I-NEXT:  # %bb.1: # %iffalse
-; RV64I-NEXT:    li a1, -2
-; RV64I-NEXT:  .LBB2_2: # %merge
-; RV64I-NEXT:    slli a0, a1, 32
-; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    mv a1, a0
+; RV64I-NEXT:    li a0, -1
+; RV64I-NEXT:    beqz a1, .LBB2_2
+; RV64I-NEXT:  # %bb.1: # %merge
+; RV64I-NEXT:    ret
+; RV64I-NEXT:  .LBB2_2: # %iffalse
+; RV64I-NEXT:    li a0, -2
 ; RV64I-NEXT:    ret
   %a = icmp ne i32 %c, 0
   br i1 %a, label %iftrue, label %iffalse
diff --git a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
--- a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
@@ -2655,8 +2655,7 @@
 ;
 ; RV64NOZBB-LABEL: test_parity_i32:
 ; RV64NOZBB:       # %bb.0:
-; RV64NOZBB-NEXT:    slli a1, a0, 32
-; RV64NOZBB-NEXT:    srli a1, a1, 32
+; RV64NOZBB-NEXT:    sext.w a1, a0
 ; RV64NOZBB-NEXT:    srliw a0, a0, 16
 ; RV64NOZBB-NEXT:    xor a0, a1, a0
 ; RV64NOZBB-NEXT:    srli a1, a0, 8
diff --git a/llvm/test/CodeGen/RISCV/div.ll b/llvm/test/CodeGen/RISCV/div.ll
--- a/llvm/test/CodeGen/RISCV/div.ll
+++ b/llvm/test/CodeGen/RISCV/div.ll
@@ -27,10 +27,8 @@
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 32
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    sext.w a1, a1
 ; RV64I-NEXT:    call __udivdi3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
@@ -67,8 +65,7 @@
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    li a1, 5
 ; RV64I-NEXT:    call __udivdi3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
@@ -134,8 +131,7 @@
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a1, a0, 32
+; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    li a0, 10
 ; RV64I-NEXT:    call __udivdi3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/frame-info.ll b/llvm/test/CodeGen/RISCV/frame-info.ll
--- a/llvm/test/CodeGen/RISCV/frame-info.ll
+++ b/llvm/test/CodeGen/RISCV/frame-info.ll
@@ -81,8 +81,7 @@
 ; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 16
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
-; RV64-NEXT:    slli a0, a0, 32
-; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    addi a0, a0, 15
 ; RV64-NEXT:    andi a0, a0, -16
 ; RV64-NEXT:    sub a0, sp, a0
@@ -125,8 +124,7 @@
 ; RV64-WITHFP-NEXT:    .cfi_offset s0, -16
 ; RV64-WITHFP-NEXT:    addi s0, sp, 16
 ; RV64-WITHFP-NEXT:    .cfi_def_cfa s0, 0
-; RV64-WITHFP-NEXT:    slli a0, a0, 32
-; RV64-WITHFP-NEXT:    srli a0, a0, 32
+; RV64-WITHFP-NEXT:    sext.w a0, a0
 ; RV64-WITHFP-NEXT:    addi a0, a0, 15
 ; RV64-WITHFP-NEXT:    andi a0, a0, -16
 ; RV64-WITHFP-NEXT:    sub a0, sp, a0
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -2046,8 +2046,7 @@
 ; RV64I-NEXT:    slli a0, a0, 48
 ; RV64I-NEXT:    srli a0, a0, 48
 ; RV64I-NEXT:    call __extendhfsf2@plt
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    call __extendsfdf2@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
diff --git a/llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll b/llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
--- a/llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
+++ b/llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
@@ -63,9 +63,7 @@
 ; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64-NEXT:    mulw a5, a2, a0
 ; RV64-NEXT:    addw a5, a5, a1
-; RV64-NEXT:    slli a6, a5, 32
-; RV64-NEXT:    srli a6, a6, 32
-; RV64-NEXT:    add a6, a3, a6
+; RV64-NEXT:    add a6, a3, a5
 ; RV64-NEXT:    sb zero, 0(a6)
 ; RV64-NEXT:    addw a5, a5, a0
 ; RV64-NEXT:    addiw a2, a2, 1
diff --git a/llvm/test/CodeGen/RISCV/mul.ll b/llvm/test/CodeGen/RISCV/mul.ll
--- a/llvm/test/CodeGen/RISCV/mul.ll
+++ b/llvm/test/CodeGen/RISCV/mul.ll
@@ -405,8 +405,7 @@
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    sext.w a1, a1
 ; RV64I-NEXT:    call __muldi3@plt
 ; RV64I-NEXT:    srli a0, a0, 32
@@ -416,8 +415,7 @@
 ;
 ; RV64IM-LABEL: mulhsu:
 ; RV64IM:       # %bb.0:
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
+; RV64IM-NEXT:    sext.w a0, a0
 ; RV64IM-NEXT:    sext.w a1, a1
 ; RV64IM-NEXT:    mul a0, a0, a1
 ; RV64IM-NEXT:    srli a0, a0, 32
@@ -448,8 +446,8 @@
 ;
 ; RV64I-LABEL: mulhu_constant:
 ; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a1, a0, 32
 ; RV64I-NEXT:    srli a0, a0, 30
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    srli a0, a0, 32
@@ -457,8 +455,8 @@
 ;
 ; RV64IM-LABEL: mulhu_constant:
 ; RV64IM:       # %bb.0:
+; RV64IM-NEXT:    sext.w a1, a0
 ; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a1, a0, 32
 ; RV64IM-NEXT:    srli a0, a0, 30
 ; RV64IM-NEXT:    add a0, a0, a1
 ; RV64IM-NEXT:    srli a0, a0, 32
diff --git a/llvm/test/CodeGen/RISCV/rem.ll b/llvm/test/CodeGen/RISCV/rem.ll
--- a/llvm/test/CodeGen/RISCV/rem.ll
+++ b/llvm/test/CodeGen/RISCV/rem.ll
@@ -27,10 +27,8 @@
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 32
+; RV64I-NEXT:    sext.w a0, a0
+; RV64I-NEXT:    sext.w a1, a1
 ; RV64I-NEXT:    call __umoddi3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
@@ -66,8 +64,7 @@
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a1, a0, 32
+; RV64I-NEXT:    sext.w a1, a0
 ; RV64I-NEXT:    li a0, 10
 ; RV64I-NEXT:    call __umoddi3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll b/llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
--- a/llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll
@@ -30,8 +30,6 @@
 ; RV64ID-LABEL: zext_fptosi:
 ; RV64ID:       # %bb.0:
 ; RV64ID-NEXT:    fcvt.w.d a0, fa0, rtz
-; RV64ID-NEXT:    slli a0, a0, 32
-; RV64ID-NEXT:    srli a0, a0, 32
 ; RV64ID-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
diff --git a/llvm/test/CodeGen/RISCV/rv64d-double-convert.ll b/llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
--- a/llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
+++ b/llvm/test/CodeGen/RISCV/rv64d-double-convert.ll
@@ -29,8 +29,6 @@
 ; RV64ID-LABEL: zext_fptosi:
 ; RV64ID:       # %bb.0:
 ; RV64ID-NEXT:    fcvt.w.d a0, fa0, rtz
-; RV64ID-NEXT:    slli a0, a0, 32
-; RV64ID-NEXT:    srli a0, a0, 32
 ; RV64ID-NEXT:    ret
   %1 = fptosi double %a to i32
   ret i32 %1
diff --git a/llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll b/llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
--- a/llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll
@@ -30,8 +30,6 @@
 ; RV64IF-LABEL: zext_fptosi:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT:    slli a0, a0, 32
-; RV64IF-NEXT:    srli a0, a0, 32
 ; RV64IF-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
diff --git a/llvm/test/CodeGen/RISCV/rv64f-float-convert.ll b/llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
--- a/llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
+++ b/llvm/test/CodeGen/RISCV/rv64f-float-convert.ll
@@ -29,8 +29,6 @@
 ; RV64IF-LABEL: zext_fptosi:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fcvt.w.s a0, fa0, rtz
-; RV64IF-NEXT:    slli a0, a0, 32
-; RV64IF-NEXT:    srli a0, a0, 32
 ; RV64IF-NEXT:    ret
   %1 = fptosi float %a to i32
   ret i32 %1
@@ -90,8 +88,6 @@
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fadd.s ft0, fa0, fa1
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
-; RV64IF-NEXT:    slli a0, a0, 32
-; RV64IF-NEXT:    srli a0, a0, 32
 ; RV64IF-NEXT:    ret
   %1 = fadd float %a, %b
   %2 = bitcast float %1 to i32
diff --git a/llvm/test/CodeGen/RISCV/rv64i-complex-float.ll b/llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
--- a/llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
@@ -21,8 +21,7 @@
 ; CHECK-NEXT:    mv a1, s1
 ; CHECK-NEXT:    call __addsf3@plt
 ; CHECK-NEXT:    slli a0, a0, 32
-; CHECK-NEXT:    slli a1, s2, 32
-; CHECK-NEXT:    srli a1, a1, 32
+; CHECK-NEXT:    sext.w a1, s2
 ; CHECK-NEXT:    or a0, a0, a1
 ; CHECK-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
diff --git a/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll b/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
--- a/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
@@ -181,8 +181,6 @@
 ; RV64I-LABEL: zext_addw_aext_aext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_addw_aext_aext:
@@ -198,8 +196,6 @@
 ; RV64I-LABEL: zext_addw_aext_sext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_addw_aext_sext:
@@ -215,8 +211,6 @@
 ; RV64I-LABEL: zext_addw_aext_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_addw_aext_zext:
@@ -232,8 +226,6 @@
 ; RV64I-LABEL: zext_addw_sext_aext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_addw_sext_aext:
@@ -249,8 +241,6 @@
 ; RV64I-LABEL: zext_addw_sext_sext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_addw_sext_sext:
@@ -266,8 +256,6 @@
 ; RV64I-LABEL: zext_addw_sext_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_addw_sext_zext:
@@ -283,8 +271,6 @@
 ; RV64I-LABEL: zext_addw_zext_aext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_addw_zext_aext:
@@ -300,8 +286,6 @@
 ; RV64I-LABEL: zext_addw_zext_sext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_addw_zext_sext:
@@ -317,8 +301,6 @@
 ; RV64I-LABEL: zext_addw_zext_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_addw_zext_zext:
@@ -502,8 +484,6 @@
 ; RV64I-LABEL: zext_subw_aext_aext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    subw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_subw_aext_aext:
@@ -519,8 +499,6 @@
 ; RV64I-LABEL: zext_subw_aext_sext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    subw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_subw_aext_sext:
@@ -536,8 +514,6 @@
 ; RV64I-LABEL: zext_subw_aext_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    subw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_subw_aext_zext:
@@ -553,8 +529,6 @@
 ; RV64I-LABEL: zext_subw_sext_aext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    subw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_subw_sext_aext:
@@ -570,8 +544,6 @@
 ; RV64I-LABEL: zext_subw_sext_sext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    subw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_subw_sext_sext:
@@ -587,8 +559,6 @@
 ; RV64I-LABEL: zext_subw_sext_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    subw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_subw_sext_zext:
@@ -604,8 +574,6 @@
 ; RV64I-LABEL: zext_subw_zext_aext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    subw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_subw_zext_aext:
@@ -621,8 +589,6 @@
 ; RV64I-LABEL: zext_subw_zext_sext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    subw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_subw_zext_sext:
@@ -638,8 +604,6 @@
 ; RV64I-LABEL: zext_subw_zext_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    subw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_subw_zext_zext:
@@ -821,8 +785,6 @@
 ; RV64I-LABEL: zext_sllw_aext_aext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sllw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sllw_aext_aext:
@@ -838,8 +800,6 @@
 ; RV64I-LABEL: zext_sllw_aext_sext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sllw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sllw_aext_sext:
@@ -855,8 +815,6 @@
 ; RV64I-LABEL: zext_sllw_aext_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sllw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sllw_aext_zext:
@@ -872,8 +830,6 @@
 ; RV64I-LABEL: zext_sllw_sext_aext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sllw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sllw_sext_aext:
@@ -889,8 +845,6 @@
 ; RV64I-LABEL: zext_sllw_sext_sext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sllw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sllw_sext_sext:
@@ -906,8 +860,6 @@
 ; RV64I-LABEL: zext_sllw_sext_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sllw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sllw_sext_zext:
@@ -923,8 +875,6 @@
 ; RV64I-LABEL: zext_sllw_zext_aext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sllw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sllw_zext_aext:
@@ -940,8 +890,6 @@
 ; RV64I-LABEL: zext_sllw_zext_sext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sllw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sllw_zext_sext:
@@ -957,8 +905,6 @@
 ; RV64I-LABEL: zext_sllw_zext_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sllw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sllw_zext_zext:
@@ -1136,8 +1082,6 @@
 ; RV64I-LABEL: zext_srlw_aext_aext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srlw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_srlw_aext_aext:
@@ -1153,8 +1097,6 @@
 ; RV64I-LABEL: zext_srlw_aext_sext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srlw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_srlw_aext_sext:
@@ -1170,8 +1112,6 @@
 ; RV64I-LABEL: zext_srlw_aext_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srlw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_srlw_aext_zext:
@@ -1187,8 +1127,6 @@
 ; RV64I-LABEL: zext_srlw_sext_aext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srlw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_srlw_sext_aext:
@@ -1204,8 +1142,6 @@
 ; RV64I-LABEL: zext_srlw_sext_sext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srlw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_srlw_sext_sext:
@@ -1221,8 +1157,6 @@
 ; RV64I-LABEL: zext_srlw_sext_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srlw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_srlw_sext_zext:
@@ -1238,8 +1172,6 @@
 ; RV64I-LABEL: zext_srlw_zext_aext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srlw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_srlw_zext_aext:
@@ -1255,8 +1187,6 @@
 ; RV64I-LABEL: zext_srlw_zext_sext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srlw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_srlw_zext_sext:
@@ -1272,8 +1202,6 @@
 ; RV64I-LABEL: zext_srlw_zext_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srlw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_srlw_zext_zext:
@@ -1451,8 +1379,6 @@
 ; RV64I-LABEL: zext_sraw_aext_aext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sraw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sraw_aext_aext:
@@ -1468,8 +1394,6 @@
 ; RV64I-LABEL: zext_sraw_aext_sext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sraw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sraw_aext_sext:
@@ -1485,8 +1409,6 @@
 ; RV64I-LABEL: zext_sraw_aext_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sraw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sraw_aext_zext:
@@ -1502,8 +1424,6 @@
 ; RV64I-LABEL: zext_sraw_sext_aext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sraw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sraw_sext_aext:
@@ -1519,8 +1439,6 @@
 ; RV64I-LABEL: zext_sraw_sext_sext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sraw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sraw_sext_sext:
@@ -1536,8 +1454,6 @@
 ; RV64I-LABEL: zext_sraw_sext_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sraw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sraw_sext_zext:
@@ -1553,8 +1469,6 @@
 ; RV64I-LABEL: zext_sraw_zext_aext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sraw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sraw_zext_aext:
@@ -1570,8 +1484,6 @@
 ; RV64I-LABEL: zext_sraw_zext_sext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sraw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sraw_zext_sext:
@@ -1587,8 +1499,6 @@
 ; RV64I-LABEL: zext_sraw_zext_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sraw a0, a0, a1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_sraw_zext_zext:
@@ -1660,8 +1570,6 @@
 ; RV64I-LABEL: zext_addiw_aext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addiw a0, a0, 7
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_addiw_aext:
@@ -1677,8 +1585,6 @@
 ; RV64I-LABEL: zext_addiw_sext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addiw a0, a0, 8
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_addiw_sext:
@@ -1694,8 +1600,6 @@
 ; RV64I-LABEL: zext_addiw_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addiw a0, a0, 9
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zext_addiw_zext:
diff --git a/llvm/test/CodeGen/RISCV/rv64i-tricky-shifts.ll b/llvm/test/CodeGen/RISCV/rv64i-tricky-shifts.ll
--- a/llvm/test/CodeGen/RISCV/rv64i-tricky-shifts.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-tricky-shifts.ll
@@ -22,8 +22,7 @@
 define i64 @tricky_lshr(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: tricky_lshr:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    srl a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = and i64 %a, 4294967295
diff --git a/llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll b/llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
--- a/llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
+++ b/llvm/test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
@@ -172,8 +172,6 @@
 ; RV64IM-LABEL: zext_mulw_aext_aext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    mulw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = mul i32 %a, %b
   ret i32 %1
@@ -183,8 +181,6 @@
 ; RV64IM-LABEL: zext_mulw_aext_sext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    mulw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = mul i32 %a, %b
   ret i32 %1
@@ -194,8 +190,6 @@
 ; RV64IM-LABEL: zext_mulw_aext_zext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    mulw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = mul i32 %a, %b
   ret i32 %1
@@ -205,8 +199,6 @@
 ; RV64IM-LABEL: zext_mulw_sext_aext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    mulw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = mul i32 %a, %b
   ret i32 %1
@@ -216,8 +208,6 @@
 ; RV64IM-LABEL: zext_mulw_sext_sext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    mulw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = mul i32 %a, %b
   ret i32 %1
@@ -227,8 +217,6 @@
 ; RV64IM-LABEL: zext_mulw_sext_zext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    mulw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = mul i32 %a, %b
   ret i32 %1
@@ -238,8 +226,6 @@
 ; RV64IM-LABEL: zext_mulw_zext_aext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    mulw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = mul i32 %a, %b
   ret i32 %1
@@ -249,8 +235,6 @@
 ; RV64IM-LABEL: zext_mulw_zext_sext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    mulw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = mul i32 %a, %b
   ret i32 %1
@@ -260,8 +244,6 @@
 ; RV64IM-LABEL: zext_mulw_zext_zext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    mulw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = mul i32 %a, %b
   ret i32 %1
@@ -433,8 +415,6 @@
 ; RV64IM-LABEL: zext_divuw_aext_aext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divuw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = udiv i32 %a, %b
   ret i32 %1
@@ -444,8 +424,6 @@
 ; RV64IM-LABEL: zext_divuw_aext_sext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divuw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = udiv i32 %a, %b
   ret i32 %1
@@ -455,8 +433,6 @@
 ; RV64IM-LABEL: zext_divuw_aext_zext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divuw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = udiv i32 %a, %b
   ret i32 %1
@@ -466,8 +442,6 @@
 ; RV64IM-LABEL: zext_divuw_sext_aext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divuw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = udiv i32 %a, %b
   ret i32 %1
@@ -477,8 +451,6 @@
 ; RV64IM-LABEL: zext_divuw_sext_sext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divuw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = udiv i32 %a, %b
   ret i32 %1
@@ -488,8 +460,6 @@
 ; RV64IM-LABEL: zext_divuw_sext_zext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divuw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = udiv i32 %a, %b
   ret i32 %1
@@ -499,8 +469,6 @@
 ; RV64IM-LABEL: zext_divuw_zext_aext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divuw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = udiv i32 %a, %b
   ret i32 %1
@@ -510,8 +478,6 @@
 ; RV64IM-LABEL: zext_divuw_zext_sext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divuw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = udiv i32 %a, %b
   ret i32 %1
@@ -710,8 +676,6 @@
 ; RV64IM-LABEL: zext_divw_aext_aext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = sdiv i32 %a, %b
   ret i32 %1
@@ -721,8 +685,6 @@
 ; RV64IM-LABEL: zext_divw_aext_sext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = sdiv i32 %a, %b
   ret i32 %1
@@ -732,8 +694,6 @@
 ; RV64IM-LABEL: zext_divw_aext_zext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = sdiv i32 %a, %b
   ret i32 %1
@@ -743,8 +703,6 @@
 ; RV64IM-LABEL: zext_divw_sext_aext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = sdiv i32 %a, %b
   ret i32 %1
@@ -754,8 +712,6 @@
 ; RV64IM-LABEL: zext_divw_sext_sext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = sdiv i32 %a, %b
   ret i32 %1
@@ -765,8 +721,6 @@
 ; RV64IM-LABEL: zext_divw_sext_zext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = sdiv i32 %a, %b
   ret i32 %1
@@ -776,8 +730,6 @@
 ; RV64IM-LABEL: zext_divw_zext_aext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = sdiv i32 %a, %b
   ret i32 %1
@@ -787,8 +739,6 @@
 ; RV64IM-LABEL: zext_divw_zext_sext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = sdiv i32 %a, %b
   ret i32 %1
@@ -798,8 +748,6 @@
 ; RV64IM-LABEL: zext_divw_zext_zext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    divw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = sdiv i32 %a, %b
   ret i32 %1
@@ -993,8 +941,6 @@
 ; RV64IM-LABEL: zext_remw_aext_aext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %a, %b
   ret i32 %1
@@ -1004,8 +950,6 @@
 ; RV64IM-LABEL: zext_remw_aext_sext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %a, %b
   ret i32 %1
@@ -1015,8 +959,6 @@
 ; RV64IM-LABEL: zext_remw_aext_zext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %a, %b
   ret i32 %1
@@ -1026,8 +968,6 @@
 ; RV64IM-LABEL: zext_remw_sext_aext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %a, %b
   ret i32 %1
@@ -1037,8 +977,6 @@
 ; RV64IM-LABEL: zext_remw_sext_sext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %a, %b
   ret i32 %1
@@ -1048,8 +986,6 @@
 ; RV64IM-LABEL: zext_remw_sext_zext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %a, %b
   ret i32 %1
@@ -1059,8 +995,6 @@
 ; RV64IM-LABEL: zext_remw_zext_aext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %a, %b
   ret i32 %1
@@ -1070,8 +1004,6 @@
 ; RV64IM-LABEL: zext_remw_zext_sext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %a, %b
   ret i32 %1
@@ -1081,8 +1013,6 @@
 ; RV64IM-LABEL: zext_remw_zext_zext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = srem i32 %a, %b
   ret i32 %1
@@ -1294,8 +1224,6 @@
 ; RV64IM-LABEL: zext_remuw_aext_aext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remuw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %a, %b
   ret i32 %1
@@ -1305,8 +1233,6 @@
 ; RV64IM-LABEL: zext_remuw_aext_sext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remuw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %a, %b
   ret i32 %1
@@ -1316,8 +1242,6 @@
 ; RV64IM-LABEL: zext_remuw_aext_zext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remuw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %a, %b
   ret i32 %1
@@ -1327,8 +1251,6 @@
 ; RV64IM-LABEL: zext_remuw_sext_aext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remuw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %a, %b
   ret i32 %1
@@ -1338,8 +1260,6 @@
 ; RV64IM-LABEL: zext_remuw_sext_sext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remuw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %a, %b
   ret i32 %1
@@ -1349,8 +1269,6 @@
 ; RV64IM-LABEL: zext_remuw_sext_zext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remuw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %a, %b
   ret i32 %1
@@ -1360,8 +1278,6 @@
 ; RV64IM-LABEL: zext_remuw_zext_aext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remuw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %a, %b
   ret i32 %1
@@ -1371,8 +1287,6 @@
 ; RV64IM-LABEL: zext_remuw_zext_sext:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    remuw a0, a0, a1
-; RV64IM-NEXT:    slli a0, a0, 32
-; RV64IM-NEXT:    srli a0, a0, 32
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %a, %b
   ret i32 %1
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -48,8 +48,7 @@
 define i64 @adduw(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: adduw:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 32
+; RV64I-NEXT:    sext.w a1, a1
 ; RV64I-NEXT:    add a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
@@ -65,8 +64,7 @@
 define signext i8 @adduw_2(i32 signext %0, i8* %1) {
 ; RV64I-LABEL: adduw_2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    add a0, a1, a0
 ; RV64I-NEXT:    lb a0, 0(a0)
 ; RV64I-NEXT:    ret
@@ -85,8 +83,7 @@
 define i64 @zextw_i64(i64 %a) nounwind {
 ; RV64I-LABEL: zextw_i64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zextw_i64:
@@ -103,8 +100,7 @@
 ; RV64I-LABEL: zextw_demandedbits_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    ori a0, a0, 1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: zextw_demandedbits_i64:
@@ -620,8 +616,7 @@
 define i64 @adduw_imm(i32 signext %0) nounwind {
 ; RV64I-LABEL: adduw_imm:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    addi a0, a0, 5
 ; RV64I-NEXT:    ret
 ;
diff --git a/llvm/test/CodeGen/RISCV/rv64zbp-zbkb.ll b/llvm/test/CodeGen/RISCV/rv64zbp-zbkb.ll
--- a/llvm/test/CodeGen/RISCV/rv64zbp-zbkb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbp-zbkb.ll
@@ -28,8 +28,7 @@
 define i64 @pack_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: pack_i64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    slli a1, a1, 32
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/rv64zbt.ll b/llvm/test/CodeGen/RISCV/rv64zbt.ll
--- a/llvm/test/CodeGen/RISCV/rv64zbt.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbt.ll
@@ -676,9 +676,8 @@
 define signext i32 @fshl_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
 ; RV64I-LABEL: fshl_i32:
 ; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a1, a1
 ; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    andi a1, a2, 31
 ; RV64I-NEXT:    sll a0, a0, a1
@@ -698,9 +697,8 @@
 define void @fshl_i32_nosext(i32 signext %a, i32 signext %b, i32 signext %c, i32* %x) nounwind {
 ; RV64I-LABEL: fshl_i32_nosext:
 ; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a1, a1
 ; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    andi a1, a2, 31
 ; RV64I-NEXT:    sll a0, a0, a1
@@ -745,9 +743,8 @@
 define signext i32 @fshr_i32(i32 signext %a, i32 signext %b, i32 signext %c) nounwind {
 ; RV64I-LABEL: fshr_i32:
 ; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a1, a1
 ; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    andi a1, a2, 31
 ; RV64I-NEXT:    srl a0, a0, a1
@@ -767,9 +764,8 @@
 define void @fshr_i32_nosext(i32 signext %a, i32 signext %b, i32 signext %c, i32* %x) nounwind {
 ; RV64I-LABEL: fshr_i32_nosext:
 ; RV64I:       # %bb.0:
+; RV64I-NEXT:    sext.w a1, a1
 ; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    slli a1, a1, 32
-; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    andi a1, a2, 31
 ; RV64I-NEXT:    srl a0, a0, a1
diff --git a/llvm/test/CodeGen/RISCV/rv64zfh-half-convert-strict.ll b/llvm/test/CodeGen/RISCV/rv64zfh-half-convert-strict.ll
--- a/llvm/test/CodeGen/RISCV/rv64zfh-half-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zfh-half-convert-strict.ll
@@ -31,8 +31,6 @@
 ; RV64IZFH-LABEL: zext_fptosi:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
-; RV64IZFH-NEXT:    slli a0, a0, 32
-; RV64IZFH-NEXT:    srli a0, a0, 32
 ; RV64IZFH-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
diff --git a/llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll b/llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll
--- a/llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll
@@ -29,8 +29,6 @@
 ; RV64IZFH-LABEL: zext_fptosi:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
-; RV64IZFH-NEXT:    slli a0, a0, 32
-; RV64IZFH-NEXT:    srli a0, a0, 32
 ; RV64IZFH-NEXT:    ret
   %1 = fptosi half %a to i32
   ret i32 %1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
@@ -769,9 +769,7 @@
 ; CHECK-NEXT:    mv a3, a2
 ; CHECK-NEXT:    bltu a4, a5, .LBB12_5
 ; CHECK-NEXT:  # %bb.2:
-; CHECK-NEXT:    slli a3, a4, 32
-; CHECK-NEXT:    srli a3, a3, 32
-; CHECK-NEXT:    addi a4, a3, 1
+; CHECK-NEXT:    addi a4, a4, 1
 ; CHECK-NEXT:    andi a5, a4, -32
 ; CHECK-NEXT:    add a3, a5, a2
 ; CHECK-NEXT:    slli a6, a2, 2
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
@@ -2286,11 +2286,9 @@
 ; RV64ZVE32F-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; RV64ZVE32F-NEXT:    vslidedown.vi v9, v8, 1
 ; RV64ZVE32F-NEXT:    vmv.x.s a0, v9
-; RV64ZVE32F-NEXT:    slli a0, a0, 32
-; RV64ZVE32F-NEXT:    srli a1, a0, 32
+; RV64ZVE32F-NEXT:    sext.w a1, a0
 ; RV64ZVE32F-NEXT:    vmv.x.s a0, v8
-; RV64ZVE32F-NEXT:    slli a0, a0, 32
-; RV64ZVE32F-NEXT:    srli a0, a0, 32
+; RV64ZVE32F-NEXT:    sext.w a0, a0
 ; RV64ZVE32F-NEXT:    ret
   %v = call <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*> %ptrs, i32 4, <2 x i1> %m, <2 x i32> %passthru)
   %ev = zext <2 x i32> %v to <2 x i64>
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
@@ -585,8 +585,7 @@
 ;
 ; RV64-LABEL: vpreduce_umax_v2i32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    slli a0, a0, 32
-; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; RV64-NEXT:    vmv.s.x v9, a0
 ; RV64-NEXT:    vsetvli zero, a1, e32, mf2, tu, mu
@@ -626,8 +625,7 @@
 ;
 ; RV64-LABEL: vpreduce_umin_v2i32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    slli a0, a0, 32
-; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; RV64-NEXT:    vmv.s.x v9, a0
 ; RV64-NEXT:    vsetvli zero, a1, e32, mf2, tu, mu
@@ -727,8 +725,7 @@
 ;
 ; RV64-LABEL: vpreduce_umax_v4i32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    slli a0, a0, 32
-; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; RV64-NEXT:    vmv.s.x v9, a0
 ; RV64-NEXT:    vsetvli zero, a1, e32, m1, tu, mu
@@ -768,8 +765,7 @@
 ;
 ; RV64-LABEL: vpreduce_umin_v4i32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    slli a0, a0, 32
-; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; RV64-NEXT:    vmv.s.x v9, a0
 ; RV64-NEXT:    vsetvli zero, a1, e32, m1, tu, mu
diff --git a/llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
--- a/llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/pass-fast-math-flags-sdnode.ll
@@ -12,12 +12,11 @@
   ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vr = COPY $v0
   ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:vr = COPY $v9
   ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:vr = COPY $v8
-  ; CHECK-NEXT:   [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 32
-  ; CHECK-NEXT:   [[SRLI:%[0-9]+]]:gprnox0 = SRLI killed [[SLLI]], 32
+  ; CHECK-NEXT:   [[ADDIW:%[0-9]+]]:gprnox0 = ADDIW [[COPY]], 0
   ; CHECK-NEXT:   $v0 = COPY [[COPY1]]
   ; CHECK-NEXT:   [[DEF:%[0-9]+]]:vrnov0 = IMPLICIT_DEF
-  ; CHECK-NEXT:   %7:vrnov0 = nnan ninf nsz arcp contract afn reassoc nofpexcept PseudoVFMUL_VV_M1_MASK [[DEF]], [[COPY3]], [[COPY2]], $v0, killed [[SRLI]], 6 /* e64 */, 1, implicit $frm
-  ; CHECK-NEXT:   $v8 = COPY %7
+  ; CHECK-NEXT:   %6:vrnov0 = nnan ninf nsz arcp contract afn reassoc nofpexcept PseudoVFMUL_VV_M1_MASK [[DEF]], [[COPY3]], [[COPY2]], $v0, killed [[ADDIW]], 6 /* e64 */, 1, implicit $frm
+  ; CHECK-NEXT:   $v8 = COPY %6
   ; CHECK-NEXT:   PseudoRET implicit $v8
   %1 = call fast <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %x, <vscale x 1 x double> %y, <vscale x 1 x i1> %m, i32 %vl)
   ret <vscale x 1 x double> %1
diff --git a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
@@ -852,8 +852,7 @@
 ;
 ; RV64-LABEL: vpreduce_umax_nxv1i32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    slli a0, a0, 32
-; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; RV64-NEXT:    vmv.s.x v9, a0
 ; RV64-NEXT:    vsetvli zero, a1, e32, mf2, tu, mu
@@ -893,8 +892,7 @@
 ;
 ; RV64-LABEL: vpreduce_umin_nxv1i32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    slli a0, a0, 32
-; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; RV64-NEXT:    vmv.s.x v9, a0
 ; RV64-NEXT:    vsetvli zero, a1, e32, mf2, tu, mu
@@ -994,8 +992,7 @@
 ;
 ; RV64-LABEL: vpreduce_umax_nxv2i32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    slli a0, a0, 32
-; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; RV64-NEXT:    vmv.s.x v9, a0
 ; RV64-NEXT:    vsetvli zero, a1, e32, m1, tu, mu
@@ -1035,8 +1032,7 @@
 ;
 ; RV64-LABEL: vpreduce_umin_nxv2i32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    slli a0, a0, 32
-; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; RV64-NEXT:    vmv.s.x v9, a0
 ; RV64-NEXT:    vsetvli zero, a1, e32, m1, tu, mu
@@ -1136,8 +1132,7 @@
 ;
 ; RV64-LABEL: vpreduce_umax_nxv4i32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    slli a0, a0, 32
-; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; RV64-NEXT:    vmv.s.x v10, a0
 ; RV64-NEXT:    vsetvli zero, a1, e32, m2, tu, mu
@@ -1184,27 +1179,26 @@
 ;
 ; RV64-LABEL: vpreduce_umax_nxv32i32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    csrr a3, vlenb
-; RV64-NEXT:    srli a2, a3, 2
-; RV64-NEXT:    slli a4, a0, 32
-; RV64-NEXT:    slli a0, a3, 1
-; RV64-NEXT:    srli a3, a4, 32
+; RV64-NEXT:    csrr a2, vlenb
+; RV64-NEXT:    srli a3, a2, 2
+; RV64-NEXT:    slli a2, a2, 1
+; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    mv a4, a1
-; RV64-NEXT:    bltu a1, a0, .LBB67_2
+; RV64-NEXT:    bltu a1, a2, .LBB67_2
 ; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    mv a4, a0
+; RV64-NEXT:    mv a4, a2
 ; RV64-NEXT:  .LBB67_2:
 ; RV64-NEXT:    li a5, 0
 ; RV64-NEXT:    vsetvli a6, zero, e8, mf2, ta, mu
-; RV64-NEXT:    vslidedown.vx v24, v0, a2
+; RV64-NEXT:    vslidedown.vx v24, v0, a3
 ; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; RV64-NEXT:    vmv.s.x v25, a3
+; RV64-NEXT:    vmv.s.x v25, a0
 ; RV64-NEXT:    vsetvli zero, a4, e32, m8, tu, mu
 ; RV64-NEXT:    vredmaxu.vs v25, v8, v25, v0.t
-; RV64-NEXT:    vmv.x.s a2, v25
+; RV64-NEXT:    vmv.x.s a3, v25
 ; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
-; RV64-NEXT:    sub a0, a1, a0
-; RV64-NEXT:    vmv.s.x v8, a2
+; RV64-NEXT:    sub a0, a1, a2
+; RV64-NEXT:    vmv.s.x v8, a3
 ; RV64-NEXT:    bltu a1, a0, .LBB67_4
 ; RV64-NEXT:  # %bb.3:
 ; RV64-NEXT:    mv a5, a0
@@ -1247,8 +1241,7 @@
 ;
 ; RV64-LABEL: vpreduce_umin_nxv4i32:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    slli a0, a0, 32
-; RV64-NEXT:    srli a0, a0, 32
+; RV64-NEXT:    sext.w a0, a0
 ; RV64-NEXT:    vsetivli zero, 1, e32, m1, ta, mu
 ; RV64-NEXT:    vmv.s.x v10, a0
 ; RV64-NEXT:    vsetvli zero, a1, e32, m2, tu, mu
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll b/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
@@ -268,8 +268,7 @@
 ;
 ; RV64V-LABEL: vsplat_nxv8i64_14:
 ; RV64V:       # %bb.0:
-; RV64V-NEXT:    slli a0, a0, 32
-; RV64V-NEXT:    srli a0, a0, 32
+; RV64V-NEXT:    sext.w a0, a0
 ; RV64V-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
 ; RV64V-NEXT:    vmv.v.x v8, a0
 ; RV64V-NEXT:    ret
diff --git a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
--- a/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
+++ b/llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
@@ -306,8 +306,7 @@
 ;
 ; RV64I-LABEL: zext_i32_to_i64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
   %1 = zext i32 %a to i64
   ret i64 %1
diff --git a/llvm/test/CodeGen/RISCV/shrinkwrap.ll b/llvm/test/CodeGen/RISCV/shrinkwrap.ll
--- a/llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ b/llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -131,16 +131,14 @@
 ;
 ; RV64I-SW-LABEL: conditional_alloca:
 ; RV64I-SW:       # %bb.0:
-; RV64I-SW-NEXT:    sext.w a1, a0
-; RV64I-SW-NEXT:    li a2, 32
-; RV64I-SW-NEXT:    bltu a2, a1, .LBB1_2
+; RV64I-SW-NEXT:    sext.w a0, a0
+; RV64I-SW-NEXT:    li a1, 32
+; RV64I-SW-NEXT:    bltu a1, a0, .LBB1_2
 ; RV64I-SW-NEXT:  # %bb.1: # %if.then
 ; RV64I-SW-NEXT:    addi sp, sp, -16
 ; RV64I-SW-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-SW-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; RV64I-SW-NEXT:    addi s0, sp, 16
-; RV64I-SW-NEXT:    slli a0, a0, 32
-; RV64I-SW-NEXT:    srli a0, a0, 32
 ; RV64I-SW-NEXT:    addi a0, a0, 15
 ; RV64I-SW-NEXT:    andi a0, a0, -16
 ; RV64I-SW-NEXT:    sub a0, sp, a0
diff --git a/llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll b/llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
--- a/llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
+++ b/llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
@@ -48,8 +48,7 @@
 ; RV64I-NEXT:    .cfi_def_cfa s0, 0
 ; RV64I-NEXT:    andi sp, sp, -64
 ; RV64I-NEXT:    mv s1, sp
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    addi a0, a0, 15
 ; RV64I-NEXT:    andi a0, a0, -16
 ; RV64I-NEXT:    sub a0, sp, a0
diff --git a/llvm/test/CodeGen/RISCV/urem-lkk.ll b/llvm/test/CodeGen/RISCV/urem-lkk.ll
--- a/llvm/test/CodeGen/RISCV/urem-lkk.ll
+++ b/llvm/test/CodeGen/RISCV/urem-lkk.ll
@@ -37,8 +37,7 @@
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    li a1, 95
 ; RV64I-NEXT:    call __umoddi3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
@@ -92,8 +91,7 @@
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
+; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    li a1, 1060
 ; RV64I-NEXT:    call __umoddi3@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
@@ -160,8 +158,7 @@
 ; RV64I-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli s0, a0, 32
+; RV64I-NEXT:    sext.w s0, a0
 ; RV64I-NEXT:    li a1, 95
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call __umoddi3@plt
diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll
--- a/llvm/test/CodeGen/RISCV/vararg.ll
+++ b/llvm/test/CodeGen/RISCV/vararg.ll
@@ -358,8 +358,7 @@
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a1, 8(s0)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a0, s0, 16
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a0, -32(s0)
-; LP64-LP64F-LP64D-FPELIM-NEXT:    slli a0, a1, 32
-; LP64-LP64F-LP64D-FPELIM-NEXT:    srli a0, a0, 32
+; LP64-LP64F-LP64D-FPELIM-NEXT:    sext.w a0, a1
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a0, a0, 15
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    andi a0, a0, -16
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sub a0, sp, a0
@@ -390,8 +389,7 @@
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, 8(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a0, s0, 16
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a0, -32(s0)
-; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a0, a1, 32
-; LP64-LP64F-LP64D-WITHFP-NEXT:    srli a0, a0, 32
+; LP64-LP64F-LP64D-WITHFP-NEXT:    sext.w a0, a1
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a0, a0, 15
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    andi a0, a0, -16
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sub a0, sp, a0
@@ -565,9 +563,7 @@
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a0, 8(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    lw a0, 8(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addiw a0, a0, 7
-; LP64-LP64F-LP64D-FPELIM-NEXT:    slli a1, a0, 32
-; LP64-LP64F-LP64D-FPELIM-NEXT:    srli a1, a1, 32
-; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a1, a1, 8
+; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a1, a0, 8
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a1, 8(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    li a1, 1
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    slli a1, a1, 32
@@ -594,9 +590,7 @@
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a0, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    lw a0, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addiw a0, a0, 7
-; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a1, a0, 32
-; LP64-LP64F-LP64D-WITHFP-NEXT:    srli a1, a1, 32
-; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a1, a1, 8
+; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a1, a0, 8
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a1, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    li a1, 1
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a1, a1, 32
@@ -888,9 +882,7 @@
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    lw a0, 8(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a2, 16(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    addiw a0, a0, 7
-; LP64-LP64F-LP64D-FPELIM-NEXT:    slli a2, a0, 32
-; LP64-LP64F-LP64D-FPELIM-NEXT:    srli a2, a2, 32
-; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a2, a2, 8
+; LP64-LP64F-LP64D-FPELIM-NEXT:    addi a2, a0, 8
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    sd a2, 8(sp)
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    li a2, 1
 ; LP64-LP64F-LP64D-FPELIM-NEXT:    slli a2, a2, 32
@@ -917,9 +909,7 @@
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    lw a0, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a2, 0(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    addiw a0, a0, 7
-; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a2, a0, 32
-; LP64-LP64F-LP64D-WITHFP-NEXT:    srli a2, a2, 32
-; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a2, a2, 8
+; LP64-LP64F-LP64D-WITHFP-NEXT:    addi a2, a0, 8
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    sd a2, -24(s0)
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    li a2, 1
 ; LP64-LP64F-LP64D-WITHFP-NEXT:    slli a2, a2, 32