Index: llvm/test/TableGen/AsmPredicateCombiningRISCV.td =================================================================== --- llvm/test/TableGen/AsmPredicateCombiningRISCV.td +++ llvm/test/TableGen/AsmPredicateCombiningRISCV.td @@ -60,6 +60,7 @@ def SmallInst1 : RVInst16<1, []>; def : CompressPat<(BigInst Regs:$r), (SmallInst1 Regs:$r), [AsmPred1]>; // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] && +// COMPRESS-NEXT: (MI.getOperand(0).isReg()) && // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { // COMPRESS-NEXT: // SmallInst1 $r @@ -67,12 +68,14 @@ def : CompressPat<(BigInst Regs:$r), (SmallInst2 Regs:$r), [AsmPred2]>; // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond2a] && // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] && +// COMPRESS-NEXT: (MI.getOperand(0).isReg()) && // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { // COMPRESS-NEXT: // SmallInst2 $r def SmallInst3 : RVInst16<2, []>; def : CompressPat<(BigInst Regs:$r), (SmallInst3 Regs:$r), [AsmPred3]>; // COMPRESS: if ((STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) && +// COMPRESS-NEXT: (MI.getOperand(0).isReg()) && // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { // COMPRESS-NEXT: // SmallInst3 $r @@ -81,6 +84,7 @@ // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] && // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2a] && // COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] && +// COMPRESS-NEXT: (MI.getOperand(0).isReg()) && // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { // COMPRESS-NEXT: // SmallInst4 $r @@ -88,6 +92,7 @@ def : CompressPat<(BigInst Regs:$r), (SmallInst5 Regs:$r), [AsmPred1, AsmPred3]>; // COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] && // COMPRESS-NEXT: (STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) && +// COMPRESS-NEXT: (MI.getOperand(0).isReg()) && // COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { // COMPRESS-NEXT: // SmallInst5 $r Index: llvm/utils/TableGen/CompressInstEmitter.cpp =================================================================== --- llvm/utils/TableGen/CompressInstEmitter.cpp +++ llvm/utils/TableGen/CompressInstEmitter.cpp @@ -716,7 +716,10 @@ if (SourceOperandMap[OpNo].TiedOpIdx != -1) { if (Source.Operands[OpNo].Rec->isSubClassOf("RegisterClass")) CondStream.indent(6) - << "(MI.getOperand(" << OpNo << ").getReg() == MI.getOperand(" + << "(MI.getOperand(" << OpNo << ").isReg()) && (MI.getOperand(" + << SourceOperandMap[OpNo].TiedOpIdx << ").isReg()) &&\n" + << " (MI.getOperand(" << OpNo + << ").getReg() == MI.getOperand(" << SourceOperandMap[OpNo].TiedOpIdx << ").getReg()) &&\n"; else PrintFatalError("Unexpected tied operand types!\n"); @@ -735,7 +738,8 @@ case OpData::Reg: { Record *Reg = SourceOperandMap[OpNo].Data.Reg; CondStream.indent(6) - << "(MI.getOperand(" << OpNo << ").getReg() == " << TargetName + << "(MI.getOperand(" << OpNo << ").isReg()) &&\n" + << " (MI.getOperand(" << OpNo << ").getReg() == " << TargetName << "::" << Reg->getName() << ") &&\n"; break; } @@ -759,10 +763,12 @@ // Don't check register class if this is a tied operand, it was done // for the operand its tied to. if (DestOperand.getTiedRegister() == -1) - CondStream.indent(6) << "(MRI.getRegClass(" << TargetName - << "::" << DestOperand.Rec->getName() - << "RegClassID).contains(MI.getOperand(" - << OpIdx << ").getReg())) &&\n"; + CondStream.indent(6) + << "(MI.getOperand(" << OpIdx << ").isReg()) &&\n" + << " (MRI.getRegClass(" << TargetName + << "::" << DestOperand.Rec->getName() + << "RegClassID).contains(MI.getOperand(" << OpIdx + << ").getReg())) &&\n"; if (CompressOrUncompress) CodeStream.indent(6)