Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
===================================================================
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h
@@ -30,6 +30,7 @@
   void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
                  const MCSubtargetInfo &STI, raw_ostream &O) override;
   void printRegName(raw_ostream &OS, unsigned RegNo) const override;
+  void printRegName(raw_ostream &OS, unsigned RegNo, unsigned AltIdx) const;
 
   // Autogenerated by tblgen.
   std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
Index: llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
===================================================================
--- llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
+++ llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
@@ -63,6 +63,11 @@
   OS << markup("<reg:") << getRegisterName(RegNo) << markup(">");
 }
 
+void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo,
+                                      unsigned AltIdx) const {
+  OS << markup("<reg:") << getRegisterName(RegNo, AltIdx) << markup(">");
+}
+
 void AArch64InstPrinter::printInst(const MCInst *MI, uint64_t Address,
                                    StringRef Annot, const MCSubtargetInfo &STI,
                                    raw_ostream &O) {
@@ -112,8 +117,10 @@
       }
 
       if (AsmMnemonic) {
-        O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
-          << ", " << getRegisterName(getWRegFromXReg(Op1.getReg()));
+        O << '\t' << AsmMnemonic << '\t';
+        printRegName(O, Op0.getReg());
+        O << ", ";
+        printRegName(O, getWRegFromXReg(Op1.getReg()));
         printAnnotation(O, Annot);
         return;
       }
@@ -737,14 +744,15 @@
 
   bool IsTbx;
   if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
-    O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t'
-      << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", ";
+    O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t';
+    printRegName(O, MI->getOperand(0).getReg(), AArch64::vreg);
+    O << ", ";
 
     unsigned ListOpNum = IsTbx ? 2 : 1;
     printVectorList(MI, ListOpNum, STI, O, "");
 
-    O << ", "
-      << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
+    O << ", ";
+    printRegName(O, MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg);
     printAnnotation(O, Annot);
     return;
   }
@@ -762,14 +770,17 @@
 
     // Next the address: [xN]
     unsigned AddrReg = MI->getOperand(OpNum++).getReg();
-    O << ", [" << getRegisterName(AddrReg) << ']';
+    O << ", [";
+    printRegName(O, AddrReg);
+    O << ']';
 
     // Finally, there might be a post-indexed offset.
     if (LdStDesc->NaturalOffset != 0) {
       unsigned Reg = MI->getOperand(OpNum++).getReg();
-      if (Reg != AArch64::XZR)
-        O << ", " << getRegisterName(Reg);
-      else {
+      if (Reg != AArch64::XZR) {
+        O << ", ";
+        printRegName(O, Reg);
+      } else {
         assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
         O << ", " << markup("<imm:") << "#" << LdStDesc->NaturalOffset
           << markup(">");
@@ -890,8 +901,10 @@
   std::transform(Str.begin(), Str.end(), Str.begin(), ::tolower);
 
   O << '\t' << Str;
-  if (NeedsReg)
-    O << ", " << getRegisterName(MI->getOperand(4).getReg());
+  if (NeedsReg) {
+    O << ", ";
+    printRegName(O, MI->getOperand(4).getReg());
+  }
 
   return true;
 }
@@ -1023,7 +1036,7 @@
   const MCOperand &Op = MI->getOperand(OpNo);
   assert(Op.isReg() && "Non-register vreg operand!");
   unsigned Reg = Op.getReg();
-  O << getRegisterName(Reg, AArch64::vreg);
+  printRegName(O, Reg, AArch64::vreg);
 }
 
 void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
@@ -1183,7 +1196,9 @@
 void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
                                         const MCSubtargetInfo &STI,
                                         raw_ostream &O) {
-  O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
+  O << '[';
+  printRegName(O, MI->getOperand(OpNum).getReg());
+  O << ']';
 }
 
 template<int Scale>
@@ -1209,7 +1224,8 @@
 void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
                                           unsigned Scale, raw_ostream &O) {
   const MCOperand MO1 = MI->getOperand(OpNum + 1);
-  O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
+  O << '[';
+  printRegName(O, MI->getOperand(OpNum).getReg());
   if (MO1.isImm()) {
     O << ", " << markup("<imm:") << "#" << formatImm(MO1.getImm() * Scale)
       << markup(">");
@@ -1366,7 +1382,9 @@
 
   unsigned Even = MRI.getSubReg(Reg,  Sube);
   unsigned Odd = MRI.getSubReg(Reg,  Subo);
-  O << getRegisterName(Even) << ", " << getRegisterName(Odd);
+  printRegName(O, Even);
+  O << ", ";
+  printRegName(O, Odd);
 }
 
 void AArch64InstPrinter::printMatrixTileList(const MCInst *MI, unsigned OpNum,
@@ -1435,10 +1453,11 @@
   }
 
   for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
-    if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
-      O << getRegisterName(Reg) << LayoutSuffix;
-    else
-      O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix;
+    if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
+      printRegName(O, Reg);
+    else
+      printRegName(O, Reg, AArch64::vreg);
+    O << LayoutSuffix;
 
     if (i + 1 != NumRegs)
       O << ", ";
Index: llvm/test/MC/Disassembler/AArch64/marked-up.txt
===================================================================
--- llvm/test/MC/Disassembler/AArch64/marked-up.txt
+++ llvm/test/MC/Disassembler/AArch64/marked-up.txt
@@ -12,3 +12,21 @@
 ## ls64
 # CHECK-NEXT: st64b <reg:x2>, [<reg:x1>]
 0x22 0x90 0x3f 0xf8
+
+## bfi/bfxil
+# CHECK-NEXT: bfi	<reg:x4>, <reg:x5>, <imm:#52>, <imm:#11>
+0xa4 0x28 0x4c 0xb3
+# CHECK-NEXT: bfxil	<reg:w9>, <reg:w10>, <imm:#0>, <imm:#1>
+0x49 0x1 0x0 0x33
+
+## sbfiz/ubfiz
+# CHECK-NEXT: sbfiz	<reg:x2>, <reg:x3>, <imm:#63>, <imm:#1>
+0x62 0x0 0x41 0x93
+# CHECK-NEXT: ubfiz	<reg:xzr>, <reg:xzr>, <imm:#10>, <imm:#11>
+0xff 0x2b 0x76 0xd3
+
+## sbfx/ubfx
+# CHECK-NEXT: sbfx	<reg:w12>, <reg:w9>, <imm:#0>, <imm:#1>
+0x2c 0x1 0x0 0x13
+# CHECK-NEXT: ubfx	<reg:xzr>, <reg:x4>, <imm:#0>, <imm:#1>
+0x9f 0x0 0x40 0xd3