Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -2117,6 +2117,20 @@
   def : InstAlias<"fcmlt $Zd, $Pg/z, $Zm, $Zn",
                   (FCMGT_PPzZZ_D PPR64:$Zd, PPR3bAny:$Pg, ZPR64:$Zn, ZPR64:$Zm), 0>;
 
+  class AddSubFoldPattern<ValueType Zty, ValueType PTy,
+                          SDNode op, string I, string size>
+    : Pat<(op (Zty ZPR:$Za),
+              (vselect (PTy PPR:$gp), (Zty ZPR:$Zb), (SVEDup0))),
+          (!cast<Instruction>(I # "_ZPmZ_" # size) PPR:$gp, ZPR:$Za, ZPR:$Zb)>;
+  multiclass add_sub_folds<SDNode Op, string I> {
+  def : AddSubFoldPattern<nxv16i8, nxv16i1, Op, I, "B">;
+  def : AddSubFoldPattern<nxv8i16, nxv8i1, Op, I, "H">;
+  def : AddSubFoldPattern<nxv4i32, nxv4i1, Op, I, "S">;
+  def : AddSubFoldPattern<nxv2i64, nxv2i1, Op, I, "D">;
+  }
+  defm : add_sub_folds<add, "ADD">;
+  defm : add_sub_folds<sub, "SUB">;
+
   // Pseudo instructions representing unpredicated LDR and STR for ZPR2,3,4.
   // These get expanded to individual LDR_ZXI/STR_ZXI instructions in
   // AArch64ExpandPseudoInsts.
Index: llvm/test/CodeGen/AArch64/sve-masked-add-sub.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-masked-add-sub.ll
@@ -0,0 +1,90 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
+
+;
+; Masked Additions
+;
+
+define <vscale x 16 x i8> @masked_add_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: masked_add_nxv16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    add z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT:    ret
+  %select = select <vscale x 16 x i1> %mask, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer
+  %ret = add <vscale x 16 x i8> %a, %select
+  ret <vscale x 16 x i8> %ret
+}
+
+define <vscale x 8 x i16> @masked_add_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: masked_add_nxv8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    add z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    ret
+  %select = select <vscale x 8 x i1> %mask, <vscale x 8 x i16> %b, <vscale x 8 x i16> zeroinitializer
+  %ret = add <vscale x 8 x i16> %a, %select
+  ret <vscale x 8 x i16> %ret
+}
+
+define <vscale x 4 x i32> @masked_add_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: masked_add_nxv4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    add z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    ret
+  %select = select <vscale x 4 x i1> %mask, <vscale x 4 x i32> %b, <vscale x 4 x i32> zeroinitializer
+  %ret = add <vscale x 4 x i32> %a, %select
+  ret <vscale x 4 x i32> %ret
+}
+
+define <vscale x 2 x i64> @masked_add_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: masked_add_nxv2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    add z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT:    ret
+  %select = select <vscale x 2 x i1> %mask, <vscale x 2 x i64> %b, <vscale x 2 x i64> zeroinitializer
+  %ret = add <vscale x 2 x i64> %a, %select
+  ret <vscale x 2 x i64> %ret
+}
+
+;
+; Masked Subtractions
+;
+
+define <vscale x 16 x i8> @masked_sub_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i1> %mask) {
+; CHECK-LABEL: masked_sub_nxv16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sub z0.b, p0/m, z0.b, z1.b
+; CHECK-NEXT:    ret
+  %select = select <vscale x 16 x i1> %mask, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer
+  %ret = sub <vscale x 16 x i8> %a, %select
+  ret <vscale x 16 x i8> %ret
+}
+
+define <vscale x 8 x i16> @masked_sub_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i1> %mask) {
+; CHECK-LABEL: masked_sub_nxv8i16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sub z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    ret
+  %select = select <vscale x 8 x i1> %mask, <vscale x 8 x i16> %b, <vscale x 8 x i16> zeroinitializer
+  %ret = sub <vscale x 8 x i16> %a, %select
+  ret <vscale x 8 x i16> %ret
+}
+
+define <vscale x 4 x i32> @masked_sub_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i1> %mask) {
+; CHECK-LABEL: masked_sub_nxv4i32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sub z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    ret
+  %select = select <vscale x 4 x i1> %mask, <vscale x 4 x i32> %b, <vscale x 4 x i32> zeroinitializer
+  %ret = sub <vscale x 4 x i32> %a, %select
+  ret <vscale x 4 x i32> %ret
+}
+
+define <vscale x 2 x i64> @masked_sub_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i1> %mask) {
+; CHECK-LABEL: masked_sub_nxv2i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sub z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT:    ret
+  %select = select <vscale x 2 x i1> %mask, <vscale x 2 x i64> %b, <vscale x 2 x i64> zeroinitializer
+  %ret = sub <vscale x 2 x i64> %a, %select
+  ret <vscale x 2 x i64> %ret
+}