Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h =================================================================== --- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h +++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h @@ -128,6 +128,7 @@ #include "RISCVGenDAGISel.inc" private: + bool doPeepholeLoadStoreADDI(SDNode *Node); bool doPeepholeSExtW(SDNode *Node); bool doPeepholeMaskedRVV(SDNode *Node); }; Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp =================================================================== --- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -146,6 +146,7 @@ continue; MadeChange |= doPeepholeSExtW(N); + MadeChange |= doPeepholeLoadStoreADDI(N); MadeChange |= doPeepholeMaskedRVV(N); } @@ -155,6 +156,48 @@ CurDAG->RemoveDeadNodes(); } +// Returns true if N is a MachineSDNode that has a reg and a constant zero +// memory operand. The indices of the base pointer and offset are returned in +// BaseOpIdx and OffsetOpIdx. +static bool hasConstantZeroMemOffset(SDNode *N, unsigned &BaseOpIdx, + unsigned &OffsetOpIdx) { + if (!N->isMachineOpcode()) + return false; + + switch (N->getMachineOpcode()) { + case RISCV::LB: + case RISCV::LH: + case RISCV::LW: + case RISCV::LBU: + case RISCV::LHU: + case RISCV::LWU: + case RISCV::LD: + case RISCV::FLH: + case RISCV::FLW: + case RISCV::FLD: + BaseOpIdx = 0; + OffsetOpIdx = 1; + break; + case RISCV::SB: + case RISCV::SH: + case RISCV::SW: + case RISCV::SD: + case RISCV::FSH: + case RISCV::FSW: + case RISCV::FSD: + BaseOpIdx = 1; + OffsetOpIdx = 2; + break; + default: + return false; + } + + if (!isa(N->getOperand(OffsetOpIdx))) + return false; + + return (N->getConstantOperandVal(OffsetOpIdx) == 0); +} + static SDNode *selectImmSeq(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT, RISCVMatInt::InstSeq &Seq) { SDNode *Result = nullptr; @@ -1822,8 +1865,8 @@ return true; } -// Is this ADD instruction only used as the base pointer of scalar loads and -// stores? +// Is this ADD/ADD_LO instruction only used as the base pointer of scalar +// loads and stores? static bool isWorthFoldingAdd(SDValue Add) { for (auto Use : Add->uses()) { if (Use->getOpcode() != ISD::LOAD && Use->getOpcode() != ISD::STORE && @@ -1854,7 +1897,10 @@ SDLoc DL(Addr); MVT VT = Addr.getSimpleValueType(); - if (Addr.getOpcode() == RISCVISD::ADD_LO) { + // Select the Base and Offset from the ADD_LO except in the case that the + // ADD_LO is used in non-memory instruction (e.g. as a base to an add). In + // which case, leaving it separated may lead to better codegen. + if (Addr.getOpcode() == RISCVISD::ADD_LO && isWorthFoldingAdd(Addr)) { Base = Addr.getOperand(0); Offset = Addr.getOperand(1); return true; @@ -2337,6 +2383,46 @@ return false; } +// SelectAddrRegImm won't merge an ADD_LO into a memory operation if it has +// uses that aren't scalar loads and stores. This will turn out to be a bad +// decision if all those other uses end up being merged into memory +// operations. This peephole folds the resulting ADDI back in that is the +// case. +bool RISCVDAGToDAGISel::doPeepholeLoadStoreADDI(SDNode *N) { + unsigned OffsetOpIdx, BaseOpIdx; + if (!hasConstantZeroMemOffset(N, BaseOpIdx, OffsetOpIdx)) + return false; + + SDValue Base = N->getOperand(BaseOpIdx); + if (!Base.isMachineOpcode()) + return false; + if (Base.getMachineOpcode() != RISCV::ADDI) + return false; + if (!isa(Base.getOperand(1))) + return false; + for (auto Use : Base->uses()) { + unsigned Dummy1, Dummy2; + if (!hasConstantZeroMemOffset(Use, Dummy1, Dummy2)) + return false; + } + + LLVM_DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: "); + LLVM_DEBUG(Base->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\nN: "); + LLVM_DEBUG(N->dump(CurDAG)); + LLVM_DEBUG(dbgs() << "\n"); + + if (BaseOpIdx == 0) { // Load + N = CurDAG->UpdateNodeOperands(N, Base.getOperand(0), Base.getOperand(1), + N->getOperand(2)); + } else { // Store + N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), Base.getOperand(0), + Base.getOperand(1), N->getOperand(3)); + } + + return true; +} + // Try to remove sext.w if the input is a W instruction or can be made into // a W instruction cheaply. bool RISCVDAGToDAGISel::doPeepholeSExtW(SDNode *N) { Index: llvm/test/CodeGen/RISCV/byval.ll =================================================================== --- llvm/test/CodeGen/RISCV/byval.ll +++ llvm/test/CodeGen/RISCV/byval.ll @@ -23,15 +23,15 @@ ; RV32I-NEXT: addi sp, sp, -32 ; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: lui a0, %hi(foo) -; RV32I-NEXT: lw a1, %lo(foo)(a0) -; RV32I-NEXT: sw a1, 12(sp) ; RV32I-NEXT: addi a0, a0, %lo(foo) ; RV32I-NEXT: lw a1, 12(a0) ; RV32I-NEXT: sw a1, 24(sp) ; RV32I-NEXT: lw a1, 8(a0) ; RV32I-NEXT: sw a1, 20(sp) -; RV32I-NEXT: lw a0, 4(a0) -; RV32I-NEXT: sw a0, 16(sp) +; RV32I-NEXT: lw a1, 4(a0) +; RV32I-NEXT: sw a1, 16(sp) +; RV32I-NEXT: lw a0, 0(a0) +; RV32I-NEXT: sw a0, 12(sp) ; RV32I-NEXT: addi a0, sp, 12 ; RV32I-NEXT: call callee@plt ; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload Index: llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll =================================================================== --- llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll +++ llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll @@ -24,11 +24,11 @@ ; ILP32-LABEL: callee: ; ILP32: # %bb.0: ; ILP32-NEXT: lui a0, %hi(var) -; ILP32-NEXT: flw ft0, %lo(var)(a0) +; ILP32-NEXT: addi a1, a0, %lo(var) +; ILP32-NEXT: flw ft0, 0(a1) ; ILP32-NEXT: flw ft1, %lo(var+4)(a0) ; ILP32-NEXT: flw ft2, %lo(var+8)(a0) ; ILP32-NEXT: flw ft3, %lo(var+12)(a0) -; ILP32-NEXT: addi a1, a0, %lo(var) ; ILP32-NEXT: flw ft4, 16(a1) ; ILP32-NEXT: flw ft5, 20(a1) ; ILP32-NEXT: flw ft6, 24(a1) @@ -88,17 +88,17 @@ ; ILP32-NEXT: fsw ft3, %lo(var+12)(a0) ; ILP32-NEXT: fsw ft2, %lo(var+8)(a0) ; ILP32-NEXT: fsw ft1, %lo(var+4)(a0) -; ILP32-NEXT: fsw ft0, %lo(var)(a0) +; ILP32-NEXT: fsw ft0, 0(a1) ; ILP32-NEXT: ret ; ; LP64-LABEL: callee: ; LP64: # %bb.0: ; LP64-NEXT: lui a0, %hi(var) -; LP64-NEXT: flw ft0, %lo(var)(a0) +; LP64-NEXT: addi a1, a0, %lo(var) +; LP64-NEXT: flw ft0, 0(a1) ; LP64-NEXT: flw ft1, %lo(var+4)(a0) ; LP64-NEXT: flw ft2, %lo(var+8)(a0) ; LP64-NEXT: flw ft3, %lo(var+12)(a0) -; LP64-NEXT: addi a1, a0, %lo(var) ; LP64-NEXT: flw ft4, 16(a1) ; LP64-NEXT: flw ft5, 20(a1) ; LP64-NEXT: flw ft6, 24(a1) @@ -158,7 +158,7 @@ ; LP64-NEXT: fsw ft3, %lo(var+12)(a0) ; LP64-NEXT: fsw ft2, %lo(var+8)(a0) ; LP64-NEXT: fsw ft1, %lo(var+4)(a0) -; LP64-NEXT: fsw ft0, %lo(var)(a0) +; LP64-NEXT: fsw ft0, 0(a1) ; LP64-NEXT: ret ; ; ILP32F-LABEL: callee: @@ -177,11 +177,11 @@ ; ILP32F-NEXT: fsw fs10, 4(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs11, 0(sp) # 4-byte Folded Spill ; ILP32F-NEXT: lui a0, %hi(var) -; ILP32F-NEXT: flw ft0, %lo(var)(a0) +; ILP32F-NEXT: addi a1, a0, %lo(var) +; ILP32F-NEXT: flw ft0, 0(a1) ; ILP32F-NEXT: flw ft1, %lo(var+4)(a0) ; ILP32F-NEXT: flw ft2, %lo(var+8)(a0) ; ILP32F-NEXT: flw ft3, %lo(var+12)(a0) -; ILP32F-NEXT: addi a1, a0, %lo(var) ; ILP32F-NEXT: flw ft4, 16(a1) ; ILP32F-NEXT: flw ft5, 20(a1) ; ILP32F-NEXT: flw ft6, 24(a1) @@ -241,7 +241,7 @@ ; ILP32F-NEXT: fsw ft3, %lo(var+12)(a0) ; ILP32F-NEXT: fsw ft2, %lo(var+8)(a0) ; ILP32F-NEXT: fsw ft1, %lo(var+4)(a0) -; ILP32F-NEXT: fsw ft0, %lo(var)(a0) +; ILP32F-NEXT: fsw ft0, 0(a1) ; ILP32F-NEXT: flw fs0, 44(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fs1, 40(sp) # 4-byte Folded Reload ; ILP32F-NEXT: flw fs2, 36(sp) # 4-byte Folded Reload @@ -273,11 +273,11 @@ ; LP64F-NEXT: fsw fs10, 4(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fs11, 0(sp) # 4-byte Folded Spill ; LP64F-NEXT: lui a0, %hi(var) -; LP64F-NEXT: flw ft0, %lo(var)(a0) +; LP64F-NEXT: addi a1, a0, %lo(var) +; LP64F-NEXT: flw ft0, 0(a1) ; LP64F-NEXT: flw ft1, %lo(var+4)(a0) ; LP64F-NEXT: flw ft2, %lo(var+8)(a0) ; LP64F-NEXT: flw ft3, %lo(var+12)(a0) -; LP64F-NEXT: addi a1, a0, %lo(var) ; LP64F-NEXT: flw ft4, 16(a1) ; LP64F-NEXT: flw ft5, 20(a1) ; LP64F-NEXT: flw ft6, 24(a1) @@ -337,7 +337,7 @@ ; LP64F-NEXT: fsw ft3, %lo(var+12)(a0) ; LP64F-NEXT: fsw ft2, %lo(var+8)(a0) ; LP64F-NEXT: fsw ft1, %lo(var+4)(a0) -; LP64F-NEXT: fsw ft0, %lo(var)(a0) +; LP64F-NEXT: fsw ft0, 0(a1) ; LP64F-NEXT: flw fs0, 44(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fs1, 40(sp) # 4-byte Folded Reload ; LP64F-NEXT: flw fs2, 36(sp) # 4-byte Folded Reload @@ -369,11 +369,11 @@ ; ILP32D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill ; ILP32D-NEXT: lui a0, %hi(var) -; ILP32D-NEXT: flw ft0, %lo(var)(a0) +; ILP32D-NEXT: addi a1, a0, %lo(var) +; ILP32D-NEXT: flw ft0, 0(a1) ; ILP32D-NEXT: flw ft1, %lo(var+4)(a0) ; ILP32D-NEXT: flw ft2, %lo(var+8)(a0) ; ILP32D-NEXT: flw ft3, %lo(var+12)(a0) -; ILP32D-NEXT: addi a1, a0, %lo(var) ; ILP32D-NEXT: flw ft4, 16(a1) ; ILP32D-NEXT: flw ft5, 20(a1) ; ILP32D-NEXT: flw ft6, 24(a1) @@ -433,7 +433,7 @@ ; ILP32D-NEXT: fsw ft3, %lo(var+12)(a0) ; ILP32D-NEXT: fsw ft2, %lo(var+8)(a0) ; ILP32D-NEXT: fsw ft1, %lo(var+4)(a0) -; ILP32D-NEXT: fsw ft0, %lo(var)(a0) +; ILP32D-NEXT: fsw ft0, 0(a1) ; ILP32D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload @@ -465,11 +465,11 @@ ; LP64D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill ; LP64D-NEXT: lui a0, %hi(var) -; LP64D-NEXT: flw ft0, %lo(var)(a0) +; LP64D-NEXT: addi a1, a0, %lo(var) +; LP64D-NEXT: flw ft0, 0(a1) ; LP64D-NEXT: flw ft1, %lo(var+4)(a0) ; LP64D-NEXT: flw ft2, %lo(var+8)(a0) ; LP64D-NEXT: flw ft3, %lo(var+12)(a0) -; LP64D-NEXT: addi a1, a0, %lo(var) ; LP64D-NEXT: flw ft4, 16(a1) ; LP64D-NEXT: flw ft5, 20(a1) ; LP64D-NEXT: flw ft6, 24(a1) @@ -529,7 +529,7 @@ ; LP64D-NEXT: fsw ft3, %lo(var+12)(a0) ; LP64D-NEXT: fsw ft2, %lo(var+8)(a0) ; LP64D-NEXT: fsw ft1, %lo(var+4)(a0) -; LP64D-NEXT: fsw ft0, %lo(var)(a0) +; LP64D-NEXT: fsw ft0, 0(a1) ; LP64D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload @@ -564,7 +564,8 @@ ; ILP32-NEXT: sw s0, 136(sp) # 4-byte Folded Spill ; ILP32-NEXT: sw s1, 132(sp) # 4-byte Folded Spill ; ILP32-NEXT: lui s0, %hi(var) -; ILP32-NEXT: flw ft0, %lo(var)(s0) +; ILP32-NEXT: addi s1, s0, %lo(var) +; ILP32-NEXT: flw ft0, 0(s1) ; ILP32-NEXT: fsw ft0, 128(sp) # 4-byte Folded Spill ; ILP32-NEXT: flw ft0, %lo(var+4)(s0) ; ILP32-NEXT: fsw ft0, 124(sp) # 4-byte Folded Spill @@ -572,7 +573,6 @@ ; ILP32-NEXT: fsw ft0, 120(sp) # 4-byte Folded Spill ; ILP32-NEXT: flw ft0, %lo(var+12)(s0) ; ILP32-NEXT: fsw ft0, 116(sp) # 4-byte Folded Spill -; ILP32-NEXT: addi s1, s0, %lo(var) ; ILP32-NEXT: flw ft0, 16(s1) ; ILP32-NEXT: fsw ft0, 112(sp) # 4-byte Folded Spill ; ILP32-NEXT: flw ft0, 20(s1) @@ -693,7 +693,7 @@ ; ILP32-NEXT: flw ft0, 124(sp) # 4-byte Folded Reload ; ILP32-NEXT: fsw ft0, %lo(var+4)(s0) ; ILP32-NEXT: flw ft0, 128(sp) # 4-byte Folded Reload -; ILP32-NEXT: fsw ft0, %lo(var)(s0) +; ILP32-NEXT: fsw ft0, 0(s1) ; ILP32-NEXT: lw ra, 140(sp) # 4-byte Folded Reload ; ILP32-NEXT: lw s0, 136(sp) # 4-byte Folded Reload ; ILP32-NEXT: lw s1, 132(sp) # 4-byte Folded Reload @@ -707,7 +707,8 @@ ; LP64-NEXT: sd s0, 144(sp) # 8-byte Folded Spill ; LP64-NEXT: sd s1, 136(sp) # 8-byte Folded Spill ; LP64-NEXT: lui s0, %hi(var) -; LP64-NEXT: flw ft0, %lo(var)(s0) +; LP64-NEXT: addi s1, s0, %lo(var) +; LP64-NEXT: flw ft0, 0(s1) ; LP64-NEXT: fsw ft0, 132(sp) # 4-byte Folded Spill ; LP64-NEXT: flw ft0, %lo(var+4)(s0) ; LP64-NEXT: fsw ft0, 128(sp) # 4-byte Folded Spill @@ -715,7 +716,6 @@ ; LP64-NEXT: fsw ft0, 124(sp) # 4-byte Folded Spill ; LP64-NEXT: flw ft0, %lo(var+12)(s0) ; LP64-NEXT: fsw ft0, 120(sp) # 4-byte Folded Spill -; LP64-NEXT: addi s1, s0, %lo(var) ; LP64-NEXT: flw ft0, 16(s1) ; LP64-NEXT: fsw ft0, 116(sp) # 4-byte Folded Spill ; LP64-NEXT: flw ft0, 20(s1) @@ -836,7 +836,7 @@ ; LP64-NEXT: flw ft0, 128(sp) # 4-byte Folded Reload ; LP64-NEXT: fsw ft0, %lo(var+4)(s0) ; LP64-NEXT: flw ft0, 132(sp) # 4-byte Folded Reload -; LP64-NEXT: fsw ft0, %lo(var)(s0) +; LP64-NEXT: fsw ft0, 0(s1) ; LP64-NEXT: ld ra, 152(sp) # 8-byte Folded Reload ; LP64-NEXT: ld s0, 144(sp) # 8-byte Folded Reload ; LP64-NEXT: ld s1, 136(sp) # 8-byte Folded Reload @@ -862,7 +862,8 @@ ; ILP32F-NEXT: fsw fs10, 88(sp) # 4-byte Folded Spill ; ILP32F-NEXT: fsw fs11, 84(sp) # 4-byte Folded Spill ; ILP32F-NEXT: lui s0, %hi(var) -; ILP32F-NEXT: flw ft0, %lo(var)(s0) +; ILP32F-NEXT: addi s1, s0, %lo(var) +; ILP32F-NEXT: flw ft0, 0(s1) ; ILP32F-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill ; ILP32F-NEXT: flw ft0, %lo(var+4)(s0) ; ILP32F-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill @@ -870,7 +871,6 @@ ; ILP32F-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill ; ILP32F-NEXT: flw ft0, %lo(var+12)(s0) ; ILP32F-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill -; ILP32F-NEXT: addi s1, s0, %lo(var) ; ILP32F-NEXT: flw ft0, 16(s1) ; ILP32F-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill ; ILP32F-NEXT: flw ft0, 20(s1) @@ -967,7 +967,7 @@ ; ILP32F-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload ; ILP32F-NEXT: fsw ft0, %lo(var+4)(s0) ; ILP32F-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload -; ILP32F-NEXT: fsw ft0, %lo(var)(s0) +; ILP32F-NEXT: fsw ft0, 0(s1) ; ILP32F-NEXT: lw ra, 140(sp) # 4-byte Folded Reload ; ILP32F-NEXT: lw s0, 136(sp) # 4-byte Folded Reload ; ILP32F-NEXT: lw s1, 132(sp) # 4-byte Folded Reload @@ -1005,7 +1005,8 @@ ; LP64F-NEXT: fsw fs10, 92(sp) # 4-byte Folded Spill ; LP64F-NEXT: fsw fs11, 88(sp) # 4-byte Folded Spill ; LP64F-NEXT: lui s0, %hi(var) -; LP64F-NEXT: flw ft0, %lo(var)(s0) +; LP64F-NEXT: addi s1, s0, %lo(var) +; LP64F-NEXT: flw ft0, 0(s1) ; LP64F-NEXT: fsw ft0, 84(sp) # 4-byte Folded Spill ; LP64F-NEXT: flw ft0, %lo(var+4)(s0) ; LP64F-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill @@ -1013,7 +1014,6 @@ ; LP64F-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill ; LP64F-NEXT: flw ft0, %lo(var+12)(s0) ; LP64F-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill -; LP64F-NEXT: addi s1, s0, %lo(var) ; LP64F-NEXT: flw ft0, 16(s1) ; LP64F-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill ; LP64F-NEXT: flw ft0, 20(s1) @@ -1110,7 +1110,7 @@ ; LP64F-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload ; LP64F-NEXT: fsw ft0, %lo(var+4)(s0) ; LP64F-NEXT: flw ft0, 84(sp) # 4-byte Folded Reload -; LP64F-NEXT: fsw ft0, %lo(var)(s0) +; LP64F-NEXT: fsw ft0, 0(s1) ; LP64F-NEXT: ld ra, 152(sp) # 8-byte Folded Reload ; LP64F-NEXT: ld s0, 144(sp) # 8-byte Folded Reload ; LP64F-NEXT: ld s1, 136(sp) # 8-byte Folded Reload @@ -1148,7 +1148,8 @@ ; ILP32D-NEXT: fsd fs10, 88(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs11, 80(sp) # 8-byte Folded Spill ; ILP32D-NEXT: lui s0, %hi(var) -; ILP32D-NEXT: flw ft0, %lo(var)(s0) +; ILP32D-NEXT: addi s1, s0, %lo(var) +; ILP32D-NEXT: flw ft0, 0(s1) ; ILP32D-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill ; ILP32D-NEXT: flw ft0, %lo(var+4)(s0) ; ILP32D-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill @@ -1156,7 +1157,6 @@ ; ILP32D-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill ; ILP32D-NEXT: flw ft0, %lo(var+12)(s0) ; ILP32D-NEXT: fsw ft0, 64(sp) # 4-byte Folded Spill -; ILP32D-NEXT: addi s1, s0, %lo(var) ; ILP32D-NEXT: flw ft0, 16(s1) ; ILP32D-NEXT: fsw ft0, 60(sp) # 4-byte Folded Spill ; ILP32D-NEXT: flw ft0, 20(s1) @@ -1253,7 +1253,7 @@ ; ILP32D-NEXT: flw ft0, 72(sp) # 4-byte Folded Reload ; ILP32D-NEXT: fsw ft0, %lo(var+4)(s0) ; ILP32D-NEXT: flw ft0, 76(sp) # 4-byte Folded Reload -; ILP32D-NEXT: fsw ft0, %lo(var)(s0) +; ILP32D-NEXT: fsw ft0, 0(s1) ; ILP32D-NEXT: lw ra, 188(sp) # 4-byte Folded Reload ; ILP32D-NEXT: lw s0, 184(sp) # 4-byte Folded Reload ; ILP32D-NEXT: lw s1, 180(sp) # 4-byte Folded Reload @@ -1291,7 +1291,8 @@ ; LP64D-NEXT: fsd fs10, 96(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs11, 88(sp) # 8-byte Folded Spill ; LP64D-NEXT: lui s0, %hi(var) -; LP64D-NEXT: flw ft0, %lo(var)(s0) +; LP64D-NEXT: addi s1, s0, %lo(var) +; LP64D-NEXT: flw ft0, 0(s1) ; LP64D-NEXT: fsw ft0, 84(sp) # 4-byte Folded Spill ; LP64D-NEXT: flw ft0, %lo(var+4)(s0) ; LP64D-NEXT: fsw ft0, 80(sp) # 4-byte Folded Spill @@ -1299,7 +1300,6 @@ ; LP64D-NEXT: fsw ft0, 76(sp) # 4-byte Folded Spill ; LP64D-NEXT: flw ft0, %lo(var+12)(s0) ; LP64D-NEXT: fsw ft0, 72(sp) # 4-byte Folded Spill -; LP64D-NEXT: addi s1, s0, %lo(var) ; LP64D-NEXT: flw ft0, 16(s1) ; LP64D-NEXT: fsw ft0, 68(sp) # 4-byte Folded Spill ; LP64D-NEXT: flw ft0, 20(s1) @@ -1396,7 +1396,7 @@ ; LP64D-NEXT: flw ft0, 80(sp) # 4-byte Folded Reload ; LP64D-NEXT: fsw ft0, %lo(var+4)(s0) ; LP64D-NEXT: flw ft0, 84(sp) # 4-byte Folded Reload -; LP64D-NEXT: fsw ft0, %lo(var)(s0) +; LP64D-NEXT: fsw ft0, 0(s1) ; LP64D-NEXT: ld ra, 200(sp) # 8-byte Folded Reload ; LP64D-NEXT: ld s0, 192(sp) # 8-byte Folded Reload ; LP64D-NEXT: ld s1, 184(sp) # 8-byte Folded Reload Index: llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll =================================================================== --- llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll +++ llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll @@ -20,9 +20,9 @@ ; ILP32-LABEL: callee: ; ILP32: # %bb.0: ; ILP32-NEXT: lui a0, %hi(var) -; ILP32-NEXT: fld ft0, %lo(var)(a0) -; ILP32-NEXT: fld ft1, %lo(var+8)(a0) ; ILP32-NEXT: addi a1, a0, %lo(var) +; ILP32-NEXT: fld ft0, 0(a1) +; ILP32-NEXT: fld ft1, %lo(var+8)(a0) ; ILP32-NEXT: fld ft2, 16(a1) ; ILP32-NEXT: fld ft3, 24(a1) ; ILP32-NEXT: fld ft4, 32(a1) @@ -84,15 +84,15 @@ ; ILP32-NEXT: fsd ft3, 24(a1) ; ILP32-NEXT: fsd ft2, 16(a1) ; ILP32-NEXT: fsd ft1, %lo(var+8)(a0) -; ILP32-NEXT: fsd ft0, %lo(var)(a0) +; ILP32-NEXT: fsd ft0, 0(a1) ; ILP32-NEXT: ret ; ; LP64-LABEL: callee: ; LP64: # %bb.0: ; LP64-NEXT: lui a0, %hi(var) -; LP64-NEXT: fld ft0, %lo(var)(a0) -; LP64-NEXT: fld ft1, %lo(var+8)(a0) ; LP64-NEXT: addi a1, a0, %lo(var) +; LP64-NEXT: fld ft0, 0(a1) +; LP64-NEXT: fld ft1, %lo(var+8)(a0) ; LP64-NEXT: fld ft2, 16(a1) ; LP64-NEXT: fld ft3, 24(a1) ; LP64-NEXT: fld ft4, 32(a1) @@ -154,7 +154,7 @@ ; LP64-NEXT: fsd ft3, 24(a1) ; LP64-NEXT: fsd ft2, 16(a1) ; LP64-NEXT: fsd ft1, %lo(var+8)(a0) -; LP64-NEXT: fsd ft0, %lo(var)(a0) +; LP64-NEXT: fsd ft0, 0(a1) ; LP64-NEXT: ret ; ; ILP32D-LABEL: callee: @@ -173,9 +173,9 @@ ; ILP32D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill ; ILP32D-NEXT: lui a0, %hi(var) -; ILP32D-NEXT: fld ft0, %lo(var)(a0) -; ILP32D-NEXT: fld ft1, %lo(var+8)(a0) ; ILP32D-NEXT: addi a1, a0, %lo(var) +; ILP32D-NEXT: fld ft0, 0(a1) +; ILP32D-NEXT: fld ft1, %lo(var+8)(a0) ; ILP32D-NEXT: fld ft2, 16(a1) ; ILP32D-NEXT: fld ft3, 24(a1) ; ILP32D-NEXT: fld ft4, 32(a1) @@ -237,7 +237,7 @@ ; ILP32D-NEXT: fsd ft3, 24(a1) ; ILP32D-NEXT: fsd ft2, 16(a1) ; ILP32D-NEXT: fsd ft1, %lo(var+8)(a0) -; ILP32D-NEXT: fsd ft0, %lo(var)(a0) +; ILP32D-NEXT: fsd ft0, 0(a1) ; ILP32D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload @@ -269,9 +269,9 @@ ; LP64D-NEXT: fsd fs10, 8(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs11, 0(sp) # 8-byte Folded Spill ; LP64D-NEXT: lui a0, %hi(var) -; LP64D-NEXT: fld ft0, %lo(var)(a0) -; LP64D-NEXT: fld ft1, %lo(var+8)(a0) ; LP64D-NEXT: addi a1, a0, %lo(var) +; LP64D-NEXT: fld ft0, 0(a1) +; LP64D-NEXT: fld ft1, %lo(var+8)(a0) ; LP64D-NEXT: fld ft2, 16(a1) ; LP64D-NEXT: fld ft3, 24(a1) ; LP64D-NEXT: fld ft4, 32(a1) @@ -333,7 +333,7 @@ ; LP64D-NEXT: fsd ft3, 24(a1) ; LP64D-NEXT: fsd ft2, 16(a1) ; LP64D-NEXT: fsd ft1, %lo(var+8)(a0) -; LP64D-NEXT: fsd ft0, %lo(var)(a0) +; LP64D-NEXT: fsd ft0, 0(a1) ; LP64D-NEXT: fld fs0, 88(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs1, 80(sp) # 8-byte Folded Reload ; LP64D-NEXT: fld fs2, 72(sp) # 8-byte Folded Reload @@ -368,11 +368,11 @@ ; ILP32-NEXT: sw s0, 264(sp) # 4-byte Folded Spill ; ILP32-NEXT: sw s1, 260(sp) # 4-byte Folded Spill ; ILP32-NEXT: lui s0, %hi(var) -; ILP32-NEXT: fld ft0, %lo(var)(s0) +; ILP32-NEXT: addi s1, s0, %lo(var) +; ILP32-NEXT: fld ft0, 0(s1) ; ILP32-NEXT: fsd ft0, 248(sp) # 8-byte Folded Spill ; ILP32-NEXT: fld ft0, %lo(var+8)(s0) ; ILP32-NEXT: fsd ft0, 240(sp) # 8-byte Folded Spill -; ILP32-NEXT: addi s1, s0, %lo(var) ; ILP32-NEXT: fld ft0, 16(s1) ; ILP32-NEXT: fsd ft0, 232(sp) # 8-byte Folded Spill ; ILP32-NEXT: fld ft0, 24(s1) @@ -497,7 +497,7 @@ ; ILP32-NEXT: fld ft0, 240(sp) # 8-byte Folded Reload ; ILP32-NEXT: fsd ft0, %lo(var+8)(s0) ; ILP32-NEXT: fld ft0, 248(sp) # 8-byte Folded Reload -; ILP32-NEXT: fsd ft0, %lo(var)(s0) +; ILP32-NEXT: fsd ft0, 0(s1) ; ILP32-NEXT: lw ra, 268(sp) # 4-byte Folded Reload ; ILP32-NEXT: lw s0, 264(sp) # 4-byte Folded Reload ; ILP32-NEXT: lw s1, 260(sp) # 4-byte Folded Reload @@ -511,11 +511,11 @@ ; LP64-NEXT: sd s0, 272(sp) # 8-byte Folded Spill ; LP64-NEXT: sd s1, 264(sp) # 8-byte Folded Spill ; LP64-NEXT: lui s0, %hi(var) -; LP64-NEXT: fld ft0, %lo(var)(s0) +; LP64-NEXT: addi s1, s0, %lo(var) +; LP64-NEXT: fld ft0, 0(s1) ; LP64-NEXT: fsd ft0, 256(sp) # 8-byte Folded Spill ; LP64-NEXT: fld ft0, %lo(var+8)(s0) ; LP64-NEXT: fsd ft0, 248(sp) # 8-byte Folded Spill -; LP64-NEXT: addi s1, s0, %lo(var) ; LP64-NEXT: fld ft0, 16(s1) ; LP64-NEXT: fsd ft0, 240(sp) # 8-byte Folded Spill ; LP64-NEXT: fld ft0, 24(s1) @@ -640,7 +640,7 @@ ; LP64-NEXT: fld ft0, 248(sp) # 8-byte Folded Reload ; LP64-NEXT: fsd ft0, %lo(var+8)(s0) ; LP64-NEXT: fld ft0, 256(sp) # 8-byte Folded Reload -; LP64-NEXT: fsd ft0, %lo(var)(s0) +; LP64-NEXT: fsd ft0, 0(s1) ; LP64-NEXT: ld ra, 280(sp) # 8-byte Folded Reload ; LP64-NEXT: ld s0, 272(sp) # 8-byte Folded Reload ; LP64-NEXT: ld s1, 264(sp) # 8-byte Folded Reload @@ -666,11 +666,11 @@ ; ILP32D-NEXT: fsd fs10, 168(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fsd fs11, 160(sp) # 8-byte Folded Spill ; ILP32D-NEXT: lui s0, %hi(var) -; ILP32D-NEXT: fld ft0, %lo(var)(s0) +; ILP32D-NEXT: addi s1, s0, %lo(var) +; ILP32D-NEXT: fld ft0, 0(s1) ; ILP32D-NEXT: fsd ft0, 152(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fld ft0, %lo(var+8)(s0) ; ILP32D-NEXT: fsd ft0, 144(sp) # 8-byte Folded Spill -; ILP32D-NEXT: addi s1, s0, %lo(var) ; ILP32D-NEXT: fld ft0, 16(s1) ; ILP32D-NEXT: fsd ft0, 136(sp) # 8-byte Folded Spill ; ILP32D-NEXT: fld ft0, 24(s1) @@ -771,7 +771,7 @@ ; ILP32D-NEXT: fld ft0, 144(sp) # 8-byte Folded Reload ; ILP32D-NEXT: fsd ft0, %lo(var+8)(s0) ; ILP32D-NEXT: fld ft0, 152(sp) # 8-byte Folded Reload -; ILP32D-NEXT: fsd ft0, %lo(var)(s0) +; ILP32D-NEXT: fsd ft0, 0(s1) ; ILP32D-NEXT: lw ra, 268(sp) # 4-byte Folded Reload ; ILP32D-NEXT: lw s0, 264(sp) # 4-byte Folded Reload ; ILP32D-NEXT: lw s1, 260(sp) # 4-byte Folded Reload @@ -809,11 +809,11 @@ ; LP64D-NEXT: fsd fs10, 176(sp) # 8-byte Folded Spill ; LP64D-NEXT: fsd fs11, 168(sp) # 8-byte Folded Spill ; LP64D-NEXT: lui s0, %hi(var) -; LP64D-NEXT: fld ft0, %lo(var)(s0) +; LP64D-NEXT: addi s1, s0, %lo(var) +; LP64D-NEXT: fld ft0, 0(s1) ; LP64D-NEXT: fsd ft0, 160(sp) # 8-byte Folded Spill ; LP64D-NEXT: fld ft0, %lo(var+8)(s0) ; LP64D-NEXT: fsd ft0, 152(sp) # 8-byte Folded Spill -; LP64D-NEXT: addi s1, s0, %lo(var) ; LP64D-NEXT: fld ft0, 16(s1) ; LP64D-NEXT: fsd ft0, 144(sp) # 8-byte Folded Spill ; LP64D-NEXT: fld ft0, 24(s1) @@ -914,7 +914,7 @@ ; LP64D-NEXT: fld ft0, 152(sp) # 8-byte Folded Reload ; LP64D-NEXT: fsd ft0, %lo(var+8)(s0) ; LP64D-NEXT: fld ft0, 160(sp) # 8-byte Folded Reload -; LP64D-NEXT: fsd ft0, %lo(var)(s0) +; LP64D-NEXT: fsd ft0, 0(s1) ; LP64D-NEXT: ld ra, 280(sp) # 8-byte Folded Reload ; LP64D-NEXT: ld s0, 272(sp) # 8-byte Folded Reload ; LP64D-NEXT: ld s1, 264(sp) # 8-byte Folded Reload Index: llvm/test/CodeGen/RISCV/callee-saved-gprs.ll =================================================================== --- llvm/test/CodeGen/RISCV/callee-saved-gprs.ll +++ llvm/test/CodeGen/RISCV/callee-saved-gprs.ll @@ -43,7 +43,8 @@ ; RV32I-NEXT: sw s10, 32(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s11, 28(sp) # 4-byte Folded Spill ; RV32I-NEXT: lui a7, %hi(var) -; RV32I-NEXT: lw a0, %lo(var)(a7) +; RV32I-NEXT: addi a1, a7, %lo(var) +; RV32I-NEXT: lw a0, 0(a1) ; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a0, %lo(var+4)(a7) ; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill @@ -51,67 +52,66 @@ ; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a0, %lo(var+12)(a7) ; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: addi a5, a7, %lo(var) -; RV32I-NEXT: lw a0, 16(a5) +; RV32I-NEXT: lw a0, 16(a1) ; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 20(a5) +; RV32I-NEXT: lw a0, 20(a1) ; RV32I-NEXT: sw a0, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw t0, 24(a5) -; RV32I-NEXT: lw t1, 28(a5) -; RV32I-NEXT: lw t2, 32(a5) -; RV32I-NEXT: lw t3, 36(a5) -; RV32I-NEXT: lw t4, 40(a5) -; RV32I-NEXT: lw t5, 44(a5) -; RV32I-NEXT: lw t6, 48(a5) -; RV32I-NEXT: lw s0, 52(a5) -; RV32I-NEXT: lw s1, 56(a5) -; RV32I-NEXT: lw s2, 60(a5) -; RV32I-NEXT: lw s3, 64(a5) -; RV32I-NEXT: lw s4, 68(a5) -; RV32I-NEXT: lw s5, 72(a5) -; RV32I-NEXT: lw s6, 76(a5) -; RV32I-NEXT: lw s7, 80(a5) -; RV32I-NEXT: lw s8, 84(a5) -; RV32I-NEXT: lw s9, 88(a5) -; RV32I-NEXT: lw s10, 92(a5) -; RV32I-NEXT: lw s11, 96(a5) -; RV32I-NEXT: lw ra, 100(a5) -; RV32I-NEXT: lw a6, 104(a5) -; RV32I-NEXT: lw a4, 108(a5) -; RV32I-NEXT: lw a0, 124(a5) -; RV32I-NEXT: lw a1, 120(a5) -; RV32I-NEXT: lw a2, 116(a5) -; RV32I-NEXT: lw a3, 112(a5) -; RV32I-NEXT: sw a0, 124(a5) -; RV32I-NEXT: sw a1, 120(a5) -; RV32I-NEXT: sw a2, 116(a5) -; RV32I-NEXT: sw a3, 112(a5) -; RV32I-NEXT: sw a4, 108(a5) -; RV32I-NEXT: sw a6, 104(a5) -; RV32I-NEXT: sw ra, 100(a5) -; RV32I-NEXT: sw s11, 96(a5) -; RV32I-NEXT: sw s10, 92(a5) -; RV32I-NEXT: sw s9, 88(a5) -; RV32I-NEXT: sw s8, 84(a5) -; RV32I-NEXT: sw s7, 80(a5) -; RV32I-NEXT: sw s6, 76(a5) -; RV32I-NEXT: sw s5, 72(a5) -; RV32I-NEXT: sw s4, 68(a5) -; RV32I-NEXT: sw s3, 64(a5) -; RV32I-NEXT: sw s2, 60(a5) -; RV32I-NEXT: sw s1, 56(a5) -; RV32I-NEXT: sw s0, 52(a5) -; RV32I-NEXT: sw t6, 48(a5) -; RV32I-NEXT: sw t5, 44(a5) -; RV32I-NEXT: sw t4, 40(a5) -; RV32I-NEXT: sw t3, 36(a5) -; RV32I-NEXT: sw t2, 32(a5) -; RV32I-NEXT: sw t1, 28(a5) -; RV32I-NEXT: sw t0, 24(a5) +; RV32I-NEXT: lw t0, 24(a1) +; RV32I-NEXT: lw t1, 28(a1) +; RV32I-NEXT: lw t2, 32(a1) +; RV32I-NEXT: lw t3, 36(a1) +; RV32I-NEXT: lw t4, 40(a1) +; RV32I-NEXT: lw t5, 44(a1) +; RV32I-NEXT: lw t6, 48(a1) +; RV32I-NEXT: lw s0, 52(a1) +; RV32I-NEXT: lw s1, 56(a1) +; RV32I-NEXT: lw s2, 60(a1) +; RV32I-NEXT: lw s3, 64(a1) +; RV32I-NEXT: lw s4, 68(a1) +; RV32I-NEXT: lw s5, 72(a1) +; RV32I-NEXT: lw s6, 76(a1) +; RV32I-NEXT: lw s7, 80(a1) +; RV32I-NEXT: lw s8, 84(a1) +; RV32I-NEXT: lw s9, 88(a1) +; RV32I-NEXT: lw s10, 92(a1) +; RV32I-NEXT: lw s11, 96(a1) +; RV32I-NEXT: lw ra, 100(a1) +; RV32I-NEXT: lw a6, 104(a1) +; RV32I-NEXT: lw a5, 108(a1) +; RV32I-NEXT: lw a0, 124(a1) +; RV32I-NEXT: lw a2, 120(a1) +; RV32I-NEXT: lw a3, 116(a1) +; RV32I-NEXT: lw a4, 112(a1) +; RV32I-NEXT: sw a0, 124(a1) +; RV32I-NEXT: sw a2, 120(a1) +; RV32I-NEXT: sw a3, 116(a1) +; RV32I-NEXT: sw a4, 112(a1) +; RV32I-NEXT: sw a5, 108(a1) +; RV32I-NEXT: sw a6, 104(a1) +; RV32I-NEXT: sw ra, 100(a1) +; RV32I-NEXT: sw s11, 96(a1) +; RV32I-NEXT: sw s10, 92(a1) +; RV32I-NEXT: sw s9, 88(a1) +; RV32I-NEXT: sw s8, 84(a1) +; RV32I-NEXT: sw s7, 80(a1) +; RV32I-NEXT: sw s6, 76(a1) +; RV32I-NEXT: sw s5, 72(a1) +; RV32I-NEXT: sw s4, 68(a1) +; RV32I-NEXT: sw s3, 64(a1) +; RV32I-NEXT: sw s2, 60(a1) +; RV32I-NEXT: sw s1, 56(a1) +; RV32I-NEXT: sw s0, 52(a1) +; RV32I-NEXT: sw t6, 48(a1) +; RV32I-NEXT: sw t5, 44(a1) +; RV32I-NEXT: sw t4, 40(a1) +; RV32I-NEXT: sw t3, 36(a1) +; RV32I-NEXT: sw t2, 32(a1) +; RV32I-NEXT: sw t1, 28(a1) +; RV32I-NEXT: sw t0, 24(a1) ; RV32I-NEXT: lw a0, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 20(a5) +; RV32I-NEXT: sw a0, 20(a1) ; RV32I-NEXT: lw a0, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 16(a5) +; RV32I-NEXT: sw a0, 16(a1) ; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: sw a0, %lo(var+12)(a7) ; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload @@ -119,7 +119,7 @@ ; RV32I-NEXT: lw a0, 20(sp) # 4-byte Folded Reload ; RV32I-NEXT: sw a0, %lo(var+4)(a7) ; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, %lo(var)(a7) +; RV32I-NEXT: sw a0, 0(a1) ; RV32I-NEXT: lw ra, 76(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 72(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 68(sp) # 4-byte Folded Reload @@ -153,86 +153,86 @@ ; RV32I-WITH-FP-NEXT: sw s10, 32(sp) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: sw s11, 28(sp) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: addi s0, sp, 80 -; RV32I-WITH-FP-NEXT: lui a7, %hi(var) -; RV32I-WITH-FP-NEXT: lw a0, %lo(var)(a7) +; RV32I-WITH-FP-NEXT: lui t0, %hi(var) +; RV32I-WITH-FP-NEXT: addi a1, t0, %lo(var) +; RV32I-WITH-FP-NEXT: lw a0, 0(a1) ; RV32I-WITH-FP-NEXT: sw a0, -56(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, %lo(var+4)(a7) +; RV32I-WITH-FP-NEXT: lw a0, %lo(var+4)(t0) ; RV32I-WITH-FP-NEXT: sw a0, -60(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, %lo(var+8)(a7) +; RV32I-WITH-FP-NEXT: lw a0, %lo(var+8)(t0) ; RV32I-WITH-FP-NEXT: sw a0, -64(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, %lo(var+12)(a7) +; RV32I-WITH-FP-NEXT: lw a0, %lo(var+12)(t0) ; RV32I-WITH-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: addi a5, a7, %lo(var) -; RV32I-WITH-FP-NEXT: lw a0, 16(a5) +; RV32I-WITH-FP-NEXT: lw a0, 16(a1) ; RV32I-WITH-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 20(a5) +; RV32I-WITH-FP-NEXT: lw a0, 20(a1) ; RV32I-WITH-FP-NEXT: sw a0, -76(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 24(a5) +; RV32I-WITH-FP-NEXT: lw a0, 24(a1) ; RV32I-WITH-FP-NEXT: sw a0, -80(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw t1, 28(a5) -; RV32I-WITH-FP-NEXT: lw t2, 32(a5) -; RV32I-WITH-FP-NEXT: lw t3, 36(a5) -; RV32I-WITH-FP-NEXT: lw t4, 40(a5) -; RV32I-WITH-FP-NEXT: lw t5, 44(a5) -; RV32I-WITH-FP-NEXT: lw t6, 48(a5) -; RV32I-WITH-FP-NEXT: lw s1, 52(a5) -; RV32I-WITH-FP-NEXT: lw s2, 56(a5) -; RV32I-WITH-FP-NEXT: lw s3, 60(a5) -; RV32I-WITH-FP-NEXT: lw s4, 64(a5) -; RV32I-WITH-FP-NEXT: lw s5, 68(a5) -; RV32I-WITH-FP-NEXT: lw s6, 72(a5) -; RV32I-WITH-FP-NEXT: lw s7, 76(a5) -; RV32I-WITH-FP-NEXT: lw s8, 80(a5) -; RV32I-WITH-FP-NEXT: lw s9, 84(a5) -; RV32I-WITH-FP-NEXT: lw s10, 88(a5) -; RV32I-WITH-FP-NEXT: lw s11, 92(a5) -; RV32I-WITH-FP-NEXT: lw ra, 96(a5) -; RV32I-WITH-FP-NEXT: lw t0, 100(a5) -; RV32I-WITH-FP-NEXT: lw a6, 104(a5) -; RV32I-WITH-FP-NEXT: lw a4, 108(a5) -; RV32I-WITH-FP-NEXT: lw a0, 124(a5) -; RV32I-WITH-FP-NEXT: lw a1, 120(a5) -; RV32I-WITH-FP-NEXT: lw a2, 116(a5) -; RV32I-WITH-FP-NEXT: lw a3, 112(a5) -; RV32I-WITH-FP-NEXT: sw a0, 124(a5) -; RV32I-WITH-FP-NEXT: sw a1, 120(a5) -; RV32I-WITH-FP-NEXT: sw a2, 116(a5) -; RV32I-WITH-FP-NEXT: sw a3, 112(a5) -; RV32I-WITH-FP-NEXT: sw a4, 108(a5) -; RV32I-WITH-FP-NEXT: sw a6, 104(a5) -; RV32I-WITH-FP-NEXT: sw t0, 100(a5) -; RV32I-WITH-FP-NEXT: sw ra, 96(a5) -; RV32I-WITH-FP-NEXT: sw s11, 92(a5) -; RV32I-WITH-FP-NEXT: sw s10, 88(a5) -; RV32I-WITH-FP-NEXT: sw s9, 84(a5) -; RV32I-WITH-FP-NEXT: sw s8, 80(a5) -; RV32I-WITH-FP-NEXT: sw s7, 76(a5) -; RV32I-WITH-FP-NEXT: sw s6, 72(a5) -; RV32I-WITH-FP-NEXT: sw s5, 68(a5) -; RV32I-WITH-FP-NEXT: sw s4, 64(a5) -; RV32I-WITH-FP-NEXT: sw s3, 60(a5) -; RV32I-WITH-FP-NEXT: sw s2, 56(a5) -; RV32I-WITH-FP-NEXT: sw s1, 52(a5) -; RV32I-WITH-FP-NEXT: sw t6, 48(a5) -; RV32I-WITH-FP-NEXT: sw t5, 44(a5) -; RV32I-WITH-FP-NEXT: sw t4, 40(a5) -; RV32I-WITH-FP-NEXT: sw t3, 36(a5) -; RV32I-WITH-FP-NEXT: sw t2, 32(a5) -; RV32I-WITH-FP-NEXT: sw t1, 28(a5) +; RV32I-WITH-FP-NEXT: lw t1, 28(a1) +; RV32I-WITH-FP-NEXT: lw t2, 32(a1) +; RV32I-WITH-FP-NEXT: lw t3, 36(a1) +; RV32I-WITH-FP-NEXT: lw t4, 40(a1) +; RV32I-WITH-FP-NEXT: lw t5, 44(a1) +; RV32I-WITH-FP-NEXT: lw t6, 48(a1) +; RV32I-WITH-FP-NEXT: lw s1, 52(a1) +; RV32I-WITH-FP-NEXT: lw s2, 56(a1) +; RV32I-WITH-FP-NEXT: lw s3, 60(a1) +; RV32I-WITH-FP-NEXT: lw s4, 64(a1) +; RV32I-WITH-FP-NEXT: lw s5, 68(a1) +; RV32I-WITH-FP-NEXT: lw s6, 72(a1) +; RV32I-WITH-FP-NEXT: lw s7, 76(a1) +; RV32I-WITH-FP-NEXT: lw s8, 80(a1) +; RV32I-WITH-FP-NEXT: lw s9, 84(a1) +; RV32I-WITH-FP-NEXT: lw s10, 88(a1) +; RV32I-WITH-FP-NEXT: lw s11, 92(a1) +; RV32I-WITH-FP-NEXT: lw ra, 96(a1) +; RV32I-WITH-FP-NEXT: lw a7, 100(a1) +; RV32I-WITH-FP-NEXT: lw a6, 104(a1) +; RV32I-WITH-FP-NEXT: lw a5, 108(a1) +; RV32I-WITH-FP-NEXT: lw a0, 124(a1) +; RV32I-WITH-FP-NEXT: lw a2, 120(a1) +; RV32I-WITH-FP-NEXT: lw a3, 116(a1) +; RV32I-WITH-FP-NEXT: lw a4, 112(a1) +; RV32I-WITH-FP-NEXT: sw a0, 124(a1) +; RV32I-WITH-FP-NEXT: sw a2, 120(a1) +; RV32I-WITH-FP-NEXT: sw a3, 116(a1) +; RV32I-WITH-FP-NEXT: sw a4, 112(a1) +; RV32I-WITH-FP-NEXT: sw a5, 108(a1) +; RV32I-WITH-FP-NEXT: sw a6, 104(a1) +; RV32I-WITH-FP-NEXT: sw a7, 100(a1) +; RV32I-WITH-FP-NEXT: sw ra, 96(a1) +; RV32I-WITH-FP-NEXT: sw s11, 92(a1) +; RV32I-WITH-FP-NEXT: sw s10, 88(a1) +; RV32I-WITH-FP-NEXT: sw s9, 84(a1) +; RV32I-WITH-FP-NEXT: sw s8, 80(a1) +; RV32I-WITH-FP-NEXT: sw s7, 76(a1) +; RV32I-WITH-FP-NEXT: sw s6, 72(a1) +; RV32I-WITH-FP-NEXT: sw s5, 68(a1) +; RV32I-WITH-FP-NEXT: sw s4, 64(a1) +; RV32I-WITH-FP-NEXT: sw s3, 60(a1) +; RV32I-WITH-FP-NEXT: sw s2, 56(a1) +; RV32I-WITH-FP-NEXT: sw s1, 52(a1) +; RV32I-WITH-FP-NEXT: sw t6, 48(a1) +; RV32I-WITH-FP-NEXT: sw t5, 44(a1) +; RV32I-WITH-FP-NEXT: sw t4, 40(a1) +; RV32I-WITH-FP-NEXT: sw t3, 36(a1) +; RV32I-WITH-FP-NEXT: sw t2, 32(a1) +; RV32I-WITH-FP-NEXT: sw t1, 28(a1) ; RV32I-WITH-FP-NEXT: lw a0, -80(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 24(a5) +; RV32I-WITH-FP-NEXT: sw a0, 24(a1) ; RV32I-WITH-FP-NEXT: lw a0, -76(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 20(a5) +; RV32I-WITH-FP-NEXT: sw a0, 20(a1) ; RV32I-WITH-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 16(a5) +; RV32I-WITH-FP-NEXT: sw a0, 16(a1) ; RV32I-WITH-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, %lo(var+12)(a7) +; RV32I-WITH-FP-NEXT: sw a0, %lo(var+12)(t0) ; RV32I-WITH-FP-NEXT: lw a0, -64(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, %lo(var+8)(a7) +; RV32I-WITH-FP-NEXT: sw a0, %lo(var+8)(t0) ; RV32I-WITH-FP-NEXT: lw a0, -60(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, %lo(var+4)(a7) +; RV32I-WITH-FP-NEXT: sw a0, %lo(var+4)(t0) ; RV32I-WITH-FP-NEXT: lw a0, -56(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, %lo(var)(a7) +; RV32I-WITH-FP-NEXT: sw a0, 0(a1) ; RV32I-WITH-FP-NEXT: lw ra, 76(sp) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw s0, 72(sp) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw s1, 68(sp) # 4-byte Folded Reload @@ -266,7 +266,8 @@ ; RV64I-NEXT: sd s10, 64(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s11, 56(sp) # 8-byte Folded Spill ; RV64I-NEXT: lui a7, %hi(var) -; RV64I-NEXT: lw a0, %lo(var)(a7) +; RV64I-NEXT: addi a1, a7, %lo(var) +; RV64I-NEXT: lw a0, 0(a1) ; RV64I-NEXT: sd a0, 48(sp) # 8-byte Folded Spill ; RV64I-NEXT: lw a0, %lo(var+4)(a7) ; RV64I-NEXT: sd a0, 40(sp) # 8-byte Folded Spill @@ -274,67 +275,66 @@ ; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill ; RV64I-NEXT: lw a0, %lo(var+12)(a7) ; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill -; RV64I-NEXT: addi a5, a7, %lo(var) -; RV64I-NEXT: lw a0, 16(a5) +; RV64I-NEXT: lw a0, 16(a1) ; RV64I-NEXT: sd a0, 16(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 20(a5) +; RV64I-NEXT: lw a0, 20(a1) ; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw t0, 24(a5) -; RV64I-NEXT: lw t1, 28(a5) -; RV64I-NEXT: lw t2, 32(a5) -; RV64I-NEXT: lw t3, 36(a5) -; RV64I-NEXT: lw t4, 40(a5) -; RV64I-NEXT: lw t5, 44(a5) -; RV64I-NEXT: lw t6, 48(a5) -; RV64I-NEXT: lw s0, 52(a5) -; RV64I-NEXT: lw s1, 56(a5) -; RV64I-NEXT: lw s2, 60(a5) -; RV64I-NEXT: lw s3, 64(a5) -; RV64I-NEXT: lw s4, 68(a5) -; RV64I-NEXT: lw s5, 72(a5) -; RV64I-NEXT: lw s6, 76(a5) -; RV64I-NEXT: lw s7, 80(a5) -; RV64I-NEXT: lw s8, 84(a5) -; RV64I-NEXT: lw s9, 88(a5) -; RV64I-NEXT: lw s10, 92(a5) -; RV64I-NEXT: lw s11, 96(a5) -; RV64I-NEXT: lw ra, 100(a5) -; RV64I-NEXT: lw a6, 104(a5) -; RV64I-NEXT: lw a4, 108(a5) -; RV64I-NEXT: lw a0, 124(a5) -; RV64I-NEXT: lw a1, 120(a5) -; RV64I-NEXT: lw a2, 116(a5) -; RV64I-NEXT: lw a3, 112(a5) -; RV64I-NEXT: sw a0, 124(a5) -; RV64I-NEXT: sw a1, 120(a5) -; RV64I-NEXT: sw a2, 116(a5) -; RV64I-NEXT: sw a3, 112(a5) -; RV64I-NEXT: sw a4, 108(a5) -; RV64I-NEXT: sw a6, 104(a5) -; RV64I-NEXT: sw ra, 100(a5) -; RV64I-NEXT: sw s11, 96(a5) -; RV64I-NEXT: sw s10, 92(a5) -; RV64I-NEXT: sw s9, 88(a5) -; RV64I-NEXT: sw s8, 84(a5) -; RV64I-NEXT: sw s7, 80(a5) -; RV64I-NEXT: sw s6, 76(a5) -; RV64I-NEXT: sw s5, 72(a5) -; RV64I-NEXT: sw s4, 68(a5) -; RV64I-NEXT: sw s3, 64(a5) -; RV64I-NEXT: sw s2, 60(a5) -; RV64I-NEXT: sw s1, 56(a5) -; RV64I-NEXT: sw s0, 52(a5) -; RV64I-NEXT: sw t6, 48(a5) -; RV64I-NEXT: sw t5, 44(a5) -; RV64I-NEXT: sw t4, 40(a5) -; RV64I-NEXT: sw t3, 36(a5) -; RV64I-NEXT: sw t2, 32(a5) -; RV64I-NEXT: sw t1, 28(a5) -; RV64I-NEXT: sw t0, 24(a5) +; RV64I-NEXT: lw t0, 24(a1) +; RV64I-NEXT: lw t1, 28(a1) +; RV64I-NEXT: lw t2, 32(a1) +; RV64I-NEXT: lw t3, 36(a1) +; RV64I-NEXT: lw t4, 40(a1) +; RV64I-NEXT: lw t5, 44(a1) +; RV64I-NEXT: lw t6, 48(a1) +; RV64I-NEXT: lw s0, 52(a1) +; RV64I-NEXT: lw s1, 56(a1) +; RV64I-NEXT: lw s2, 60(a1) +; RV64I-NEXT: lw s3, 64(a1) +; RV64I-NEXT: lw s4, 68(a1) +; RV64I-NEXT: lw s5, 72(a1) +; RV64I-NEXT: lw s6, 76(a1) +; RV64I-NEXT: lw s7, 80(a1) +; RV64I-NEXT: lw s8, 84(a1) +; RV64I-NEXT: lw s9, 88(a1) +; RV64I-NEXT: lw s10, 92(a1) +; RV64I-NEXT: lw s11, 96(a1) +; RV64I-NEXT: lw ra, 100(a1) +; RV64I-NEXT: lw a6, 104(a1) +; RV64I-NEXT: lw a5, 108(a1) +; RV64I-NEXT: lw a0, 124(a1) +; RV64I-NEXT: lw a2, 120(a1) +; RV64I-NEXT: lw a3, 116(a1) +; RV64I-NEXT: lw a4, 112(a1) +; RV64I-NEXT: sw a0, 124(a1) +; RV64I-NEXT: sw a2, 120(a1) +; RV64I-NEXT: sw a3, 116(a1) +; RV64I-NEXT: sw a4, 112(a1) +; RV64I-NEXT: sw a5, 108(a1) +; RV64I-NEXT: sw a6, 104(a1) +; RV64I-NEXT: sw ra, 100(a1) +; RV64I-NEXT: sw s11, 96(a1) +; RV64I-NEXT: sw s10, 92(a1) +; RV64I-NEXT: sw s9, 88(a1) +; RV64I-NEXT: sw s8, 84(a1) +; RV64I-NEXT: sw s7, 80(a1) +; RV64I-NEXT: sw s6, 76(a1) +; RV64I-NEXT: sw s5, 72(a1) +; RV64I-NEXT: sw s4, 68(a1) +; RV64I-NEXT: sw s3, 64(a1) +; RV64I-NEXT: sw s2, 60(a1) +; RV64I-NEXT: sw s1, 56(a1) +; RV64I-NEXT: sw s0, 52(a1) +; RV64I-NEXT: sw t6, 48(a1) +; RV64I-NEXT: sw t5, 44(a1) +; RV64I-NEXT: sw t4, 40(a1) +; RV64I-NEXT: sw t3, 36(a1) +; RV64I-NEXT: sw t2, 32(a1) +; RV64I-NEXT: sw t1, 28(a1) +; RV64I-NEXT: sw t0, 24(a1) ; RV64I-NEXT: ld a0, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 20(a5) +; RV64I-NEXT: sw a0, 20(a1) ; RV64I-NEXT: ld a0, 16(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 16(a5) +; RV64I-NEXT: sw a0, 16(a1) ; RV64I-NEXT: ld a0, 24(sp) # 8-byte Folded Reload ; RV64I-NEXT: sw a0, %lo(var+12)(a7) ; RV64I-NEXT: ld a0, 32(sp) # 8-byte Folded Reload @@ -342,7 +342,7 @@ ; RV64I-NEXT: ld a0, 40(sp) # 8-byte Folded Reload ; RV64I-NEXT: sw a0, %lo(var+4)(a7) ; RV64I-NEXT: ld a0, 48(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, %lo(var)(a7) +; RV64I-NEXT: sw a0, 0(a1) ; RV64I-NEXT: ld ra, 152(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 144(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 136(sp) # 8-byte Folded Reload @@ -376,86 +376,86 @@ ; RV64I-WITH-FP-NEXT: sd s10, 64(sp) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: sd s11, 56(sp) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: addi s0, sp, 160 -; RV64I-WITH-FP-NEXT: lui a7, %hi(var) -; RV64I-WITH-FP-NEXT: lw a0, %lo(var)(a7) +; RV64I-WITH-FP-NEXT: lui t0, %hi(var) +; RV64I-WITH-FP-NEXT: addi a1, t0, %lo(var) +; RV64I-WITH-FP-NEXT: lw a0, 0(a1) ; RV64I-WITH-FP-NEXT: sd a0, -112(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, %lo(var+4)(a7) +; RV64I-WITH-FP-NEXT: lw a0, %lo(var+4)(t0) ; RV64I-WITH-FP-NEXT: sd a0, -120(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, %lo(var+8)(a7) +; RV64I-WITH-FP-NEXT: lw a0, %lo(var+8)(t0) ; RV64I-WITH-FP-NEXT: sd a0, -128(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, %lo(var+12)(a7) +; RV64I-WITH-FP-NEXT: lw a0, %lo(var+12)(t0) ; RV64I-WITH-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: addi a5, a7, %lo(var) -; RV64I-WITH-FP-NEXT: lw a0, 16(a5) +; RV64I-WITH-FP-NEXT: lw a0, 16(a1) ; RV64I-WITH-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 20(a5) +; RV64I-WITH-FP-NEXT: lw a0, 20(a1) ; RV64I-WITH-FP-NEXT: sd a0, -152(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 24(a5) +; RV64I-WITH-FP-NEXT: lw a0, 24(a1) ; RV64I-WITH-FP-NEXT: sd a0, -160(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw t1, 28(a5) -; RV64I-WITH-FP-NEXT: lw t2, 32(a5) -; RV64I-WITH-FP-NEXT: lw t3, 36(a5) -; RV64I-WITH-FP-NEXT: lw t4, 40(a5) -; RV64I-WITH-FP-NEXT: lw t5, 44(a5) -; RV64I-WITH-FP-NEXT: lw t6, 48(a5) -; RV64I-WITH-FP-NEXT: lw s1, 52(a5) -; RV64I-WITH-FP-NEXT: lw s2, 56(a5) -; RV64I-WITH-FP-NEXT: lw s3, 60(a5) -; RV64I-WITH-FP-NEXT: lw s4, 64(a5) -; RV64I-WITH-FP-NEXT: lw s5, 68(a5) -; RV64I-WITH-FP-NEXT: lw s6, 72(a5) -; RV64I-WITH-FP-NEXT: lw s7, 76(a5) -; RV64I-WITH-FP-NEXT: lw s8, 80(a5) -; RV64I-WITH-FP-NEXT: lw s9, 84(a5) -; RV64I-WITH-FP-NEXT: lw s10, 88(a5) -; RV64I-WITH-FP-NEXT: lw s11, 92(a5) -; RV64I-WITH-FP-NEXT: lw ra, 96(a5) -; RV64I-WITH-FP-NEXT: lw t0, 100(a5) -; RV64I-WITH-FP-NEXT: lw a6, 104(a5) -; RV64I-WITH-FP-NEXT: lw a4, 108(a5) -; RV64I-WITH-FP-NEXT: lw a0, 124(a5) -; RV64I-WITH-FP-NEXT: lw a1, 120(a5) -; RV64I-WITH-FP-NEXT: lw a2, 116(a5) -; RV64I-WITH-FP-NEXT: lw a3, 112(a5) -; RV64I-WITH-FP-NEXT: sw a0, 124(a5) -; RV64I-WITH-FP-NEXT: sw a1, 120(a5) -; RV64I-WITH-FP-NEXT: sw a2, 116(a5) -; RV64I-WITH-FP-NEXT: sw a3, 112(a5) -; RV64I-WITH-FP-NEXT: sw a4, 108(a5) -; RV64I-WITH-FP-NEXT: sw a6, 104(a5) -; RV64I-WITH-FP-NEXT: sw t0, 100(a5) -; RV64I-WITH-FP-NEXT: sw ra, 96(a5) -; RV64I-WITH-FP-NEXT: sw s11, 92(a5) -; RV64I-WITH-FP-NEXT: sw s10, 88(a5) -; RV64I-WITH-FP-NEXT: sw s9, 84(a5) -; RV64I-WITH-FP-NEXT: sw s8, 80(a5) -; RV64I-WITH-FP-NEXT: sw s7, 76(a5) -; RV64I-WITH-FP-NEXT: sw s6, 72(a5) -; RV64I-WITH-FP-NEXT: sw s5, 68(a5) -; RV64I-WITH-FP-NEXT: sw s4, 64(a5) -; RV64I-WITH-FP-NEXT: sw s3, 60(a5) -; RV64I-WITH-FP-NEXT: sw s2, 56(a5) -; RV64I-WITH-FP-NEXT: sw s1, 52(a5) -; RV64I-WITH-FP-NEXT: sw t6, 48(a5) -; RV64I-WITH-FP-NEXT: sw t5, 44(a5) -; RV64I-WITH-FP-NEXT: sw t4, 40(a5) -; RV64I-WITH-FP-NEXT: sw t3, 36(a5) -; RV64I-WITH-FP-NEXT: sw t2, 32(a5) -; RV64I-WITH-FP-NEXT: sw t1, 28(a5) +; RV64I-WITH-FP-NEXT: lw t1, 28(a1) +; RV64I-WITH-FP-NEXT: lw t2, 32(a1) +; RV64I-WITH-FP-NEXT: lw t3, 36(a1) +; RV64I-WITH-FP-NEXT: lw t4, 40(a1) +; RV64I-WITH-FP-NEXT: lw t5, 44(a1) +; RV64I-WITH-FP-NEXT: lw t6, 48(a1) +; RV64I-WITH-FP-NEXT: lw s1, 52(a1) +; RV64I-WITH-FP-NEXT: lw s2, 56(a1) +; RV64I-WITH-FP-NEXT: lw s3, 60(a1) +; RV64I-WITH-FP-NEXT: lw s4, 64(a1) +; RV64I-WITH-FP-NEXT: lw s5, 68(a1) +; RV64I-WITH-FP-NEXT: lw s6, 72(a1) +; RV64I-WITH-FP-NEXT: lw s7, 76(a1) +; RV64I-WITH-FP-NEXT: lw s8, 80(a1) +; RV64I-WITH-FP-NEXT: lw s9, 84(a1) +; RV64I-WITH-FP-NEXT: lw s10, 88(a1) +; RV64I-WITH-FP-NEXT: lw s11, 92(a1) +; RV64I-WITH-FP-NEXT: lw ra, 96(a1) +; RV64I-WITH-FP-NEXT: lw a7, 100(a1) +; RV64I-WITH-FP-NEXT: lw a6, 104(a1) +; RV64I-WITH-FP-NEXT: lw a5, 108(a1) +; RV64I-WITH-FP-NEXT: lw a0, 124(a1) +; RV64I-WITH-FP-NEXT: lw a2, 120(a1) +; RV64I-WITH-FP-NEXT: lw a3, 116(a1) +; RV64I-WITH-FP-NEXT: lw a4, 112(a1) +; RV64I-WITH-FP-NEXT: sw a0, 124(a1) +; RV64I-WITH-FP-NEXT: sw a2, 120(a1) +; RV64I-WITH-FP-NEXT: sw a3, 116(a1) +; RV64I-WITH-FP-NEXT: sw a4, 112(a1) +; RV64I-WITH-FP-NEXT: sw a5, 108(a1) +; RV64I-WITH-FP-NEXT: sw a6, 104(a1) +; RV64I-WITH-FP-NEXT: sw a7, 100(a1) +; RV64I-WITH-FP-NEXT: sw ra, 96(a1) +; RV64I-WITH-FP-NEXT: sw s11, 92(a1) +; RV64I-WITH-FP-NEXT: sw s10, 88(a1) +; RV64I-WITH-FP-NEXT: sw s9, 84(a1) +; RV64I-WITH-FP-NEXT: sw s8, 80(a1) +; RV64I-WITH-FP-NEXT: sw s7, 76(a1) +; RV64I-WITH-FP-NEXT: sw s6, 72(a1) +; RV64I-WITH-FP-NEXT: sw s5, 68(a1) +; RV64I-WITH-FP-NEXT: sw s4, 64(a1) +; RV64I-WITH-FP-NEXT: sw s3, 60(a1) +; RV64I-WITH-FP-NEXT: sw s2, 56(a1) +; RV64I-WITH-FP-NEXT: sw s1, 52(a1) +; RV64I-WITH-FP-NEXT: sw t6, 48(a1) +; RV64I-WITH-FP-NEXT: sw t5, 44(a1) +; RV64I-WITH-FP-NEXT: sw t4, 40(a1) +; RV64I-WITH-FP-NEXT: sw t3, 36(a1) +; RV64I-WITH-FP-NEXT: sw t2, 32(a1) +; RV64I-WITH-FP-NEXT: sw t1, 28(a1) ; RV64I-WITH-FP-NEXT: ld a0, -160(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 24(a5) +; RV64I-WITH-FP-NEXT: sw a0, 24(a1) ; RV64I-WITH-FP-NEXT: ld a0, -152(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 20(a5) +; RV64I-WITH-FP-NEXT: sw a0, 20(a1) ; RV64I-WITH-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 16(a5) +; RV64I-WITH-FP-NEXT: sw a0, 16(a1) ; RV64I-WITH-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, %lo(var+12)(a7) +; RV64I-WITH-FP-NEXT: sw a0, %lo(var+12)(t0) ; RV64I-WITH-FP-NEXT: ld a0, -128(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, %lo(var+8)(a7) +; RV64I-WITH-FP-NEXT: sw a0, %lo(var+8)(t0) ; RV64I-WITH-FP-NEXT: ld a0, -120(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, %lo(var+4)(a7) +; RV64I-WITH-FP-NEXT: sw a0, %lo(var+4)(t0) ; RV64I-WITH-FP-NEXT: ld a0, -112(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, %lo(var)(a7) +; RV64I-WITH-FP-NEXT: sw a0, 0(a1) ; RV64I-WITH-FP-NEXT: ld ra, 152(sp) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld s0, 144(sp) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld s1, 136(sp) # 8-byte Folded Reload @@ -497,7 +497,8 @@ ; RV32I-NEXT: sw s10, 96(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s11, 92(sp) # 4-byte Folded Spill ; RV32I-NEXT: lui s0, %hi(var) -; RV32I-NEXT: lw a0, %lo(var)(s0) +; RV32I-NEXT: addi s1, s0, %lo(var) +; RV32I-NEXT: lw a0, 0(s1) ; RV32I-NEXT: sw a0, 88(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a0, %lo(var+4)(s0) ; RV32I-NEXT: sw a0, 84(sp) # 4-byte Folded Spill @@ -505,100 +506,99 @@ ; RV32I-NEXT: sw a0, 80(sp) # 4-byte Folded Spill ; RV32I-NEXT: lw a0, %lo(var+12)(s0) ; RV32I-NEXT: sw a0, 76(sp) # 4-byte Folded Spill -; RV32I-NEXT: addi s5, s0, %lo(var) -; RV32I-NEXT: lw a0, 16(s5) +; RV32I-NEXT: lw a0, 16(s1) ; RV32I-NEXT: sw a0, 72(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 20(s5) +; RV32I-NEXT: lw a0, 20(s1) ; RV32I-NEXT: sw a0, 68(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 24(s5) +; RV32I-NEXT: lw a0, 24(s1) ; RV32I-NEXT: sw a0, 64(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 28(s5) +; RV32I-NEXT: lw a0, 28(s1) ; RV32I-NEXT: sw a0, 60(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 32(s5) +; RV32I-NEXT: lw a0, 32(s1) ; RV32I-NEXT: sw a0, 56(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 36(s5) +; RV32I-NEXT: lw a0, 36(s1) ; RV32I-NEXT: sw a0, 52(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 40(s5) +; RV32I-NEXT: lw a0, 40(s1) ; RV32I-NEXT: sw a0, 48(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 44(s5) +; RV32I-NEXT: lw a0, 44(s1) ; RV32I-NEXT: sw a0, 44(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 48(s5) +; RV32I-NEXT: lw a0, 48(s1) ; RV32I-NEXT: sw a0, 40(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 52(s5) +; RV32I-NEXT: lw a0, 52(s1) ; RV32I-NEXT: sw a0, 36(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 56(s5) +; RV32I-NEXT: lw a0, 56(s1) ; RV32I-NEXT: sw a0, 32(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 60(s5) +; RV32I-NEXT: lw a0, 60(s1) ; RV32I-NEXT: sw a0, 28(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 64(s5) +; RV32I-NEXT: lw a0, 64(s1) ; RV32I-NEXT: sw a0, 24(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 68(s5) +; RV32I-NEXT: lw a0, 68(s1) ; RV32I-NEXT: sw a0, 20(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 72(s5) +; RV32I-NEXT: lw a0, 72(s1) ; RV32I-NEXT: sw a0, 16(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 76(s5) +; RV32I-NEXT: lw a0, 76(s1) ; RV32I-NEXT: sw a0, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 80(s5) +; RV32I-NEXT: lw a0, 80(s1) ; RV32I-NEXT: sw a0, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw a0, 84(s5) +; RV32I-NEXT: lw a0, 84(s1) ; RV32I-NEXT: sw a0, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: lw s3, 88(s5) -; RV32I-NEXT: lw s4, 92(s5) -; RV32I-NEXT: lw s6, 96(s5) -; RV32I-NEXT: lw s7, 100(s5) -; RV32I-NEXT: lw s8, 104(s5) -; RV32I-NEXT: lw s9, 108(s5) -; RV32I-NEXT: lw s10, 112(s5) -; RV32I-NEXT: lw s11, 116(s5) -; RV32I-NEXT: lw s1, 120(s5) -; RV32I-NEXT: lw s2, 124(s5) +; RV32I-NEXT: lw s4, 88(s1) +; RV32I-NEXT: lw s5, 92(s1) +; RV32I-NEXT: lw s6, 96(s1) +; RV32I-NEXT: lw s7, 100(s1) +; RV32I-NEXT: lw s8, 104(s1) +; RV32I-NEXT: lw s9, 108(s1) +; RV32I-NEXT: lw s10, 112(s1) +; RV32I-NEXT: lw s11, 116(s1) +; RV32I-NEXT: lw s2, 120(s1) +; RV32I-NEXT: lw s3, 124(s1) ; RV32I-NEXT: call callee@plt -; RV32I-NEXT: sw s2, 124(s5) -; RV32I-NEXT: sw s1, 120(s5) -; RV32I-NEXT: sw s11, 116(s5) -; RV32I-NEXT: sw s10, 112(s5) -; RV32I-NEXT: sw s9, 108(s5) -; RV32I-NEXT: sw s8, 104(s5) -; RV32I-NEXT: sw s7, 100(s5) -; RV32I-NEXT: sw s6, 96(s5) -; RV32I-NEXT: sw s4, 92(s5) -; RV32I-NEXT: sw s3, 88(s5) +; RV32I-NEXT: sw s3, 124(s1) +; RV32I-NEXT: sw s2, 120(s1) +; RV32I-NEXT: sw s11, 116(s1) +; RV32I-NEXT: sw s10, 112(s1) +; RV32I-NEXT: sw s9, 108(s1) +; RV32I-NEXT: sw s8, 104(s1) +; RV32I-NEXT: sw s7, 100(s1) +; RV32I-NEXT: sw s6, 96(s1) +; RV32I-NEXT: sw s5, 92(s1) +; RV32I-NEXT: sw s4, 88(s1) ; RV32I-NEXT: lw a0, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 84(s5) +; RV32I-NEXT: sw a0, 84(s1) ; RV32I-NEXT: lw a0, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 80(s5) +; RV32I-NEXT: sw a0, 80(s1) ; RV32I-NEXT: lw a0, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 76(s5) +; RV32I-NEXT: sw a0, 76(s1) ; RV32I-NEXT: lw a0, 16(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 72(s5) +; RV32I-NEXT: sw a0, 72(s1) ; RV32I-NEXT: lw a0, 20(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 68(s5) +; RV32I-NEXT: sw a0, 68(s1) ; RV32I-NEXT: lw a0, 24(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 64(s5) +; RV32I-NEXT: sw a0, 64(s1) ; RV32I-NEXT: lw a0, 28(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 60(s5) +; RV32I-NEXT: sw a0, 60(s1) ; RV32I-NEXT: lw a0, 32(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 56(s5) +; RV32I-NEXT: sw a0, 56(s1) ; RV32I-NEXT: lw a0, 36(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 52(s5) +; RV32I-NEXT: sw a0, 52(s1) ; RV32I-NEXT: lw a0, 40(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 48(s5) +; RV32I-NEXT: sw a0, 48(s1) ; RV32I-NEXT: lw a0, 44(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 44(s5) +; RV32I-NEXT: sw a0, 44(s1) ; RV32I-NEXT: lw a0, 48(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 40(s5) +; RV32I-NEXT: sw a0, 40(s1) ; RV32I-NEXT: lw a0, 52(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 36(s5) +; RV32I-NEXT: sw a0, 36(s1) ; RV32I-NEXT: lw a0, 56(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 32(s5) +; RV32I-NEXT: sw a0, 32(s1) ; RV32I-NEXT: lw a0, 60(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 28(s5) +; RV32I-NEXT: sw a0, 28(s1) ; RV32I-NEXT: lw a0, 64(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 24(s5) +; RV32I-NEXT: sw a0, 24(s1) ; RV32I-NEXT: lw a0, 68(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 20(s5) +; RV32I-NEXT: sw a0, 20(s1) ; RV32I-NEXT: lw a0, 72(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, 16(s5) +; RV32I-NEXT: sw a0, 16(s1) ; RV32I-NEXT: lw a0, 76(sp) # 4-byte Folded Reload ; RV32I-NEXT: sw a0, %lo(var+12)(s0) ; RV32I-NEXT: lw a0, 80(sp) # 4-byte Folded Reload @@ -606,7 +606,7 @@ ; RV32I-NEXT: lw a0, 84(sp) # 4-byte Folded Reload ; RV32I-NEXT: sw a0, %lo(var+4)(s0) ; RV32I-NEXT: lw a0, 88(sp) # 4-byte Folded Reload -; RV32I-NEXT: sw a0, %lo(var)(s0) +; RV32I-NEXT: sw a0, 0(s1) ; RV32I-NEXT: lw ra, 140(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 136(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 132(sp) # 4-byte Folded Reload @@ -641,7 +641,8 @@ ; RV32I-WITH-FP-NEXT: sw s11, 92(sp) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: addi s0, sp, 144 ; RV32I-WITH-FP-NEXT: lui s1, %hi(var) -; RV32I-WITH-FP-NEXT: lw a0, %lo(var)(s1) +; RV32I-WITH-FP-NEXT: addi s2, s1, %lo(var) +; RV32I-WITH-FP-NEXT: lw a0, 0(s2) ; RV32I-WITH-FP-NEXT: sw a0, -56(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: lw a0, %lo(var+4)(s1) ; RV32I-WITH-FP-NEXT: sw a0, -60(s0) # 4-byte Folded Spill @@ -649,102 +650,101 @@ ; RV32I-WITH-FP-NEXT: sw a0, -64(s0) # 4-byte Folded Spill ; RV32I-WITH-FP-NEXT: lw a0, %lo(var+12)(s1) ; RV32I-WITH-FP-NEXT: sw a0, -68(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: addi s6, s1, %lo(var) -; RV32I-WITH-FP-NEXT: lw a0, 16(s6) +; RV32I-WITH-FP-NEXT: lw a0, 16(s2) ; RV32I-WITH-FP-NEXT: sw a0, -72(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 20(s6) +; RV32I-WITH-FP-NEXT: lw a0, 20(s2) ; RV32I-WITH-FP-NEXT: sw a0, -76(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 24(s6) +; RV32I-WITH-FP-NEXT: lw a0, 24(s2) ; RV32I-WITH-FP-NEXT: sw a0, -80(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 28(s6) +; RV32I-WITH-FP-NEXT: lw a0, 28(s2) ; RV32I-WITH-FP-NEXT: sw a0, -84(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 32(s6) +; RV32I-WITH-FP-NEXT: lw a0, 32(s2) ; RV32I-WITH-FP-NEXT: sw a0, -88(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 36(s6) +; RV32I-WITH-FP-NEXT: lw a0, 36(s2) ; RV32I-WITH-FP-NEXT: sw a0, -92(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 40(s6) +; RV32I-WITH-FP-NEXT: lw a0, 40(s2) ; RV32I-WITH-FP-NEXT: sw a0, -96(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 44(s6) +; RV32I-WITH-FP-NEXT: lw a0, 44(s2) ; RV32I-WITH-FP-NEXT: sw a0, -100(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 48(s6) +; RV32I-WITH-FP-NEXT: lw a0, 48(s2) ; RV32I-WITH-FP-NEXT: sw a0, -104(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 52(s6) +; RV32I-WITH-FP-NEXT: lw a0, 52(s2) ; RV32I-WITH-FP-NEXT: sw a0, -108(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 56(s6) +; RV32I-WITH-FP-NEXT: lw a0, 56(s2) ; RV32I-WITH-FP-NEXT: sw a0, -112(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 60(s6) +; RV32I-WITH-FP-NEXT: lw a0, 60(s2) ; RV32I-WITH-FP-NEXT: sw a0, -116(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 64(s6) +; RV32I-WITH-FP-NEXT: lw a0, 64(s2) ; RV32I-WITH-FP-NEXT: sw a0, -120(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 68(s6) +; RV32I-WITH-FP-NEXT: lw a0, 68(s2) ; RV32I-WITH-FP-NEXT: sw a0, -124(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 72(s6) +; RV32I-WITH-FP-NEXT: lw a0, 72(s2) ; RV32I-WITH-FP-NEXT: sw a0, -128(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 76(s6) +; RV32I-WITH-FP-NEXT: lw a0, 76(s2) ; RV32I-WITH-FP-NEXT: sw a0, -132(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 80(s6) +; RV32I-WITH-FP-NEXT: lw a0, 80(s2) ; RV32I-WITH-FP-NEXT: sw a0, -136(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 84(s6) +; RV32I-WITH-FP-NEXT: lw a0, 84(s2) ; RV32I-WITH-FP-NEXT: sw a0, -140(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw a0, 88(s6) +; RV32I-WITH-FP-NEXT: lw a0, 88(s2) ; RV32I-WITH-FP-NEXT: sw a0, -144(s0) # 4-byte Folded Spill -; RV32I-WITH-FP-NEXT: lw s8, 92(s6) -; RV32I-WITH-FP-NEXT: lw s9, 96(s6) -; RV32I-WITH-FP-NEXT: lw s10, 100(s6) -; RV32I-WITH-FP-NEXT: lw s11, 104(s6) -; RV32I-WITH-FP-NEXT: lw s2, 108(s6) -; RV32I-WITH-FP-NEXT: lw s3, 112(s6) -; RV32I-WITH-FP-NEXT: lw s4, 116(s6) -; RV32I-WITH-FP-NEXT: lw s5, 120(s6) -; RV32I-WITH-FP-NEXT: lw s7, 124(s6) +; RV32I-WITH-FP-NEXT: lw s8, 92(s2) +; RV32I-WITH-FP-NEXT: lw s9, 96(s2) +; RV32I-WITH-FP-NEXT: lw s10, 100(s2) +; RV32I-WITH-FP-NEXT: lw s11, 104(s2) +; RV32I-WITH-FP-NEXT: lw s3, 108(s2) +; RV32I-WITH-FP-NEXT: lw s4, 112(s2) +; RV32I-WITH-FP-NEXT: lw s5, 116(s2) +; RV32I-WITH-FP-NEXT: lw s6, 120(s2) +; RV32I-WITH-FP-NEXT: lw s7, 124(s2) ; RV32I-WITH-FP-NEXT: call callee@plt -; RV32I-WITH-FP-NEXT: sw s7, 124(s6) -; RV32I-WITH-FP-NEXT: sw s5, 120(s6) -; RV32I-WITH-FP-NEXT: sw s4, 116(s6) -; RV32I-WITH-FP-NEXT: sw s3, 112(s6) -; RV32I-WITH-FP-NEXT: sw s2, 108(s6) -; RV32I-WITH-FP-NEXT: sw s11, 104(s6) -; RV32I-WITH-FP-NEXT: sw s10, 100(s6) -; RV32I-WITH-FP-NEXT: sw s9, 96(s6) -; RV32I-WITH-FP-NEXT: sw s8, 92(s6) +; RV32I-WITH-FP-NEXT: sw s7, 124(s2) +; RV32I-WITH-FP-NEXT: sw s6, 120(s2) +; RV32I-WITH-FP-NEXT: sw s5, 116(s2) +; RV32I-WITH-FP-NEXT: sw s4, 112(s2) +; RV32I-WITH-FP-NEXT: sw s3, 108(s2) +; RV32I-WITH-FP-NEXT: sw s11, 104(s2) +; RV32I-WITH-FP-NEXT: sw s10, 100(s2) +; RV32I-WITH-FP-NEXT: sw s9, 96(s2) +; RV32I-WITH-FP-NEXT: sw s8, 92(s2) ; RV32I-WITH-FP-NEXT: lw a0, -144(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 88(s6) +; RV32I-WITH-FP-NEXT: sw a0, 88(s2) ; RV32I-WITH-FP-NEXT: lw a0, -140(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 84(s6) +; RV32I-WITH-FP-NEXT: sw a0, 84(s2) ; RV32I-WITH-FP-NEXT: lw a0, -136(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 80(s6) +; RV32I-WITH-FP-NEXT: sw a0, 80(s2) ; RV32I-WITH-FP-NEXT: lw a0, -132(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 76(s6) +; RV32I-WITH-FP-NEXT: sw a0, 76(s2) ; RV32I-WITH-FP-NEXT: lw a0, -128(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 72(s6) +; RV32I-WITH-FP-NEXT: sw a0, 72(s2) ; RV32I-WITH-FP-NEXT: lw a0, -124(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 68(s6) +; RV32I-WITH-FP-NEXT: sw a0, 68(s2) ; RV32I-WITH-FP-NEXT: lw a0, -120(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 64(s6) +; RV32I-WITH-FP-NEXT: sw a0, 64(s2) ; RV32I-WITH-FP-NEXT: lw a0, -116(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 60(s6) +; RV32I-WITH-FP-NEXT: sw a0, 60(s2) ; RV32I-WITH-FP-NEXT: lw a0, -112(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 56(s6) +; RV32I-WITH-FP-NEXT: sw a0, 56(s2) ; RV32I-WITH-FP-NEXT: lw a0, -108(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 52(s6) +; RV32I-WITH-FP-NEXT: sw a0, 52(s2) ; RV32I-WITH-FP-NEXT: lw a0, -104(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 48(s6) +; RV32I-WITH-FP-NEXT: sw a0, 48(s2) ; RV32I-WITH-FP-NEXT: lw a0, -100(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 44(s6) +; RV32I-WITH-FP-NEXT: sw a0, 44(s2) ; RV32I-WITH-FP-NEXT: lw a0, -96(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 40(s6) +; RV32I-WITH-FP-NEXT: sw a0, 40(s2) ; RV32I-WITH-FP-NEXT: lw a0, -92(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 36(s6) +; RV32I-WITH-FP-NEXT: sw a0, 36(s2) ; RV32I-WITH-FP-NEXT: lw a0, -88(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 32(s6) +; RV32I-WITH-FP-NEXT: sw a0, 32(s2) ; RV32I-WITH-FP-NEXT: lw a0, -84(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 28(s6) +; RV32I-WITH-FP-NEXT: sw a0, 28(s2) ; RV32I-WITH-FP-NEXT: lw a0, -80(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 24(s6) +; RV32I-WITH-FP-NEXT: sw a0, 24(s2) ; RV32I-WITH-FP-NEXT: lw a0, -76(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 20(s6) +; RV32I-WITH-FP-NEXT: sw a0, 20(s2) ; RV32I-WITH-FP-NEXT: lw a0, -72(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, 16(s6) +; RV32I-WITH-FP-NEXT: sw a0, 16(s2) ; RV32I-WITH-FP-NEXT: lw a0, -68(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: sw a0, %lo(var+12)(s1) ; RV32I-WITH-FP-NEXT: lw a0, -64(s0) # 4-byte Folded Reload @@ -752,7 +752,7 @@ ; RV32I-WITH-FP-NEXT: lw a0, -60(s0) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: sw a0, %lo(var+4)(s1) ; RV32I-WITH-FP-NEXT: lw a0, -56(s0) # 4-byte Folded Reload -; RV32I-WITH-FP-NEXT: sw a0, %lo(var)(s1) +; RV32I-WITH-FP-NEXT: sw a0, 0(s2) ; RV32I-WITH-FP-NEXT: lw ra, 140(sp) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw s0, 136(sp) # 4-byte Folded Reload ; RV32I-WITH-FP-NEXT: lw s1, 132(sp) # 4-byte Folded Reload @@ -786,7 +786,8 @@ ; RV64I-NEXT: sd s10, 192(sp) # 8-byte Folded Spill ; RV64I-NEXT: sd s11, 184(sp) # 8-byte Folded Spill ; RV64I-NEXT: lui s0, %hi(var) -; RV64I-NEXT: lw a0, %lo(var)(s0) +; RV64I-NEXT: addi s1, s0, %lo(var) +; RV64I-NEXT: lw a0, 0(s1) ; RV64I-NEXT: sd a0, 176(sp) # 8-byte Folded Spill ; RV64I-NEXT: lw a0, %lo(var+4)(s0) ; RV64I-NEXT: sd a0, 168(sp) # 8-byte Folded Spill @@ -794,100 +795,99 @@ ; RV64I-NEXT: sd a0, 160(sp) # 8-byte Folded Spill ; RV64I-NEXT: lw a0, %lo(var+12)(s0) ; RV64I-NEXT: sd a0, 152(sp) # 8-byte Folded Spill -; RV64I-NEXT: addi s5, s0, %lo(var) -; RV64I-NEXT: lw a0, 16(s5) +; RV64I-NEXT: lw a0, 16(s1) ; RV64I-NEXT: sd a0, 144(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 20(s5) +; RV64I-NEXT: lw a0, 20(s1) ; RV64I-NEXT: sd a0, 136(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 24(s5) +; RV64I-NEXT: lw a0, 24(s1) ; RV64I-NEXT: sd a0, 128(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 28(s5) +; RV64I-NEXT: lw a0, 28(s1) ; RV64I-NEXT: sd a0, 120(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 32(s5) +; RV64I-NEXT: lw a0, 32(s1) ; RV64I-NEXT: sd a0, 112(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 36(s5) +; RV64I-NEXT: lw a0, 36(s1) ; RV64I-NEXT: sd a0, 104(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 40(s5) +; RV64I-NEXT: lw a0, 40(s1) ; RV64I-NEXT: sd a0, 96(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 44(s5) +; RV64I-NEXT: lw a0, 44(s1) ; RV64I-NEXT: sd a0, 88(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 48(s5) +; RV64I-NEXT: lw a0, 48(s1) ; RV64I-NEXT: sd a0, 80(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 52(s5) +; RV64I-NEXT: lw a0, 52(s1) ; RV64I-NEXT: sd a0, 72(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 56(s5) +; RV64I-NEXT: lw a0, 56(s1) ; RV64I-NEXT: sd a0, 64(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 60(s5) +; RV64I-NEXT: lw a0, 60(s1) ; RV64I-NEXT: sd a0, 56(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 64(s5) +; RV64I-NEXT: lw a0, 64(s1) ; RV64I-NEXT: sd a0, 48(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 68(s5) +; RV64I-NEXT: lw a0, 68(s1) ; RV64I-NEXT: sd a0, 40(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 72(s5) +; RV64I-NEXT: lw a0, 72(s1) ; RV64I-NEXT: sd a0, 32(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 76(s5) +; RV64I-NEXT: lw a0, 76(s1) ; RV64I-NEXT: sd a0, 24(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 80(s5) +; RV64I-NEXT: lw a0, 80(s1) ; RV64I-NEXT: sd a0, 16(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw a0, 84(s5) +; RV64I-NEXT: lw a0, 84(s1) ; RV64I-NEXT: sd a0, 8(sp) # 8-byte Folded Spill -; RV64I-NEXT: lw s3, 88(s5) -; RV64I-NEXT: lw s4, 92(s5) -; RV64I-NEXT: lw s6, 96(s5) -; RV64I-NEXT: lw s7, 100(s5) -; RV64I-NEXT: lw s8, 104(s5) -; RV64I-NEXT: lw s9, 108(s5) -; RV64I-NEXT: lw s10, 112(s5) -; RV64I-NEXT: lw s11, 116(s5) -; RV64I-NEXT: lw s1, 120(s5) -; RV64I-NEXT: lw s2, 124(s5) +; RV64I-NEXT: lw s4, 88(s1) +; RV64I-NEXT: lw s5, 92(s1) +; RV64I-NEXT: lw s6, 96(s1) +; RV64I-NEXT: lw s7, 100(s1) +; RV64I-NEXT: lw s8, 104(s1) +; RV64I-NEXT: lw s9, 108(s1) +; RV64I-NEXT: lw s10, 112(s1) +; RV64I-NEXT: lw s11, 116(s1) +; RV64I-NEXT: lw s2, 120(s1) +; RV64I-NEXT: lw s3, 124(s1) ; RV64I-NEXT: call callee@plt -; RV64I-NEXT: sw s2, 124(s5) -; RV64I-NEXT: sw s1, 120(s5) -; RV64I-NEXT: sw s11, 116(s5) -; RV64I-NEXT: sw s10, 112(s5) -; RV64I-NEXT: sw s9, 108(s5) -; RV64I-NEXT: sw s8, 104(s5) -; RV64I-NEXT: sw s7, 100(s5) -; RV64I-NEXT: sw s6, 96(s5) -; RV64I-NEXT: sw s4, 92(s5) -; RV64I-NEXT: sw s3, 88(s5) +; RV64I-NEXT: sw s3, 124(s1) +; RV64I-NEXT: sw s2, 120(s1) +; RV64I-NEXT: sw s11, 116(s1) +; RV64I-NEXT: sw s10, 112(s1) +; RV64I-NEXT: sw s9, 108(s1) +; RV64I-NEXT: sw s8, 104(s1) +; RV64I-NEXT: sw s7, 100(s1) +; RV64I-NEXT: sw s6, 96(s1) +; RV64I-NEXT: sw s5, 92(s1) +; RV64I-NEXT: sw s4, 88(s1) ; RV64I-NEXT: ld a0, 8(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 84(s5) +; RV64I-NEXT: sw a0, 84(s1) ; RV64I-NEXT: ld a0, 16(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 80(s5) +; RV64I-NEXT: sw a0, 80(s1) ; RV64I-NEXT: ld a0, 24(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 76(s5) +; RV64I-NEXT: sw a0, 76(s1) ; RV64I-NEXT: ld a0, 32(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 72(s5) +; RV64I-NEXT: sw a0, 72(s1) ; RV64I-NEXT: ld a0, 40(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 68(s5) +; RV64I-NEXT: sw a0, 68(s1) ; RV64I-NEXT: ld a0, 48(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 64(s5) +; RV64I-NEXT: sw a0, 64(s1) ; RV64I-NEXT: ld a0, 56(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 60(s5) +; RV64I-NEXT: sw a0, 60(s1) ; RV64I-NEXT: ld a0, 64(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 56(s5) +; RV64I-NEXT: sw a0, 56(s1) ; RV64I-NEXT: ld a0, 72(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 52(s5) +; RV64I-NEXT: sw a0, 52(s1) ; RV64I-NEXT: ld a0, 80(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 48(s5) +; RV64I-NEXT: sw a0, 48(s1) ; RV64I-NEXT: ld a0, 88(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 44(s5) +; RV64I-NEXT: sw a0, 44(s1) ; RV64I-NEXT: ld a0, 96(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 40(s5) +; RV64I-NEXT: sw a0, 40(s1) ; RV64I-NEXT: ld a0, 104(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 36(s5) +; RV64I-NEXT: sw a0, 36(s1) ; RV64I-NEXT: ld a0, 112(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 32(s5) +; RV64I-NEXT: sw a0, 32(s1) ; RV64I-NEXT: ld a0, 120(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 28(s5) +; RV64I-NEXT: sw a0, 28(s1) ; RV64I-NEXT: ld a0, 128(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 24(s5) +; RV64I-NEXT: sw a0, 24(s1) ; RV64I-NEXT: ld a0, 136(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 20(s5) +; RV64I-NEXT: sw a0, 20(s1) ; RV64I-NEXT: ld a0, 144(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, 16(s5) +; RV64I-NEXT: sw a0, 16(s1) ; RV64I-NEXT: ld a0, 152(sp) # 8-byte Folded Reload ; RV64I-NEXT: sw a0, %lo(var+12)(s0) ; RV64I-NEXT: ld a0, 160(sp) # 8-byte Folded Reload @@ -895,7 +895,7 @@ ; RV64I-NEXT: ld a0, 168(sp) # 8-byte Folded Reload ; RV64I-NEXT: sw a0, %lo(var+4)(s0) ; RV64I-NEXT: ld a0, 176(sp) # 8-byte Folded Reload -; RV64I-NEXT: sw a0, %lo(var)(s0) +; RV64I-NEXT: sw a0, 0(s1) ; RV64I-NEXT: ld ra, 280(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s0, 272(sp) # 8-byte Folded Reload ; RV64I-NEXT: ld s1, 264(sp) # 8-byte Folded Reload @@ -930,7 +930,8 @@ ; RV64I-WITH-FP-NEXT: sd s11, 184(sp) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: addi s0, sp, 288 ; RV64I-WITH-FP-NEXT: lui s1, %hi(var) -; RV64I-WITH-FP-NEXT: lw a0, %lo(var)(s1) +; RV64I-WITH-FP-NEXT: addi s2, s1, %lo(var) +; RV64I-WITH-FP-NEXT: lw a0, 0(s2) ; RV64I-WITH-FP-NEXT: sd a0, -112(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: lw a0, %lo(var+4)(s1) ; RV64I-WITH-FP-NEXT: sd a0, -120(s0) # 8-byte Folded Spill @@ -938,102 +939,101 @@ ; RV64I-WITH-FP-NEXT: sd a0, -128(s0) # 8-byte Folded Spill ; RV64I-WITH-FP-NEXT: lw a0, %lo(var+12)(s1) ; RV64I-WITH-FP-NEXT: sd a0, -136(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: addi s6, s1, %lo(var) -; RV64I-WITH-FP-NEXT: lw a0, 16(s6) +; RV64I-WITH-FP-NEXT: lw a0, 16(s2) ; RV64I-WITH-FP-NEXT: sd a0, -144(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 20(s6) +; RV64I-WITH-FP-NEXT: lw a0, 20(s2) ; RV64I-WITH-FP-NEXT: sd a0, -152(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 24(s6) +; RV64I-WITH-FP-NEXT: lw a0, 24(s2) ; RV64I-WITH-FP-NEXT: sd a0, -160(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 28(s6) +; RV64I-WITH-FP-NEXT: lw a0, 28(s2) ; RV64I-WITH-FP-NEXT: sd a0, -168(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 32(s6) +; RV64I-WITH-FP-NEXT: lw a0, 32(s2) ; RV64I-WITH-FP-NEXT: sd a0, -176(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 36(s6) +; RV64I-WITH-FP-NEXT: lw a0, 36(s2) ; RV64I-WITH-FP-NEXT: sd a0, -184(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 40(s6) +; RV64I-WITH-FP-NEXT: lw a0, 40(s2) ; RV64I-WITH-FP-NEXT: sd a0, -192(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 44(s6) +; RV64I-WITH-FP-NEXT: lw a0, 44(s2) ; RV64I-WITH-FP-NEXT: sd a0, -200(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 48(s6) +; RV64I-WITH-FP-NEXT: lw a0, 48(s2) ; RV64I-WITH-FP-NEXT: sd a0, -208(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 52(s6) +; RV64I-WITH-FP-NEXT: lw a0, 52(s2) ; RV64I-WITH-FP-NEXT: sd a0, -216(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 56(s6) +; RV64I-WITH-FP-NEXT: lw a0, 56(s2) ; RV64I-WITH-FP-NEXT: sd a0, -224(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 60(s6) +; RV64I-WITH-FP-NEXT: lw a0, 60(s2) ; RV64I-WITH-FP-NEXT: sd a0, -232(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 64(s6) +; RV64I-WITH-FP-NEXT: lw a0, 64(s2) ; RV64I-WITH-FP-NEXT: sd a0, -240(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 68(s6) +; RV64I-WITH-FP-NEXT: lw a0, 68(s2) ; RV64I-WITH-FP-NEXT: sd a0, -248(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 72(s6) +; RV64I-WITH-FP-NEXT: lw a0, 72(s2) ; RV64I-WITH-FP-NEXT: sd a0, -256(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 76(s6) +; RV64I-WITH-FP-NEXT: lw a0, 76(s2) ; RV64I-WITH-FP-NEXT: sd a0, -264(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 80(s6) +; RV64I-WITH-FP-NEXT: lw a0, 80(s2) ; RV64I-WITH-FP-NEXT: sd a0, -272(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 84(s6) +; RV64I-WITH-FP-NEXT: lw a0, 84(s2) ; RV64I-WITH-FP-NEXT: sd a0, -280(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw a0, 88(s6) +; RV64I-WITH-FP-NEXT: lw a0, 88(s2) ; RV64I-WITH-FP-NEXT: sd a0, -288(s0) # 8-byte Folded Spill -; RV64I-WITH-FP-NEXT: lw s8, 92(s6) -; RV64I-WITH-FP-NEXT: lw s9, 96(s6) -; RV64I-WITH-FP-NEXT: lw s10, 100(s6) -; RV64I-WITH-FP-NEXT: lw s11, 104(s6) -; RV64I-WITH-FP-NEXT: lw s2, 108(s6) -; RV64I-WITH-FP-NEXT: lw s3, 112(s6) -; RV64I-WITH-FP-NEXT: lw s4, 116(s6) -; RV64I-WITH-FP-NEXT: lw s5, 120(s6) -; RV64I-WITH-FP-NEXT: lw s7, 124(s6) +; RV64I-WITH-FP-NEXT: lw s8, 92(s2) +; RV64I-WITH-FP-NEXT: lw s9, 96(s2) +; RV64I-WITH-FP-NEXT: lw s10, 100(s2) +; RV64I-WITH-FP-NEXT: lw s11, 104(s2) +; RV64I-WITH-FP-NEXT: lw s3, 108(s2) +; RV64I-WITH-FP-NEXT: lw s4, 112(s2) +; RV64I-WITH-FP-NEXT: lw s5, 116(s2) +; RV64I-WITH-FP-NEXT: lw s6, 120(s2) +; RV64I-WITH-FP-NEXT: lw s7, 124(s2) ; RV64I-WITH-FP-NEXT: call callee@plt -; RV64I-WITH-FP-NEXT: sw s7, 124(s6) -; RV64I-WITH-FP-NEXT: sw s5, 120(s6) -; RV64I-WITH-FP-NEXT: sw s4, 116(s6) -; RV64I-WITH-FP-NEXT: sw s3, 112(s6) -; RV64I-WITH-FP-NEXT: sw s2, 108(s6) -; RV64I-WITH-FP-NEXT: sw s11, 104(s6) -; RV64I-WITH-FP-NEXT: sw s10, 100(s6) -; RV64I-WITH-FP-NEXT: sw s9, 96(s6) -; RV64I-WITH-FP-NEXT: sw s8, 92(s6) +; RV64I-WITH-FP-NEXT: sw s7, 124(s2) +; RV64I-WITH-FP-NEXT: sw s6, 120(s2) +; RV64I-WITH-FP-NEXT: sw s5, 116(s2) +; RV64I-WITH-FP-NEXT: sw s4, 112(s2) +; RV64I-WITH-FP-NEXT: sw s3, 108(s2) +; RV64I-WITH-FP-NEXT: sw s11, 104(s2) +; RV64I-WITH-FP-NEXT: sw s10, 100(s2) +; RV64I-WITH-FP-NEXT: sw s9, 96(s2) +; RV64I-WITH-FP-NEXT: sw s8, 92(s2) ; RV64I-WITH-FP-NEXT: ld a0, -288(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 88(s6) +; RV64I-WITH-FP-NEXT: sw a0, 88(s2) ; RV64I-WITH-FP-NEXT: ld a0, -280(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 84(s6) +; RV64I-WITH-FP-NEXT: sw a0, 84(s2) ; RV64I-WITH-FP-NEXT: ld a0, -272(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 80(s6) +; RV64I-WITH-FP-NEXT: sw a0, 80(s2) ; RV64I-WITH-FP-NEXT: ld a0, -264(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 76(s6) +; RV64I-WITH-FP-NEXT: sw a0, 76(s2) ; RV64I-WITH-FP-NEXT: ld a0, -256(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 72(s6) +; RV64I-WITH-FP-NEXT: sw a0, 72(s2) ; RV64I-WITH-FP-NEXT: ld a0, -248(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 68(s6) +; RV64I-WITH-FP-NEXT: sw a0, 68(s2) ; RV64I-WITH-FP-NEXT: ld a0, -240(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 64(s6) +; RV64I-WITH-FP-NEXT: sw a0, 64(s2) ; RV64I-WITH-FP-NEXT: ld a0, -232(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 60(s6) +; RV64I-WITH-FP-NEXT: sw a0, 60(s2) ; RV64I-WITH-FP-NEXT: ld a0, -224(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 56(s6) +; RV64I-WITH-FP-NEXT: sw a0, 56(s2) ; RV64I-WITH-FP-NEXT: ld a0, -216(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 52(s6) +; RV64I-WITH-FP-NEXT: sw a0, 52(s2) ; RV64I-WITH-FP-NEXT: ld a0, -208(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 48(s6) +; RV64I-WITH-FP-NEXT: sw a0, 48(s2) ; RV64I-WITH-FP-NEXT: ld a0, -200(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 44(s6) +; RV64I-WITH-FP-NEXT: sw a0, 44(s2) ; RV64I-WITH-FP-NEXT: ld a0, -192(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 40(s6) +; RV64I-WITH-FP-NEXT: sw a0, 40(s2) ; RV64I-WITH-FP-NEXT: ld a0, -184(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 36(s6) +; RV64I-WITH-FP-NEXT: sw a0, 36(s2) ; RV64I-WITH-FP-NEXT: ld a0, -176(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 32(s6) +; RV64I-WITH-FP-NEXT: sw a0, 32(s2) ; RV64I-WITH-FP-NEXT: ld a0, -168(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 28(s6) +; RV64I-WITH-FP-NEXT: sw a0, 28(s2) ; RV64I-WITH-FP-NEXT: ld a0, -160(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 24(s6) +; RV64I-WITH-FP-NEXT: sw a0, 24(s2) ; RV64I-WITH-FP-NEXT: ld a0, -152(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 20(s6) +; RV64I-WITH-FP-NEXT: sw a0, 20(s2) ; RV64I-WITH-FP-NEXT: ld a0, -144(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, 16(s6) +; RV64I-WITH-FP-NEXT: sw a0, 16(s2) ; RV64I-WITH-FP-NEXT: ld a0, -136(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: sw a0, %lo(var+12)(s1) ; RV64I-WITH-FP-NEXT: ld a0, -128(s0) # 8-byte Folded Reload @@ -1041,7 +1041,7 @@ ; RV64I-WITH-FP-NEXT: ld a0, -120(s0) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: sw a0, %lo(var+4)(s1) ; RV64I-WITH-FP-NEXT: ld a0, -112(s0) # 8-byte Folded Reload -; RV64I-WITH-FP-NEXT: sw a0, %lo(var)(s1) +; RV64I-WITH-FP-NEXT: sw a0, 0(s2) ; RV64I-WITH-FP-NEXT: ld ra, 280(sp) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld s0, 272(sp) # 8-byte Folded Reload ; RV64I-WITH-FP-NEXT: ld s1, 264(sp) # 8-byte Folded Reload Index: llvm/test/CodeGen/RISCV/double-mem.ll =================================================================== --- llvm/test/CodeGen/RISCV/double-mem.ll +++ llvm/test/CodeGen/RISCV/double-mem.ll @@ -44,11 +44,11 @@ ; CHECKIFD: # %bb.0: ; CHECKIFD-NEXT: fadd.d fa0, fa0, fa1 ; CHECKIFD-NEXT: lui a0, %hi(G) -; CHECKIFD-NEXT: fld ft0, %lo(G)(a0) -; CHECKIFD-NEXT: addi a1, a0, %lo(G) -; CHECKIFD-NEXT: fsd fa0, %lo(G)(a0) -; CHECKIFD-NEXT: fld ft0, 72(a1) -; CHECKIFD-NEXT: fsd fa0, 72(a1) +; CHECKIFD-NEXT: addi a0, a0, %lo(G) +; CHECKIFD-NEXT: fld ft0, 0(a0) +; CHECKIFD-NEXT: fsd fa0, 0(a0) +; CHECKIFD-NEXT: fld ft0, 72(a0) +; CHECKIFD-NEXT: fsd fa0, 72(a0) ; CHECKIFD-NEXT: ret ; Use %a and %b in an FP op to ensure floating point registers are used, even ; for the soft float ABI Index: llvm/test/CodeGen/RISCV/float-mem.ll =================================================================== --- llvm/test/CodeGen/RISCV/float-mem.ll +++ llvm/test/CodeGen/RISCV/float-mem.ll @@ -46,11 +46,11 @@ ; CHECKIF: # %bb.0: ; CHECKIF-NEXT: fadd.s fa0, fa0, fa1 ; CHECKIF-NEXT: lui a0, %hi(G) -; CHECKIF-NEXT: flw ft0, %lo(G)(a0) -; CHECKIF-NEXT: addi a1, a0, %lo(G) -; CHECKIF-NEXT: fsw fa0, %lo(G)(a0) -; CHECKIF-NEXT: flw ft0, 36(a1) -; CHECKIF-NEXT: fsw fa0, 36(a1) +; CHECKIF-NEXT: addi a0, a0, %lo(G) +; CHECKIF-NEXT: flw ft0, 0(a0) +; CHECKIF-NEXT: fsw fa0, 0(a0) +; CHECKIF-NEXT: flw ft0, 36(a0) +; CHECKIF-NEXT: fsw fa0, 36(a0) ; CHECKIF-NEXT: ret %1 = fadd float %a, %b %2 = load volatile float, float* @G Index: llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll =================================================================== --- llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll +++ llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll @@ -39,9 +39,9 @@ define dso_local i64 @load_g_1() nounwind { ; RV32I-LABEL: load_g_1: ; RV32I: # %bb.0: # %entry -; RV32I-NEXT: lui a1, %hi(g_1) -; RV32I-NEXT: lw a0, %lo(g_1)(a1) -; RV32I-NEXT: addi a1, a1, %lo(g_1) +; RV32I-NEXT: lui a0, %hi(g_1) +; RV32I-NEXT: addi a1, a0, %lo(g_1) +; RV32I-NEXT: lw a0, 0(a1) ; RV32I-NEXT: lw a1, 4(a1) ; RV32I-NEXT: ret ; @@ -58,9 +58,9 @@ define dso_local i64 @load_g_2() nounwind { ; RV32I-LABEL: load_g_2: ; RV32I: # %bb.0: # %entry -; RV32I-NEXT: lui a1, %hi(g_2) -; RV32I-NEXT: lw a0, %lo(g_2)(a1) -; RV32I-NEXT: addi a1, a1, %lo(g_2) +; RV32I-NEXT: lui a0, %hi(g_2) +; RV32I-NEXT: addi a1, a0, %lo(g_2) +; RV32I-NEXT: lw a0, 0(a1) ; RV32I-NEXT: lw a1, 4(a1) ; RV32I-NEXT: ret ; @@ -77,9 +77,9 @@ define dso_local i64 @load_g_4() nounwind { ; RV32I-LABEL: load_g_4: ; RV32I: # %bb.0: # %entry -; RV32I-NEXT: lui a1, %hi(g_4) -; RV32I-NEXT: lw a0, %lo(g_4)(a1) -; RV32I-NEXT: addi a1, a1, %lo(g_4) +; RV32I-NEXT: lui a0, %hi(g_4) +; RV32I-NEXT: addi a1, a0, %lo(g_4) +; RV32I-NEXT: lw a0, 0(a1) ; RV32I-NEXT: lw a1, 4(a1) ; RV32I-NEXT: ret ; @@ -133,9 +133,9 @@ ; RV32I-LABEL: store_g_4: ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: lui a0, %hi(g_4) -; RV32I-NEXT: sw zero, %lo(g_4)(a0) ; RV32I-NEXT: addi a0, a0, %lo(g_4) ; RV32I-NEXT: sw zero, 4(a0) +; RV32I-NEXT: sw zero, 0(a0) ; RV32I-NEXT: ret ; ; RV64I-LABEL: store_g_4: @@ -248,9 +248,9 @@ ; RV32I-LABEL: load_tl_4: ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: lui a0, %tprel_hi(tl_4) -; RV32I-NEXT: add a1, a0, tp, %tprel_add(tl_4) -; RV32I-NEXT: lw a0, %tprel_lo(tl_4)(a1) -; RV32I-NEXT: addi a1, a1, %tprel_lo(tl_4) +; RV32I-NEXT: add a0, a0, tp, %tprel_add(tl_4) +; RV32I-NEXT: addi a1, a0, %tprel_lo(tl_4) +; RV32I-NEXT: lw a0, 0(a1) ; RV32I-NEXT: lw a1, 4(a1) ; RV32I-NEXT: ret ; Index: llvm/test/CodeGen/RISCV/global-merge-minsize.ll =================================================================== --- llvm/test/CodeGen/RISCV/global-merge-minsize.ll +++ llvm/test/CodeGen/RISCV/global-merge-minsize.ll @@ -25,16 +25,12 @@ ret void } -; TODO: It would be better for code size to alter the first store below by -; first fully materialising .L_MergedGlobals in a1 and then storing to it with -; a 0 offset. - define void @f2(i32 %a) nounwind minsize optsize { ; CHECK-LABEL: f2: ; CHECK: # %bb.0: ; CHECK-NEXT: lui a1, %hi(.L_MergedGlobals) -; CHECK-NEXT: sw a0, %lo(.L_MergedGlobals)(a1) ; CHECK-NEXT: addi a1, a1, %lo(.L_MergedGlobals) +; CHECK-NEXT: sw a0, 0(a1) ; CHECK-NEXT: sw a0, 4(a1) ; CHECK-NEXT: ret store i32 %a, ptr @eg3, align 4 Index: llvm/test/CodeGen/RISCV/global-merge-offset.ll =================================================================== --- llvm/test/CodeGen/RISCV/global-merge-offset.ll +++ llvm/test/CodeGen/RISCV/global-merge-offset.ll @@ -15,27 +15,24 @@ @ga2 = dso_local global [ArrSize x i32] zeroinitializer, align 4 @gi = dso_local global i32 0, align 4 -; TODO: It would be better for codesize if the final store below was -; `sw a0, 0(a2)`. - define void @f1(i32 %a) nounwind { ; CHECK-LABEL: f1: ; CHECK: # %bb.0: ; CHECK-NEXT: lui a1, %hi(.L_MergedGlobals) -; CHECK-NEXT: addi a2, a1, %lo(.L_MergedGlobals) -; CHECK-NEXT: sw a0, 2044(a2) -; CHECK-NEXT: sw a0, 404(a2) -; CHECK-NEXT: sw a0, %lo(.L_MergedGlobals)(a1) +; CHECK-NEXT: addi a1, a1, %lo(.L_MergedGlobals) +; CHECK-NEXT: sw a0, 2044(a1) +; CHECK-NEXT: sw a0, 404(a1) +; CHECK-NEXT: sw a0, 0(a1) ; CHECK-NEXT: ret ; ; CHECK-TOOBIG-LABEL: f1: ; CHECK-TOOBIG: # %bb.0: ; CHECK-TOOBIG-NEXT: lui a1, %hi(ga1+1640) ; CHECK-TOOBIG-NEXT: lui a2, %hi(.L_MergedGlobals) -; CHECK-TOOBIG-NEXT: addi a3, a2, %lo(.L_MergedGlobals) +; CHECK-TOOBIG-NEXT: addi a2, a2, %lo(.L_MergedGlobals) ; CHECK-TOOBIG-NEXT: sw a0, %lo(ga1+1640)(a1) -; CHECK-TOOBIG-NEXT: sw a0, 408(a3) -; CHECK-TOOBIG-NEXT: sw a0, %lo(.L_MergedGlobals)(a2) +; CHECK-TOOBIG-NEXT: sw a0, 408(a2) +; CHECK-TOOBIG-NEXT: sw a0, 0(a2) ; CHECK-TOOBIG-NEXT: ret %ga1_end = getelementptr inbounds [410 x i32], ptr @ga1, i32 0, i64 410 %ga2_end = getelementptr inbounds [ArrSize x i32], ptr @ga2, i32 0, i64 ArrSize Index: llvm/test/CodeGen/RISCV/global-merge.ll =================================================================== --- llvm/test/CodeGen/RISCV/global-merge.ll +++ llvm/test/CodeGen/RISCV/global-merge.ll @@ -10,16 +10,12 @@ @eg1 = dso_local global i32 0, align 4 @eg2 = dso_local global i32 0, align 4 -; TODO: It would be better for code size to alter the first store below by -; first fully materialising .L_MergedGlobals in a1 and then storing to it with -; a 0 offset. - define void @f1(i32 %a) nounwind { ; CHECK-LABEL: f1: ; CHECK: # %bb.0: ; CHECK-NEXT: lui a1, %hi(.L_MergedGlobals) -; CHECK-NEXT: sw a0, %lo(.L_MergedGlobals)(a1) ; CHECK-NEXT: addi a1, a1, %lo(.L_MergedGlobals) +; CHECK-NEXT: sw a0, 0(a1) ; CHECK-NEXT: sw a0, 4(a1) ; CHECK-NEXT: sw a0, 8(a1) ; CHECK-NEXT: sw a0, 12(a1) Index: llvm/test/CodeGen/RISCV/half-mem.ll =================================================================== --- llvm/test/CodeGen/RISCV/half-mem.ll +++ llvm/test/CodeGen/RISCV/half-mem.ll @@ -46,11 +46,11 @@ ; CHECKIZFH: # %bb.0: ; CHECKIZFH-NEXT: fadd.h fa0, fa0, fa1 ; CHECKIZFH-NEXT: lui a0, %hi(G) -; CHECKIZFH-NEXT: flh ft0, %lo(G)(a0) -; CHECKIZFH-NEXT: addi a1, a0, %lo(G) -; CHECKIZFH-NEXT: fsh fa0, %lo(G)(a0) -; CHECKIZFH-NEXT: flh ft0, 18(a1) -; CHECKIZFH-NEXT: fsh fa0, 18(a1) +; CHECKIZFH-NEXT: addi a0, a0, %lo(G) +; CHECKIZFH-NEXT: flh ft0, 0(a0) +; CHECKIZFH-NEXT: fsh fa0, 0(a0) +; CHECKIZFH-NEXT: flh ft0, 18(a0) +; CHECKIZFH-NEXT: fsh fa0, 18(a0) ; CHECKIZFH-NEXT: ret %1 = fadd half %a, %b %2 = load volatile half, half* @G Index: llvm/test/CodeGen/RISCV/mem.ll =================================================================== --- llvm/test/CodeGen/RISCV/mem.ll +++ llvm/test/CodeGen/RISCV/mem.ll @@ -168,12 +168,12 @@ define dso_local i32 @lw_sw_global(i32 %a) nounwind { ; RV32I-LABEL: lw_sw_global: ; RV32I: # %bb.0: -; RV32I-NEXT: lui a2, %hi(G) -; RV32I-NEXT: lw a1, %lo(G)(a2) -; RV32I-NEXT: addi a3, a2, %lo(G) -; RV32I-NEXT: sw a0, %lo(G)(a2) -; RV32I-NEXT: lw a2, 36(a3) -; RV32I-NEXT: sw a0, 36(a3) +; RV32I-NEXT: lui a1, %hi(G) +; RV32I-NEXT: addi a2, a1, %lo(G) +; RV32I-NEXT: lw a1, 0(a2) +; RV32I-NEXT: sw a0, 0(a2) +; RV32I-NEXT: lw a3, 36(a2) +; RV32I-NEXT: sw a0, 36(a2) ; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: ret %1 = load volatile i32, i32* @G Index: llvm/test/CodeGen/RISCV/mem64.ll =================================================================== --- llvm/test/CodeGen/RISCV/mem64.ll +++ llvm/test/CodeGen/RISCV/mem64.ll @@ -213,12 +213,12 @@ define dso_local i64 @ld_sd_global(i64 %a) nounwind { ; RV64I-LABEL: ld_sd_global: ; RV64I: # %bb.0: -; RV64I-NEXT: lui a2, %hi(G) -; RV64I-NEXT: ld a1, %lo(G)(a2) -; RV64I-NEXT: addi a3, a2, %lo(G) -; RV64I-NEXT: sd a0, %lo(G)(a2) -; RV64I-NEXT: ld a2, 72(a3) -; RV64I-NEXT: sd a0, 72(a3) +; RV64I-NEXT: lui a1, %hi(G) +; RV64I-NEXT: addi a2, a1, %lo(G) +; RV64I-NEXT: ld a1, 0(a2) +; RV64I-NEXT: sd a0, 0(a2) +; RV64I-NEXT: ld a3, 72(a2) +; RV64I-NEXT: sd a0, 72(a2) ; RV64I-NEXT: mv a0, a1 ; RV64I-NEXT: ret %1 = load volatile i64, i64* @G Index: llvm/test/CodeGen/RISCV/memcpy-inline.ll =================================================================== --- llvm/test/CodeGen/RISCV/memcpy-inline.ll +++ llvm/test/CodeGen/RISCV/memcpy-inline.ll @@ -23,33 +23,33 @@ define i32 @t0() { ; RV32-LABEL: t0: ; RV32: # %bb.0: # %entry -; RV32-NEXT: lui a0, %hi(src) -; RV32-NEXT: lw a1, %lo(src)(a0) -; RV32-NEXT: lui a2, %hi(dst) -; RV32-NEXT: sw a1, %lo(dst)(a2) -; RV32-NEXT: addi a0, a0, %lo(src) -; RV32-NEXT: lb a1, 10(a0) -; RV32-NEXT: lh a3, 8(a0) -; RV32-NEXT: lw a0, 4(a0) -; RV32-NEXT: addi a2, a2, %lo(dst) -; RV32-NEXT: sb a1, 10(a2) -; RV32-NEXT: sh a3, 8(a2) -; RV32-NEXT: sw a0, 4(a2) +; RV32-NEXT: lui a0, %hi(dst) +; RV32-NEXT: addi a0, a0, %lo(dst) +; RV32-NEXT: lui a1, %hi(src) +; RV32-NEXT: addi a1, a1, %lo(src) +; RV32-NEXT: lb a2, 10(a1) +; RV32-NEXT: lh a3, 8(a1) +; RV32-NEXT: lw a4, 4(a1) +; RV32-NEXT: lw a1, 0(a1) +; RV32-NEXT: sb a2, 10(a0) +; RV32-NEXT: sh a3, 8(a0) +; RV32-NEXT: sw a4, 4(a0) +; RV32-NEXT: sw a1, 0(a0) ; RV32-NEXT: li a0, 0 ; RV32-NEXT: ret ; ; RV64-LABEL: t0: ; RV64: # %bb.0: # %entry -; RV64-NEXT: lui a0, %hi(src) -; RV64-NEXT: ld a1, %lo(src)(a0) -; RV64-NEXT: lui a2, %hi(dst) -; RV64-NEXT: addi a0, a0, %lo(src) -; RV64-NEXT: lb a3, 10(a0) -; RV64-NEXT: lh a0, 8(a0) -; RV64-NEXT: sd a1, %lo(dst)(a2) -; RV64-NEXT: addi a1, a2, %lo(dst) -; RV64-NEXT: sb a3, 10(a1) -; RV64-NEXT: sh a0, 8(a1) +; RV64-NEXT: lui a0, %hi(dst) +; RV64-NEXT: lui a1, %hi(src) +; RV64-NEXT: addi a1, a1, %lo(src) +; RV64-NEXT: lb a2, 10(a1) +; RV64-NEXT: lh a3, 8(a1) +; RV64-NEXT: ld a1, 0(a1) +; RV64-NEXT: addi a0, a0, %lo(dst) +; RV64-NEXT: sb a2, 10(a0) +; RV64-NEXT: sh a3, 8(a0) +; RV64-NEXT: sd a1, 0(a0) ; RV64-NEXT: li a0, 0 ; RV64-NEXT: ret entry: @@ -74,21 +74,21 @@ ; ; RV64UNALIGNED-LABEL: t1: ; RV64UNALIGNED: # %bb.0: # %entry -; RV64UNALIGNED-NEXT: lui a1, %hi(.L.str1) -; RV64UNALIGNED-NEXT: ld a2, %lo(.L.str1)(a1) -; RV64UNALIGNED-NEXT: sd a2, 0(a0) -; RV64UNALIGNED-NEXT: lui a2, 4 -; RV64UNALIGNED-NEXT: addiw a2, a2, 1870 -; RV64UNALIGNED-NEXT: sh a2, 28(a0) -; RV64UNALIGNED-NEXT: lui a2, 300325 -; RV64UNALIGNED-NEXT: addiw a2, a2, 1107 -; RV64UNALIGNED-NEXT: addi a1, a1, %lo(.L.str1) -; RV64UNALIGNED-NEXT: ld a3, 16(a1) -; RV64UNALIGNED-NEXT: ld a1, 8(a1) -; RV64UNALIGNED-NEXT: sw a2, 24(a0) -; RV64UNALIGNED-NEXT: sb zero, 30(a0) +; RV64UNALIGNED-NEXT: lui a1, 4 +; RV64UNALIGNED-NEXT: addiw a1, a1, 1870 +; RV64UNALIGNED-NEXT: sh a1, 28(a0) +; RV64UNALIGNED-NEXT: lui a1, 300325 +; RV64UNALIGNED-NEXT: addiw a1, a1, 1107 +; RV64UNALIGNED-NEXT: lui a2, %hi(.L.str1) +; RV64UNALIGNED-NEXT: addi a2, a2, %lo(.L.str1) +; RV64UNALIGNED-NEXT: ld a3, 16(a2) +; RV64UNALIGNED-NEXT: sw a1, 24(a0) +; RV64UNALIGNED-NEXT: ld a1, 8(a2) +; RV64UNALIGNED-NEXT: ld a2, 0(a2) ; RV64UNALIGNED-NEXT: sd a3, 16(a0) +; RV64UNALIGNED-NEXT: sb zero, 30(a0) ; RV64UNALIGNED-NEXT: sd a1, 8(a0) +; RV64UNALIGNED-NEXT: sd a2, 0(a0) ; RV64UNALIGNED-NEXT: ret entry: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([31 x i8], [31 x i8]* @.str1, i64 0, i64 0), i64 31, i1 false) @@ -112,19 +112,19 @@ ; ; RV64UNALIGNED-LABEL: t2: ; RV64UNALIGNED: # %bb.0: # %entry +; RV64UNALIGNED-NEXT: lui a1, 1156 +; RV64UNALIGNED-NEXT: addiw a1, a1, 332 +; RV64UNALIGNED-NEXT: sw a1, 32(a0) ; RV64UNALIGNED-NEXT: lui a1, %hi(.L.str2) -; RV64UNALIGNED-NEXT: ld a2, %lo(.L.str2)(a1) -; RV64UNALIGNED-NEXT: sd a2, 0(a0) -; RV64UNALIGNED-NEXT: lui a2, 1156 -; RV64UNALIGNED-NEXT: addiw a2, a2, 332 ; RV64UNALIGNED-NEXT: addi a1, a1, %lo(.L.str2) -; RV64UNALIGNED-NEXT: ld a3, 24(a1) -; RV64UNALIGNED-NEXT: ld a4, 16(a1) -; RV64UNALIGNED-NEXT: ld a1, 8(a1) -; RV64UNALIGNED-NEXT: sw a2, 32(a0) -; RV64UNALIGNED-NEXT: sd a3, 24(a0) -; RV64UNALIGNED-NEXT: sd a4, 16(a0) -; RV64UNALIGNED-NEXT: sd a1, 8(a0) +; RV64UNALIGNED-NEXT: ld a2, 24(a1) +; RV64UNALIGNED-NEXT: ld a3, 16(a1) +; RV64UNALIGNED-NEXT: ld a4, 8(a1) +; RV64UNALIGNED-NEXT: ld a1, 0(a1) +; RV64UNALIGNED-NEXT: sd a2, 24(a0) +; RV64UNALIGNED-NEXT: sd a3, 16(a0) +; RV64UNALIGNED-NEXT: sd a4, 8(a0) +; RV64UNALIGNED-NEXT: sd a1, 0(a0) ; RV64UNALIGNED-NEXT: ret entry: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([36 x i8], [36 x i8]* @.str2, i64 0, i64 0), i64 36, i1 false) @@ -171,13 +171,13 @@ ; RV64UNALIGNED-LABEL: t3: ; RV64UNALIGNED: # %bb.0: # %entry ; RV64UNALIGNED-NEXT: lui a1, %hi(.L.str3) -; RV64UNALIGNED-NEXT: ld a2, %lo(.L.str3)(a1) ; RV64UNALIGNED-NEXT: addi a1, a1, %lo(.L.str3) -; RV64UNALIGNED-NEXT: ld a3, 16(a1) -; RV64UNALIGNED-NEXT: ld a1, 8(a1) -; RV64UNALIGNED-NEXT: sd a2, 0(a0) -; RV64UNALIGNED-NEXT: sd a3, 16(a0) -; RV64UNALIGNED-NEXT: sd a1, 8(a0) +; RV64UNALIGNED-NEXT: ld a2, 16(a1) +; RV64UNALIGNED-NEXT: ld a3, 8(a1) +; RV64UNALIGNED-NEXT: ld a1, 0(a1) +; RV64UNALIGNED-NEXT: sd a2, 16(a0) +; RV64UNALIGNED-NEXT: sd a3, 8(a0) +; RV64UNALIGNED-NEXT: sd a1, 0(a0) ; RV64UNALIGNED-NEXT: ret entry: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([24 x i8], [24 x i8]* @.str3, i64 0, i64 0), i64 24, i1 false) @@ -220,13 +220,13 @@ ; RV64UNALIGNED-LABEL: t4: ; RV64UNALIGNED: # %bb.0: # %entry ; RV64UNALIGNED-NEXT: lui a1, %hi(.L.str4) -; RV64UNALIGNED-NEXT: ld a2, %lo(.L.str4)(a1) ; RV64UNALIGNED-NEXT: addi a1, a1, %lo(.L.str4) -; RV64UNALIGNED-NEXT: ld a1, 8(a1) +; RV64UNALIGNED-NEXT: ld a2, 8(a1) +; RV64UNALIGNED-NEXT: ld a1, 0(a1) ; RV64UNALIGNED-NEXT: li a3, 32 ; RV64UNALIGNED-NEXT: sh a3, 16(a0) -; RV64UNALIGNED-NEXT: sd a2, 0(a0) -; RV64UNALIGNED-NEXT: sd a1, 8(a0) +; RV64UNALIGNED-NEXT: sd a2, 8(a0) +; RV64UNALIGNED-NEXT: sd a1, 0(a0) ; RV64UNALIGNED-NEXT: ret entry: tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8], [18 x i8]* @.str4, i64 0, i64 0), i64 18, i1 false) Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll =================================================================== --- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store-merge-crash.ll @@ -14,13 +14,13 @@ ; CHECK-LABEL: baz: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: lui a0, %hi(foo) -; CHECK-NEXT: addi a1, a0, %lo(foo) -; CHECK-NEXT: lw a1, 4(a1) -; CHECK-NEXT: lw a0, %lo(foo)(a0) +; CHECK-NEXT: addi a0, a0, %lo(foo) +; CHECK-NEXT: lw a1, 4(a0) +; CHECK-NEXT: lw a0, 0(a0) ; CHECK-NEXT: lui a2, %hi(bar) -; CHECK-NEXT: sw a1, %lo(bar)(a2) -; CHECK-NEXT: addi a1, a2, %lo(bar) -; CHECK-NEXT: sw a0, 4(a1) +; CHECK-NEXT: addi a2, a2, %lo(bar) +; CHECK-NEXT: sw a1, 0(a2) +; CHECK-NEXT: sw a0, 4(a2) ; CHECK-NEXT: ret entry: %0 = load i32, i32* getelementptr inbounds ([2 x i32], [2 x i32]* @foo, i64 0, i64 1), align 4 Index: llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll =================================================================== --- llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll +++ llvm/test/CodeGen/RISCV/zext-with-load-is-free.ll @@ -10,12 +10,12 @@ ; RV32I-LABEL: test_zext_i8: ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: lui a0, %hi(bytes) -; RV32I-NEXT: addi a1, a0, %lo(bytes) -; RV32I-NEXT: lbu a0, %lo(bytes)(a0) -; RV32I-NEXT: lbu a1, 1(a1) -; RV32I-NEXT: xori a0, a0, 136 -; RV32I-NEXT: xori a1, a1, 7 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: addi a0, a0, %lo(bytes) +; RV32I-NEXT: lbu a1, 0(a0) +; RV32I-NEXT: lbu a0, 1(a0) +; RV32I-NEXT: xori a1, a1, 136 +; RV32I-NEXT: xori a0, a0, 7 +; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: beqz a0, .LBB0_2 ; RV32I-NEXT: # %bb.1: # %if.then ; RV32I-NEXT: li a0, 1 @@ -42,14 +42,14 @@ ; RV32I-LABEL: test_zext_i16: ; RV32I: # %bb.0: # %entry ; RV32I-NEXT: lui a0, %hi(shorts) -; RV32I-NEXT: addi a1, a0, %lo(shorts) -; RV32I-NEXT: lhu a0, %lo(shorts)(a0) -; RV32I-NEXT: lhu a1, 2(a1) +; RV32I-NEXT: addi a0, a0, %lo(shorts) +; RV32I-NEXT: lhu a1, 0(a0) +; RV32I-NEXT: lhu a0, 2(a0) ; RV32I-NEXT: lui a2, 16 ; RV32I-NEXT: addi a2, a2, -120 -; RV32I-NEXT: xor a0, a0, a2 -; RV32I-NEXT: xori a1, a1, 7 -; RV32I-NEXT: or a0, a0, a1 +; RV32I-NEXT: xor a1, a1, a2 +; RV32I-NEXT: xori a0, a0, 7 +; RV32I-NEXT: or a0, a1, a0 ; RV32I-NEXT: beqz a0, .LBB1_2 ; RV32I-NEXT: # %bb.1: # %if.then ; RV32I-NEXT: li a0, 1