diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
--- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
@@ -184,6 +184,16 @@
   if (isDefBetween(*TRI, LIS, CCReg, *Sel, *And))
     return false;
 
+  // Cannot safely mirror live intervals with PHI nodes, so check for these
+  // before optimization.
+  SlotIndex SelIdx = LIS->getInstructionIndex(*Sel);
+  LiveInterval *SelLI = &LIS->getInterval(SelReg);
+  if (llvm::any_of(SelLI->vnis(),
+                    [&](const VNInfo *VNI) {
+                      return VNI->isPHIDef();
+                    }))
+    return false;
+
   // TODO: Guard against implicit def operands?
   LLVM_DEBUG(dbgs() << "Folding sequence:\n\t" << *Sel << '\t' << *Cmp << '\t'
                     << *And);
@@ -204,31 +214,34 @@
 
   LLVM_DEBUG(dbgs() << "=>\n\t" << *Andn2 << '\n');
 
-  SlotIndex CmpIdx = LIS->getInstructionIndex(*Cmp);
-  SlotIndex SelIdx = LIS->getInstructionIndex(*Sel);
-
-  LiveInterval *CmpLI =
-      CmpReg.isVirtual() ? &LIS->getInterval(CmpReg) : nullptr;
-  LiveInterval *SelLI =
-      SelReg.isVirtual() ? &LIS->getInterval(SelReg) : nullptr;
-
   // Update live intervals for CCReg before potentially removing CmpReg/SelReg,
   // and their associated liveness information.
+  SlotIndex CmpIdx = LIS->getInstructionIndex(*Cmp);
   if (CCReg.isVirtual()) {
-    // Note: this ignores that SelLI might have multiple internal values
-    // or splits and simply extends the live range to cover all cases
-    // where the result of the v_cndmask_b32 was live (e.g. loops).
-    // This could yield worse register allocation in rare edge cases.
-    SlotIndex EndIdx = AndIdx.getRegSlot();
-    if (SelLI && SelLI->endIndex() > EndIdx && SelLI->endIndex().isBlock())
-      EndIdx = SelLI->endIndex();
+    // Apply live ranges from SelLI to CCReg potentially matching splits
+    // and extending to loop boundaries.
+
+    auto applyLiveRanges = [&](LiveRange &Dst, VNInfo *VNI) {
+      // Copy live ranges from SelLI, adjusting start and end as required
+      assert(SelLI->getSegmentContaining(SelIdx.getRegSlot()) &&
+             "No live interval segment covering defintion?");
+      for (auto I = SelLI->FindSegmentContaining(SelIdx.getRegSlot());
+                I != SelLI->end(); ++I) {
+        SlotIndex Start = I->start < SelIdx.getRegSlot() ?
+                          SelIdx.getRegSlot() : I->start;
+        SlotIndex End = I->end < AndIdx.getRegSlot() || I->end.isBlock() ?
+                        I->end : AndIdx.getRegSlot();
+        Dst.addSegment(LiveRange::Segment(Start, End, VNI));
+      }
+      // If SelLI does not cover AndIdx (because Cmp killed Sel) then extend.
+      if (!SelLI->getSegmentContaining(AndIdx.getRegSlot()))
+        Dst.addSegment(LiveRange::Segment(CmpIdx.getRegSlot(), AndIdx.getRegSlot(), VNI));
+    };
 
     LiveInterval &CCLI = LIS->getInterval(CCReg);
     auto CCQ = CCLI.Query(SelIdx.getRegSlot());
-    if (CCQ.valueIn()) {
-      CCLI.addSegment(LiveRange::Segment(SelIdx.getRegSlot(),
-                                         EndIdx, CCQ.valueIn()));
-    }
+    if (CCQ.valueIn())
+      applyLiveRanges(CCLI, CCQ.valueIn());
 
     if (CC->getSubReg()) {
       LaneBitmask Mask = TRI->getSubRegIndexLaneMask(CC->getSubReg());
@@ -237,10 +250,8 @@
           Allocator, Mask,
           [=](LiveInterval::SubRange &SR) {
             auto CCQS = SR.Query(SelIdx.getRegSlot());
-            if (CCQS.valueIn()) {
-              SR.addSegment(LiveRange::Segment(
-                  SelIdx.getRegSlot(), EndIdx, CCQS.valueIn()));
-            }
+            if (CCQS.valueIn())
+              applyLiveRanges(SR, CCQS.valueIn());
           },
           *LIS->getSlotIndexes(), *TRI);
       CCLI.removeEmptySubRanges();
@@ -253,7 +264,8 @@
 
   // Try to remove compare. Cmp value should not used in between of cmp
   // and s_and_b64 if VCC or just unused if any other register.
-  if ((CmpReg.isVirtual() && CmpLI && CmpLI->Query(AndIdx.getRegSlot()).isKill()) ||
+  LiveInterval *CmpLI = CmpReg.isVirtual() ? &LIS->getInterval(CmpReg) : nullptr;
+  if ((CmpLI && CmpLI->Query(AndIdx.getRegSlot()).isKill()) ||
       (CmpReg == Register(CondReg) &&
        std::none_of(std::next(Cmp->getIterator()), Andn2->getIterator(),
                     [&](const MachineInstr &MI) {
@@ -266,18 +278,16 @@
     Cmp->eraseFromParent();
 
     // Try to remove v_cndmask_b32.
-    if (SelLI) {
-      // Kill status must be checked before shrinking the live range.
-      bool IsKill = SelLI->Query(CmpIdx.getRegSlot()).isKill();
-      LIS->shrinkToUses(SelLI);
-      bool IsDead = SelLI->Query(SelIdx.getRegSlot()).isDeadDef();
-      if (MRI->use_nodbg_empty(SelReg) && (IsKill || IsDead)) {
-        LLVM_DEBUG(dbgs() << "Erasing: " << *Sel << '\n');
-
-        LIS->removeVRegDefAt(*SelLI, SelIdx.getRegSlot());
-        LIS->RemoveMachineInstrFromMaps(*Sel);
-        Sel->eraseFromParent();
-      }
+    // Kill status must be checked before shrinking the live range.
+    bool IsKill = SelLI->Query(CmpIdx.getRegSlot()).isKill();
+    LIS->shrinkToUses(SelLI);
+    bool IsDead = SelLI->Query(SelIdx.getRegSlot()).isDeadDef();
+    if (MRI->use_nodbg_empty(SelReg) && (IsKill || IsDead)) {
+      LLVM_DEBUG(dbgs() << "Erasing: " << *Sel << '\n');
+
+      LIS->removeVRegDefAt(*SelLI, SelIdx.getRegSlot());
+      LIS->RemoveMachineInstrFromMaps(*Sel);
+      Sel->eraseFromParent();
     }
   }
 
diff --git a/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-alloc-failure.mir b/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-alloc-failure.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-alloc-failure.mir
@@ -0,0 +1,704 @@
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -mattr=+wavefrontsize32,-wavefrontsize64 -start-before=machine-scheduler -stop-after=greedy -o - %s | FileCheck %s
+
+---
+# If optimize-exec-mask-pre-ra over approximates live intervals (not replicating splits)
+# then this triggers a register allocation failure.
+
+# CHECK-LABEL: name: test
+
+name:            test
+alignment:       1
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: sreg_64, preferred-register: '' }
+  - { id: 1, class: sreg_32, preferred-register: '' }
+  - { id: 2, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 3, class: sreg_32, preferred-register: '' }
+  - { id: 4, class: sreg_64, preferred-register: '' }
+  - { id: 5, class: sreg_64, preferred-register: '' }
+  - { id: 6, class: sreg_64, preferred-register: '' }
+  - { id: 7, class: sreg_64, preferred-register: '' }
+  - { id: 8, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 9, class: sreg_64, preferred-register: '' }
+  - { id: 10, class: sreg_64, preferred-register: '' }
+  - { id: 11, class: sreg_32, preferred-register: '' }
+  - { id: 12, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 13, class: sreg_64_xexec, preferred-register: '' }
+  - { id: 14, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 15, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 16, class: sreg_64, preferred-register: '' }
+  - { id: 17, class: sreg_64, preferred-register: '' }
+  - { id: 18, class: sreg_64, preferred-register: '' }
+  - { id: 19, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 20, class: sreg_64, preferred-register: '' }
+  - { id: 21, class: sreg_32, preferred-register: '' }
+  - { id: 22, class: vgpr_32, preferred-register: '' }
+  - { id: 23, class: sreg_64, preferred-register: '' }
+  - { id: 24, class: sreg_32, preferred-register: '' }
+  - { id: 25, class: sreg_32, preferred-register: '' }
+  - { id: 26, class: sreg_32, preferred-register: '' }
+  - { id: 27, class: vreg_64, preferred-register: '' }
+  - { id: 28, class: vreg_64, preferred-register: '' }
+  - { id: 29, class: sreg_64, preferred-register: '' }
+  - { id: 30, class: sreg_64, preferred-register: '' }
+  - { id: 31, class: sreg_64, preferred-register: '' }
+  - { id: 32, class: sreg_64, preferred-register: '' }
+  - { id: 33, class: vgpr_32, preferred-register: '' }
+  - { id: 34, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 35, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 36, class: sreg_64, preferred-register: '' }
+  - { id: 37, class: vreg_64, preferred-register: '' }
+  - { id: 38, class: vreg_64, preferred-register: '' }
+  - { id: 39, class: sreg_64, preferred-register: '' }
+  - { id: 40, class: sreg_64, preferred-register: '' }
+  - { id: 41, class: sreg_64, preferred-register: '' }
+  - { id: 42, class: sreg_64, preferred-register: '' }
+  - { id: 43, class: vreg_64, preferred-register: '' }
+  - { id: 44, class: vreg_64, preferred-register: '' }
+  - { id: 45, class: sreg_32, preferred-register: '' }
+  - { id: 46, class: sreg_32, preferred-register: '' }
+  - { id: 47, class: sreg_32, preferred-register: '' }
+  - { id: 48, class: sreg_32, preferred-register: '' }
+  - { id: 49, class: sreg_64, preferred-register: '' }
+  - { id: 50, class: sreg_64, preferred-register: '' }
+  - { id: 51, class: sreg_64, preferred-register: '' }
+  - { id: 52, class: sreg_64, preferred-register: '' }
+  - { id: 53, class: sreg_64, preferred-register: '' }
+  - { id: 54, class: sreg_64, preferred-register: '' }
+  - { id: 55, class: sreg_64, preferred-register: '' }
+  - { id: 56, class: sreg_64, preferred-register: '' }
+  - { id: 57, class: vreg_64, preferred-register: '' }
+  - { id: 58, class: vreg_64, preferred-register: '' }
+  - { id: 59, class: vreg_1, preferred-register: '' }
+  - { id: 60, class: sreg_32, preferred-register: '' }
+  - { id: 61, class: sreg_32, preferred-register: '' }
+  - { id: 62, class: vreg_64, preferred-register: '' }
+  - { id: 63, class: vreg_64, preferred-register: '' }
+  - { id: 64, class: vgpr_32, preferred-register: '' }
+  - { id: 65, class: sgpr_128, preferred-register: '' }
+  - { id: 66, class: sgpr_64, preferred-register: '' }
+  - { id: 67, class: sgpr_32, preferred-register: '' }
+  - { id: 68, class: sgpr_32, preferred-register: '' }
+  - { id: 69, class: sreg_32, preferred-register: '' }
+  - { id: 70, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 71, class: sreg_32, preferred-register: '' }
+  - { id: 72, class: sreg_32, preferred-register: '' }
+  - { id: 73, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 74, class: sreg_64_xexec, preferred-register: '' }
+  - { id: 75, class: sreg_32, preferred-register: '' }
+  - { id: 76, class: sreg_64, preferred-register: '' }
+  - { id: 77, class: sreg_64_xexec, preferred-register: '' }
+  - { id: 78, class: sgpr_128, preferred-register: '' }
+  - { id: 79, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 80, class: sgpr_128, preferred-register: '' }
+  - { id: 81, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 82, class: sreg_32, preferred-register: '' }
+  - { id: 83, class: sreg_32, preferred-register: '' }
+  - { id: 84, class: sreg_64, preferred-register: '' }
+  - { id: 85, class: sreg_32, preferred-register: '' }
+  - { id: 86, class: sreg_32, preferred-register: '' }
+  - { id: 87, class: sreg_64, preferred-register: '' }
+  - { id: 88, class: sreg_32, preferred-register: '' }
+  - { id: 89, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 90, class: sreg_32, preferred-register: '' }
+  - { id: 91, class: sreg_32, preferred-register: '' }
+  - { id: 92, class: sreg_64, preferred-register: '' }
+  - { id: 93, class: sreg_32, preferred-register: '' }
+  - { id: 94, class: sreg_32, preferred-register: '' }
+  - { id: 95, class: sreg_64, preferred-register: '' }
+  - { id: 96, class: sreg_32, preferred-register: '' }
+  - { id: 97, class: sreg_32, preferred-register: '' }
+  - { id: 98, class: sreg_32, preferred-register: '' }
+  - { id: 99, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 100, class: sreg_64_xexec, preferred-register: '' }
+  - { id: 101, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 102, class: sreg_32, preferred-register: '' }
+  - { id: 103, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 104, class: sreg_32, preferred-register: '' }
+  - { id: 105, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 106, class: sreg_64_xexec, preferred-register: '' }
+  - { id: 107, class: sgpr_128, preferred-register: '' }
+  - { id: 108, class: sreg_32, preferred-register: '' }
+  - { id: 109, class: sreg_32, preferred-register: '' }
+  - { id: 110, class: sreg_64, preferred-register: '' }
+  - { id: 111, class: sreg_32, preferred-register: '' }
+  - { id: 112, class: sreg_32, preferred-register: '' }
+  - { id: 113, class: sreg_64, preferred-register: '' }
+  - { id: 114, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 115, class: sreg_32, preferred-register: '' }
+  - { id: 116, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 117, class: sreg_64_xexec, preferred-register: '' }
+  - { id: 118, class: sreg_64, preferred-register: '' }
+  - { id: 119, class: sreg_64_xexec, preferred-register: '' }
+  - { id: 120, class: sreg_64, preferred-register: '' }
+  - { id: 121, class: sreg_32, preferred-register: '' }
+  - { id: 122, class: sreg_32, preferred-register: '' }
+  - { id: 123, class: sreg_64_xexec, preferred-register: '%132' }
+  - { id: 124, class: vreg_64, preferred-register: '' }
+  - { id: 125, class: vreg_64, preferred-register: '' }
+  - { id: 126, class: vgpr_32, preferred-register: '' }
+  - { id: 127, class: sreg_32, preferred-register: '' }
+  - { id: 128, class: sreg_32, preferred-register: '' }
+  - { id: 129, class: sreg_64, preferred-register: '' }
+  - { id: 130, class: sreg_32, preferred-register: '' }
+  - { id: 131, class: sreg_32, preferred-register: '' }
+  - { id: 132, class: sreg_32, preferred-register: '%123' }
+  - { id: 133, class: sreg_32, preferred-register: '' }
+  - { id: 134, class: sreg_32, preferred-register: '' }
+  - { id: 135, class: sreg_64, preferred-register: '' }
+  - { id: 136, class: vgpr_32, preferred-register: '' }
+  - { id: 137, class: vreg_64, preferred-register: '' }
+  - { id: 138, class: sreg_32, preferred-register: '' }
+  - { id: 139, class: sreg_32, preferred-register: '' }
+  - { id: 140, class: sreg_64, preferred-register: '' }
+  - { id: 141, class: sreg_64, preferred-register: '' }
+  - { id: 142, class: vreg_64, preferred-register: '' }
+  - { id: 143, class: vreg_64, preferred-register: '' }
+  - { id: 144, class: sreg_32, preferred-register: '' }
+  - { id: 145, class: sreg_32, preferred-register: '' }
+  - { id: 146, class: sreg_64, preferred-register: '' }
+  - { id: 147, class: sreg_32, preferred-register: '$vcc_lo' }
+  - { id: 148, class: sreg_32, preferred-register: '' }
+  - { id: 149, class: sreg_64, preferred-register: '' }
+  - { id: 150, class: sreg_32, preferred-register: '$vcc_lo' }
+  - { id: 151, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 152, class: sreg_32, preferred-register: '' }
+  - { id: 153, class: vgpr_32, preferred-register: '' }
+  - { id: 154, class: vgpr_32, preferred-register: '' }
+  - { id: 155, class: sreg_32, preferred-register: '' }
+  - { id: 156, class: vgpr_32, preferred-register: '' }
+  - { id: 157, class: vgpr_32, preferred-register: '' }
+  - { id: 158, class: sreg_64, preferred-register: '' }
+  - { id: 159, class: sreg_64, preferred-register: '' }
+  - { id: 160, class: sreg_32, preferred-register: '' }
+  - { id: 161, class: sreg_32, preferred-register: '' }
+  - { id: 162, class: sreg_32, preferred-register: '' }
+  - { id: 163, class: vgpr_32, preferred-register: '' }
+  - { id: 164, class: vgpr_32, preferred-register: '' }
+  - { id: 165, class: sreg_32, preferred-register: '' }
+  - { id: 166, class: sreg_32, preferred-register: '' }
+  - { id: 167, class: vgpr_32, preferred-register: '' }
+  - { id: 168, class: vgpr_32, preferred-register: '' }
+  - { id: 169, class: sreg_32, preferred-register: '' }
+  - { id: 170, class: vgpr_32, preferred-register: '' }
+  - { id: 171, class: sreg_32, preferred-register: '' }
+  - { id: 172, class: sreg_32, preferred-register: '' }
+  - { id: 173, class: sreg_32, preferred-register: '' }
+  - { id: 174, class: sreg_32, preferred-register: '' }
+  - { id: 175, class: vgpr_32, preferred-register: '' }
+  - { id: 176, class: sreg_64, preferred-register: '' }
+  - { id: 177, class: vreg_64, preferred-register: '' }
+  - { id: 178, class: vreg_64, preferred-register: '' }
+  - { id: 179, class: vreg_64, preferred-register: '' }
+  - { id: 180, class: sreg_32, preferred-register: '' }
+  - { id: 181, class: sreg_64, preferred-register: '' }
+  - { id: 182, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 183, class: sreg_64, preferred-register: '' }
+  - { id: 184, class: sreg_32, preferred-register: '' }
+  - { id: 185, class: sreg_32, preferred-register: '' }
+  - { id: 186, class: sgpr_32, preferred-register: '' }
+  - { id: 187, class: sreg_32, preferred-register: '' }
+  - { id: 188, class: vgpr_32, preferred-register: '' }
+  - { id: 189, class: sgpr_32, preferred-register: '' }
+  - { id: 190, class: sreg_32, preferred-register: '' }
+  - { id: 191, class: vgpr_32, preferred-register: '' }
+  - { id: 192, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 193, class: sreg_32, preferred-register: '' }
+  - { id: 194, class: sreg_64, preferred-register: '' }
+  - { id: 195, class: vreg_64, preferred-register: '' }
+  - { id: 196, class: sreg_32, preferred-register: '' }
+  - { id: 197, class: sreg_32, preferred-register: '' }
+  - { id: 198, class: sreg_64, preferred-register: '' }
+  - { id: 199, class: sreg_32, preferred-register: '' }
+  - { id: 200, class: sreg_32, preferred-register: '' }
+  - { id: 201, class: sreg_64, preferred-register: '' }
+  - { id: 202, class: vreg_64, preferred-register: '' }
+  - { id: 203, class: sreg_32, preferred-register: '' }
+  - { id: 204, class: sreg_32, preferred-register: '' }
+  - { id: 205, class: sreg_64, preferred-register: '' }
+  - { id: 206, class: vreg_64, preferred-register: '' }
+  - { id: 207, class: sreg_32, preferred-register: '' }
+  - { id: 208, class: sreg_32, preferred-register: '' }
+  - { id: 209, class: sreg_64, preferred-register: '' }
+  - { id: 210, class: vreg_64, preferred-register: '' }
+  - { id: 211, class: sreg_32, preferred-register: '' }
+  - { id: 212, class: sreg_32, preferred-register: '' }
+  - { id: 213, class: sreg_64, preferred-register: '' }
+  - { id: 214, class: vreg_64, preferred-register: '' }
+  - { id: 215, class: sreg_32, preferred-register: '' }
+  - { id: 216, class: sreg_32, preferred-register: '' }
+  - { id: 217, class: sreg_64, preferred-register: '' }
+  - { id: 218, class: vreg_64, preferred-register: '' }
+  - { id: 219, class: sreg_32, preferred-register: '' }
+  - { id: 220, class: sreg_32, preferred-register: '' }
+  - { id: 221, class: sreg_64, preferred-register: '' }
+  - { id: 222, class: vreg_64, preferred-register: '' }
+  - { id: 223, class: sreg_32, preferred-register: '' }
+  - { id: 224, class: sreg_32, preferred-register: '' }
+  - { id: 225, class: sreg_64, preferred-register: '' }
+  - { id: 226, class: vreg_64, preferred-register: '' }
+  - { id: 227, class: sreg_32, preferred-register: '' }
+  - { id: 228, class: sreg_32, preferred-register: '' }
+  - { id: 229, class: sreg_64, preferred-register: '' }
+  - { id: 230, class: vreg_64, preferred-register: '' }
+  - { id: 231, class: sreg_32, preferred-register: '' }
+  - { id: 232, class: sreg_32, preferred-register: '' }
+  - { id: 233, class: sreg_64, preferred-register: '' }
+  - { id: 234, class: vreg_64, preferred-register: '' }
+  - { id: 235, class: sreg_32, preferred-register: '' }
+  - { id: 236, class: sreg_64, preferred-register: '' }
+  - { id: 237, class: vreg_64, preferred-register: '' }
+  - { id: 238, class: vreg_64, preferred-register: '' }
+  - { id: 239, class: vreg_64, preferred-register: '' }
+  - { id: 240, class: sreg_32, preferred-register: '' }
+  - { id: 241, class: sreg_32, preferred-register: '' }
+  - { id: 242, class: sreg_64, preferred-register: '' }
+  - { id: 243, class: vreg_64, preferred-register: '' }
+  - { id: 244, class: sreg_32, preferred-register: '' }
+  - { id: 245, class: sreg_32, preferred-register: '' }
+  - { id: 246, class: sreg_64, preferred-register: '' }
+  - { id: 247, class: vreg_64, preferred-register: '' }
+  - { id: 248, class: sreg_32, preferred-register: '' }
+  - { id: 249, class: sreg_32, preferred-register: '' }
+  - { id: 250, class: sreg_64, preferred-register: '' }
+  - { id: 251, class: sreg_32, preferred-register: '' }
+  - { id: 252, class: sreg_32, preferred-register: '' }
+  - { id: 253, class: sreg_64, preferred-register: '' }
+  - { id: 254, class: vreg_64, preferred-register: '' }
+  - { id: 255, class: sreg_32, preferred-register: '' }
+  - { id: 256, class: sreg_32, preferred-register: '' }
+  - { id: 257, class: sreg_64, preferred-register: '' }
+  - { id: 258, class: vreg_64, preferred-register: '' }
+  - { id: 259, class: sreg_32, preferred-register: '' }
+  - { id: 260, class: sreg_32, preferred-register: '' }
+  - { id: 261, class: sreg_64, preferred-register: '' }
+  - { id: 262, class: vreg_64, preferred-register: '' }
+  - { id: 263, class: sreg_32, preferred-register: '' }
+  - { id: 264, class: sreg_32, preferred-register: '' }
+  - { id: 265, class: sreg_64, preferred-register: '' }
+  - { id: 266, class: vreg_64, preferred-register: '' }
+  - { id: 267, class: sreg_32, preferred-register: '' }
+  - { id: 268, class: sreg_32, preferred-register: '' }
+  - { id: 269, class: sreg_64, preferred-register: '' }
+  - { id: 270, class: vreg_64, preferred-register: '' }
+  - { id: 271, class: sreg_32, preferred-register: '' }
+  - { id: 272, class: sreg_32, preferred-register: '' }
+  - { id: 273, class: sreg_64, preferred-register: '' }
+  - { id: 274, class: vreg_64, preferred-register: '' }
+  - { id: 275, class: sreg_32, preferred-register: '' }
+  - { id: 276, class: sreg_32, preferred-register: '' }
+  - { id: 277, class: sreg_64, preferred-register: '' }
+  - { id: 278, class: vreg_64, preferred-register: '' }
+  - { id: 279, class: sreg_32, preferred-register: '' }
+  - { id: 280, class: sreg_32, preferred-register: '' }
+  - { id: 281, class: sreg_64, preferred-register: '' }
+  - { id: 282, class: vreg_64, preferred-register: '' }
+  - { id: 283, class: sreg_32, preferred-register: '' }
+  - { id: 284, class: sreg_32, preferred-register: '' }
+  - { id: 285, class: sreg_64, preferred-register: '' }
+  - { id: 286, class: vreg_64, preferred-register: '' }
+  - { id: 287, class: vreg_64, preferred-register: '' }
+  - { id: 288, class: vreg_64, preferred-register: '' }
+  - { id: 289, class: vreg_64, preferred-register: '' }
+  - { id: 290, class: vreg_64, preferred-register: '' }
+  - { id: 291, class: vreg_64, preferred-register: '' }
+  - { id: 292, class: vreg_64, preferred-register: '' }
+  - { id: 293, class: vreg_64, preferred-register: '' }
+  - { id: 294, class: vreg_64, preferred-register: '' }
+  - { id: 295, class: sreg_32, preferred-register: '' }
+  - { id: 296, class: sreg_64, preferred-register: '' }
+  - { id: 297, class: vreg_64, preferred-register: '' }
+  - { id: 298, class: vreg_64, preferred-register: '' }
+  - { id: 299, class: vreg_64, preferred-register: '' }
+  - { id: 300, class: vreg_64, preferred-register: '' }
+  - { id: 301, class: vreg_64, preferred-register: '' }
+  - { id: 302, class: vreg_64, preferred-register: '' }
+  - { id: 303, class: vreg_64, preferred-register: '' }
+  - { id: 304, class: vreg_64, preferred-register: '' }
+  - { id: 305, class: vreg_64, preferred-register: '' }
+  - { id: 306, class: sreg_32, preferred-register: '$vcc_lo' }
+  - { id: 307, class: sreg_32, preferred-register: '' }
+  - { id: 308, class: sreg_32, preferred-register: '' }
+  - { id: 309, class: sreg_32, preferred-register: '' }
+  - { id: 310, class: sreg_32, preferred-register: '' }
+  - { id: 311, class: sreg_32, preferred-register: '' }
+  - { id: 312, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 313, class: sreg_32, preferred-register: '' }
+  - { id: 314, class: sreg_32, preferred-register: '' }
+  - { id: 315, class: sreg_32, preferred-register: '' }
+  - { id: 316, class: sreg_32, preferred-register: '' }
+  - { id: 317, class: vgpr_32, preferred-register: '' }
+  - { id: 318, class: sreg_32, preferred-register: '' }
+  - { id: 319, class: sreg_32, preferred-register: '' }
+  - { id: 320, class: vgpr_32, preferred-register: '' }
+  - { id: 321, class: sreg_32, preferred-register: '' }
+  - { id: 322, class: sreg_32, preferred-register: '' }
+  - { id: 323, class: vgpr_32, preferred-register: '' }
+  - { id: 324, class: sreg_32, preferred-register: '' }
+  - { id: 325, class: sreg_32, preferred-register: '' }
+  - { id: 326, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 327, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 328, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 329, class: sreg_32_xm0_xexec, preferred-register: '$vcc_lo' }
+  - { id: 330, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 331, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 332, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 333, class: vreg_1, preferred-register: '' }
+  - { id: 334, class: vreg_64, preferred-register: '' }
+  - { id: 335, class: vreg_64, preferred-register: '' }
+  - { id: 336, class: vgpr_32, preferred-register: '' }
+  - { id: 337, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 338, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 339, class: sreg_32_xm0_xexec, preferred-register: '$vcc_lo' }
+  - { id: 340, class: vreg_64, preferred-register: '' }
+  - { id: 341, class: vreg_64, preferred-register: '' }
+  - { id: 342, class: vreg_64, preferred-register: '' }
+  - { id: 343, class: vreg_64, preferred-register: '' }
+  - { id: 344, class: vreg_64, preferred-register: '' }
+  - { id: 345, class: vreg_64, preferred-register: '' }
+  - { id: 346, class: vreg_64, preferred-register: '' }
+  - { id: 347, class: vreg_64, preferred-register: '' }
+  - { id: 348, class: vreg_64, preferred-register: '' }
+  - { id: 349, class: vreg_64, preferred-register: '' }
+  - { id: 350, class: vreg_64, preferred-register: '' }
+  - { id: 351, class: vreg_64, preferred-register: '' }
+  - { id: 352, class: vreg_64, preferred-register: '' }
+  - { id: 353, class: vreg_64, preferred-register: '' }
+  - { id: 354, class: vreg_64, preferred-register: '' }
+  - { id: 355, class: vreg_64, preferred-register: '' }
+  - { id: 356, class: vreg_64, preferred-register: '' }
+  - { id: 357, class: vreg_64, preferred-register: '' }
+  - { id: 358, class: vreg_64, preferred-register: '' }
+  - { id: 359, class: vreg_64, preferred-register: '' }
+  - { id: 360, class: vreg_64, preferred-register: '' }
+  - { id: 361, class: vreg_64, preferred-register: '' }
+  - { id: 362, class: vreg_1, preferred-register: '' }
+  - { id: 363, class: vreg_64, preferred-register: '' }
+  - { id: 364, class: vreg_64, preferred-register: '' }
+  - { id: 365, class: vreg_64, preferred-register: '' }
+  - { id: 366, class: vgpr_32, preferred-register: '' }
+  - { id: 367, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 368, class: vgpr_32, preferred-register: '' }
+  - { id: 369, class: vreg_64, preferred-register: '' }
+  - { id: 370, class: vgpr_32, preferred-register: '' }
+  - { id: 371, class: sreg_32, preferred-register: '' }
+  - { id: 372, class: sreg_32_xm0_xexec, preferred-register: '' }
+  - { id: 373, class: vgpr_32, preferred-register: '' }
+  - { id: 374, class: vreg_64, preferred-register: '' }
+  - { id: 375, class: sreg_32, preferred-register: '' }
+  - { id: 376, class: sreg_32, preferred-register: '' }
+  - { id: 377, class: sreg_32_xm0_xexec, preferred-register: '$vcc_lo' }
+  - { id: 378, class: sreg_32_xm0_xexec, preferred-register: '$vcc_lo' }
+  - { id: 379, class: sreg_32_xm0_xexec, preferred-register: '$vcc_lo' }
+  - { id: 380, class: vreg_1, preferred-register: '' }
+  - { id: 381, class: sreg_32, preferred-register: '' }
+  - { id: 382, class: sreg_32, preferred-register: '' }
+  - { id: 383, class: sreg_32, preferred-register: '' }
+  - { id: 384, class: sreg_32, preferred-register: '' }
+  - { id: 385, class: sreg_32, preferred-register: '' }
+  - { id: 386, class: sreg_32, preferred-register: '' }
+  - { id: 387, class: sreg_32, preferred-register: '' }
+  - { id: 388, class: sreg_32, preferred-register: '' }
+  - { id: 389, class: sreg_32, preferred-register: '' }
+  - { id: 390, class: sreg_32, preferred-register: '' }
+  - { id: 391, class: sreg_32, preferred-register: '' }
+  - { id: 392, class: sreg_32, preferred-register: '' }
+  - { id: 393, class: sreg_32, preferred-register: '' }
+  - { id: 394, class: sreg_32, preferred-register: '' }
+  - { id: 395, class: vreg_64, preferred-register: '' }
+  - { id: 396, class: vreg_64, preferred-register: '' }
+  - { id: 397, class: vreg_64, preferred-register: '' }
+  - { id: 398, class: vreg_64, preferred-register: '' }
+  - { id: 399, class: vreg_64, preferred-register: '' }
+  - { id: 400, class: vreg_64, preferred-register: '' }
+  - { id: 401, class: vgpr_32, preferred-register: '' }
+  - { id: 402, class: sreg_32, preferred-register: '' }
+  - { id: 403, class: vreg_64, preferred-register: '' }
+  - { id: 404, class: vreg_64, preferred-register: '' }
+  - { id: 405, class: vreg_64, preferred-register: '' }
+  - { id: 406, class: vreg_64, preferred-register: '' }
+  - { id: 407, class: vreg_64, preferred-register: '' }
+  - { id: 408, class: vreg_64, preferred-register: '' }
+  - { id: 409, class: sreg_32, preferred-register: '' }
+  - { id: 410, class: sreg_64, preferred-register: '' }
+  - { id: 411, class: vreg_64, preferred-register: '' }
+  - { id: 412, class: sreg_32, preferred-register: '' }
+  - { id: 413, class: sreg_32, preferred-register: '' }
+liveins:
+  - { reg: '$sgpr4_sgpr5', virtual-reg: '%66' }
+machineFunctionInfo:
+  isEntryFunction: true
+  scratchRSrcReg:  '$sgpr100_sgpr101_sgpr102_sgpr103'
+  stackPtrOffsetReg: '$sgpr32'
+body:             |
+  bb.0.entry:
+    liveins: $vgpr0, $sgpr4_sgpr5
+
+    %66:sgpr_64(p4) = COPY $sgpr4_sgpr5
+    %33:vgpr_32 = COPY $vgpr0
+    %70:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %66(p4), 16, 0
+    S_BITCMP1_B32 %70, 0, implicit-def $scc
+    %326:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit killed $scc
+    %388:sreg_32 = S_MOV_B32 -1
+    %74:sreg_64_xexec = S_LOAD_DWORDX2_IMM %66(p4), 136, 0
+    S_CBRANCH_SCC1 %bb.2, implicit undef $scc
+    S_BRANCH %bb.1
+
+  bb.1:
+    %77:sreg_64_xexec = S_LOAD_DWORDX2_IMM %66(p4), 8, 0
+    %78:sgpr_128 = S_LOAD_DWORDX4_IMM %66(p4), 24, 0
+    %79:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %66(p4), 40, 0
+    %80:sgpr_128 = S_LOAD_DWORDX4_IMM %66(p4), 48, 0
+    %81:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %66(p4), 64, 0
+    S_BITCMP1_B32 %79, 0, implicit-def $scc
+    %327:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit killed $scc
+    S_BITCMP1_B32 %81, 0, implicit-def $scc
+    %328:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit killed $scc
+    S_BITCMP1_B32 %81, 8, implicit-def $scc
+    %329:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit killed $scc
+    %13:sreg_64_xexec = S_LOAD_DWORDX2_IMM %66(p4), 72, 0
+    %101:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %66(p4), 80, 0
+    S_BITCMP1_B32 %101, 0, implicit-def $scc
+    %330:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit killed $scc
+    S_BITCMP1_B32 %101, 8, implicit-def $scc
+    %331:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit killed $scc
+    %106:sreg_64_xexec = S_LOAD_DWORDX2_IMM %66(p4), 88, 0
+    %107:sgpr_128 = S_LOAD_DWORDX4_IMM %66(p4), 104, 0
+    %114:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %66(p4), 120, 0
+    S_BITCMP1_B32 %114, 0, implicit-def $scc
+    %332:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit killed $scc
+    %117:sreg_64_xexec = S_LOAD_DWORDX2_IMM %66(p4), 128, 0
+    %118:sreg_64 = S_MOV_B64 0
+    %119:sreg_64_xexec = S_LOAD_DWORDX2_IMM %118, 0, 0
+    %146:sreg_64 = S_MOV_B64_IMM_PSEUDO 4652218415073722368
+    %27:vreg_64 = V_MOV_B64_PSEUDO 0, implicit $exec
+    %126:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %327, implicit $exec
+    %140:sreg_64 = S_MOV_B64_IMM_PSEUDO 4358002977218854975
+    undef %149.sub1:sreg_64 = S_MOV_B32 -1064252416
+    %171:sreg_32 = S_OR_B32 %331, %330, implicit-def dead $scc
+    undef %181.sub1:sreg_64 = S_MOV_B32 2146435072
+    %198:sreg_64 = S_MOV_B64_IMM_PSEUDO 4592094252754343337
+    %201:sreg_64 = S_MOV_B64_IMM_PSEUDO 4593089322246397463
+    %205:sreg_64 = S_MOV_B64_IMM_PSEUDO 4593150332132823898
+    %209:sreg_64 = S_MOV_B64_IMM_PSEUDO 4593971714784152002
+    %213:sreg_64 = S_MOV_B64_IMM_PSEUDO 4594710915293070409
+    %217:sreg_64 = S_MOV_B64_IMM_PSEUDO 4595718710613720112
+    %221:sreg_64 = S_MOV_B64_IMM_PSEUDO 4597174419628462798
+    %225:sreg_64 = S_MOV_B64_IMM_PSEUDO 4598818590920614106
+    %229:sreg_64 = S_MOV_B64_IMM_PSEUDO 4600877379321698716
+    %233:sreg_64 = S_MOV_B64_IMM_PSEUDO 4604180019048437077
+    undef %236.sub1:sreg_64 = S_MOV_B32 -1075489451
+    %242:sreg_64 = S_MOV_B64_IMM_PSEUDO 4609176140021203710
+    undef %246.sub1:sreg_64 = S_MOV_B32 -1132807010
+    %250:sreg_64 = S_MOV_B64_IMM_PSEUDO 4508818957471820556
+    %253:sreg_64 = S_MOV_B64_IMM_PSEUDO 4493147761815702327
+    %257:sreg_64 = S_MOV_B64_IMM_PSEUDO 4523617260404727396
+    %261:sreg_64 = S_MOV_B64_IMM_PSEUDO 4537941333260232368
+    %265:sreg_64 = S_MOV_B64_IMM_PSEUDO 4551452160460988270
+    %269:sreg_64 = S_MOV_B64_IMM_PSEUDO 4564047942395279280
+    %273:sreg_64 = S_MOV_B64_IMM_PSEUDO 4575957461383652130
+    %277:sreg_64 = S_MOV_B64_IMM_PSEUDO 4586165620538933921
+    %281:sreg_64 = S_MOV_B64_IMM_PSEUDO 4595172819793696017
+    %285:sreg_64 = S_MOV_B64_IMM_PSEUDO 4602678819172646923
+    undef %296.sub1:sreg_64 = S_MOV_B32 -1101341163
+    %388:sreg_32 = IMPLICIT_DEF
+    %393:sreg_32 = IMPLICIT_DEF
+    %26:sreg_32 = COPY %146.sub0
+    %28:vreg_64 = COPY %27
+    %358:vreg_64 = COPY %27
+    %353:vreg_64 = COPY %27
+    %348:vreg_64 = COPY %27
+    %343:vreg_64 = COPY %27
+    S_BRANCH %bb.3
+
+  bb.2:
+    %25:sreg_32 = COPY $exec_lo, implicit-def $exec_lo
+    %412:sreg_32 = S_AND_B32 %25, %388, implicit-def dead $scc
+    $exec_lo = S_MOV_B32_term %412
+    S_CBRANCH_EXECZ %bb.20, implicit $exec
+    S_BRANCH %bb.5
+
+  bb.3:
+    %122:sreg_32 = S_AND_B32 $exec_lo, %326, implicit-def dead $scc
+    $vcc_lo = COPY %122
+    %393:sreg_32 = S_OR_B32 %393, $exec_lo, implicit-def dead $scc
+    S_CBRANCH_VCCNZ %bb.7, implicit killed $vcc
+
+  bb.4:
+    %343:vreg_64 = IMPLICIT_DEF
+    %348:vreg_64 = IMPLICIT_DEF
+    %353:vreg_64 = IMPLICIT_DEF
+    %358:vreg_64 = IMPLICIT_DEF
+    %28:vreg_64 = IMPLICIT_DEF
+    %27:vreg_64 = IMPLICIT_DEF
+    %409:sreg_32 = S_MOV_B32 -1
+    S_BRANCH %bb.9
+
+  bb.5:
+    S_CBRANCH_SCC1 %bb.20, implicit undef $scc
+
+  bb.6:
+    %2:sreg_32_xm0_xexec = S_XOR_B32 %326, -1, implicit-def dead $scc
+    %73:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %66(p4), 96, 0
+    S_BITCMP1_B32 %73, 0, implicit-def $scc
+    %337:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit killed $scc
+    S_BITCMP1_B32 %74.sub1, 0, implicit-def $scc
+    %338:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit killed $scc
+    %35:sreg_32_xm0_xexec = S_XOR_B32 %338, -1, implicit-def dead $scc
+    %317:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %35, implicit $exec
+    %320:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %337, implicit $exec
+    %323:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %2, implicit $exec
+    S_BRANCH %bb.14
+
+  bb.7:
+    %124:vreg_64 = COPY %78.sub0_sub1
+    %37:vreg_64 = FLAT_LOAD_DWORDX2 %124, 0, 0, implicit $exec, implicit $flat_scr
+    %125:vreg_64 = COPY %78.sub2_sub3
+    %38:vreg_64 = FLAT_LOAD_DWORDX2 %125, 0, 0, implicit $exec, implicit $flat_scr
+    %339:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %126, implicit $exec
+    $vcc_lo = S_AND_B32 $exec_lo, %339, implicit-def dead $scc
+    %410:sreg_64 = COPY %80.sub0_sub1
+    S_CBRANCH_VCCNZ %bb.10, implicit killed $vcc
+    S_BRANCH %bb.8
+
+  bb.8:
+    %410:sreg_64 = S_MOV_B64 0
+    S_BRANCH %bb.10
+
+  bb.9:
+    %47:sreg_32 = S_XOR_B32 %409, -1, implicit-def dead $scc
+    %413:sreg_32 = S_AND_B32 $exec_lo, %393, implicit-def $scc
+    %26:sreg_32 = S_OR_B32 %413, %26, implicit-def $scc
+    %33:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %389:sreg_32 = S_ANDN2_B32 %388, $exec_lo, implicit-def dead $scc
+    %390:sreg_32 = S_AND_B32 %47, $exec_lo, implicit-def dead $scc
+    %388:sreg_32 = S_OR_B32 %389, %390, implicit-def dead $scc
+    $exec_lo = S_ANDN2_B32_term $exec_lo, %26, implicit-def $scc
+    S_CBRANCH_EXECNZ %bb.3, implicit $exec
+    S_BRANCH %bb.21
+
+  bb.10:
+    %123:sreg_64_xexec = S_LOAD_DWORDX2_IMM %119, 16, 0
+    undef %135.sub1:sreg_64 = S_AND_B32 %123.sub1, 2147483647, implicit-def dead $scc
+    %136:vgpr_32 = nofpexcept V_FREXP_EXP_I32_F64_e64 2, %123, 0, 0, implicit $mode, implicit $exec
+    %137:vreg_64 = V_CVT_F64_I32_e32 %136, implicit $mode, implicit $exec
+    %142:vreg_64 = nofpexcept V_FMA_F64_e64 0, 0, 0, %140, 0, %123, 0, 0, implicit $mode, implicit $exec
+    %147:sreg_32 = nofpexcept V_CMP_LT_F64_e64 0, %146, 0, %142, 0, implicit $mode, implicit $exec
+    %149.sub0:sreg_64 = COPY %146.sub0
+    %150:sreg_32 = nofpexcept V_CMP_GT_F64_e64 0, %149, 0, %137, 0, implicit $mode, implicit $exec
+    S_CBRANCH_SCC0 %bb.12, implicit undef $scc
+
+  bb.11:
+    %151:sreg_32_xm0_xexec = S_OR_B32 %150, %147, implicit-def dead $scc
+    undef %411.sub1:vreg_64 = V_CNDMASK_B32_e64 0, %107.sub3, 0, 0, %151, implicit $exec
+    %411.sub0:vreg_64 = V_CNDMASK_B32_e64 0, %107.sub2, 0, 0, %151, implicit $exec
+    S_BRANCH %bb.13
+
+  bb.12:
+    %411:vreg_64 = V_MOV_B64_PSEUDO 0, implicit $exec
+
+  bb.13:
+    %135.sub0:sreg_64 = COPY %123.sub0
+    %164:vgpr_32 = COPY %13.sub0
+    %163:vgpr_32 = V_CNDMASK_B32_e64 0, %410.sub0, 0, %164, %329, implicit $exec
+    %168:vgpr_32 = COPY %13.sub1
+    %167:vgpr_32 = V_CNDMASK_B32_e64 0, %410.sub1, 0, %168, %329, implicit $exec
+    %170:vgpr_32 = V_CNDMASK_B32_e64 0, %167, 0, 2146959360, %330, implicit $exec
+    dead %371:sreg_32 = S_AND_B32 %171, $exec_lo, implicit-def $scc
+    %372:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit killed $scc
+    undef %374.sub0:vreg_64 = V_CNDMASK_B32_e64 0, %163, 0, 0, %372, implicit $exec
+    %374.sub1:vreg_64 = V_CNDMASK_B32_e64 0, %170, 0, 0, %331, implicit $exec
+    %343:vreg_64 = contract nofpexcept V_ADD_F64_e64 0, %343, 0, %374, 0, 0, implicit $mode, implicit $exec
+    %348:vreg_64 = contract nofpexcept V_ADD_F64_e64 0, %348, 0, %107.sub0_sub1, 0, 0, implicit $mode, implicit $exec
+    %353:vreg_64 = contract nofpexcept V_ADD_F64_e64 0, %353, 0, %80.sub2_sub3, 0, 0, implicit $mode, implicit $exec
+    %181.sub0:sreg_64 = COPY %146.sub0
+    %182:sreg_32_xm0_xexec = nofpexcept V_CMP_EQ_F64_e64 0, %181, 0, %135, 0, implicit $mode, implicit $exec
+    %184:sreg_32 = nofpexcept V_CMP_EQ_F64_e64 0, 0, 0, %123, 0, implicit $mode, implicit $exec
+    %185:sreg_32 = S_XOR_B32 %328, %184, implicit-def dead $scc
+    dead %375:sreg_32 = S_AND_B32 %185, $exec_lo, implicit-def $scc
+    %186:sgpr_32 = S_CSELECT_B32 0, 2146435072, implicit killed $scc
+    %188:vgpr_32 = V_CNDMASK_B32_e64 0, %411.sub1, 0, %186, %182, implicit $exec
+    undef %369.sub1:vreg_64 = V_CNDMASK_B32_e64 0, %188, 0, 0, %332, implicit $exec
+    %192:sreg_32_xm0_xexec = S_OR_B32 %332, %182, implicit-def dead $scc
+    %369.sub0:vreg_64 = V_CNDMASK_B32_e64 0, %411.sub0, 0, 0, %192, implicit $exec
+    %358:vreg_64 = contract nofpexcept V_ADD_F64_e64 0, %358, 0, %369, 0, 0, implicit $mode, implicit $exec
+    %202:vreg_64 = nofpexcept V_FMA_F64_e64 0, %37, 0, %201, 0, %198, 0, 0, implicit $mode, implicit $exec
+    %206:vreg_64 = nofpexcept V_FMA_F64_e64 0, %202, 0, 0, 0, %205, 0, 0, implicit $mode, implicit $exec
+    %210:vreg_64 = nofpexcept V_FMA_F64_e64 0, %206, 0, 0, 0, %209, 0, 0, implicit $mode, implicit $exec
+    %214:vreg_64 = nofpexcept V_FMA_F64_e64 0, %210, 0, 0, 0, %213, 0, 0, implicit $mode, implicit $exec
+    %218:vreg_64 = nofpexcept V_FMA_F64_e64 0, %214, 0, 0, 0, %217, 0, 0, implicit $mode, implicit $exec
+    %222:vreg_64 = nofpexcept V_FMA_F64_e64 0, %218, 0, 0, 0, %221, 0, 0, implicit $mode, implicit $exec
+    %226:vreg_64 = nofpexcept V_FMA_F64_e64 0, %222, 0, 0, 0, %225, 0, 0, implicit $mode, implicit $exec
+    %230:vreg_64 = nofpexcept V_FMA_F64_e64 0, %226, 0, 0, 0, %229, 0, 0, implicit $mode, implicit $exec
+    %234:vreg_64 = nofpexcept V_ADD_F64_e64 0, %230, 0, %233, 0, 0, implicit $mode, implicit $exec
+    %236.sub0:sreg_64 = COPY %233.sub0
+    %237:vreg_64 = nofpexcept V_ADD_F64_e64 0, %234, 0, %236, 0, 0, implicit $mode, implicit $exec
+    %238:vreg_64 = nofpexcept V_ADD_F64_e64 0, %117, 0, %237, 0, 0, implicit $mode, implicit $exec
+    %239:vreg_64 = nofpexcept V_MUL_F64_e64 0, %77, 0, %238, 0, 0, implicit $mode, implicit $exec
+    %243:vreg_64 = nofpexcept V_MUL_F64_e64 0, %239, 0, %242, 0, 0, implicit $mode, implicit $exec
+    %246.sub0:sreg_64 = COPY %140.sub0
+    %247:vreg_64 = nofpexcept V_FMA_F64_e64 0, %243, 0, %246, 0, %106, 0, 0, implicit $mode, implicit $exec
+    %254:vreg_64 = nofpexcept V_FMA_F64_e64 0, %247, 0, %253, 0, %250, 0, 0, implicit $mode, implicit $exec
+    %258:vreg_64 = nofpexcept V_FMA_F64_e64 0, %254, 0, 0, 0, %257, 0, 0, implicit $mode, implicit $exec
+    %262:vreg_64 = nofpexcept V_FMA_F64_e64 0, %258, 0, 0, 0, %261, 0, 0, implicit $mode, implicit $exec
+    %266:vreg_64 = nofpexcept V_FMA_F64_e64 0, %262, 0, 0, 0, %265, 0, 0, implicit $mode, implicit $exec
+    %270:vreg_64 = nofpexcept V_FMA_F64_e64 0, %266, 0, 0, 0, %269, 0, 0, implicit $mode, implicit $exec
+    %274:vreg_64 = nofpexcept V_FMA_F64_e64 0, %270, 0, 0, 0, %273, 0, 0, implicit $mode, implicit $exec
+    %278:vreg_64 = nofpexcept V_FMA_F64_e64 0, %274, 0, 0, 0, %277, 0, 0, implicit $mode, implicit $exec
+    %282:vreg_64 = nofpexcept V_FMA_F64_e64 0, %278, 0, 0, 0, %281, 0, 0, implicit $mode, implicit $exec
+    %286:vreg_64 = nofpexcept V_FMA_F64_e64 0, %282, 0, 0, 0, %285, 0, 0, implicit $mode, implicit $exec
+    %28:vreg_64 = contract nofpexcept V_ADD_F64_e64 0, %28, 0, %286, 0, 0, implicit $mode, implicit $exec
+    %287:vreg_64 = nofpexcept V_FMA_F64_e64 0, %38, 0, 0, 0, %205, 0, 0, implicit $mode, implicit $exec
+    %288:vreg_64 = nofpexcept V_FMA_F64_e64 0, %287, 0, 0, 0, %209, 0, 0, implicit $mode, implicit $exec
+    %289:vreg_64 = nofpexcept V_FMA_F64_e64 0, %288, 0, 0, 0, %213, 0, 0, implicit $mode, implicit $exec
+    %290:vreg_64 = nofpexcept V_FMA_F64_e64 0, %289, 0, 0, 0, %217, 0, 0, implicit $mode, implicit $exec
+    %291:vreg_64 = nofpexcept V_FMA_F64_e64 0, %290, 0, 0, 0, %221, 0, 0, implicit $mode, implicit $exec
+    %292:vreg_64 = nofpexcept V_FMA_F64_e64 0, %291, 0, 0, 0, %225, 0, 0, implicit $mode, implicit $exec
+    %293:vreg_64 = nofpexcept V_FMA_F64_e64 0, %292, 0, 0, 0, %229, 0, 0, implicit $mode, implicit $exec
+    %294:vreg_64 = nofpexcept V_MUL_F64_e64 0, %293, 0, %242, 0, 0, implicit $mode, implicit $exec
+    %296.sub0:sreg_64 = COPY %253.sub0
+    %297:vreg_64 = nofpexcept V_FMA_F64_e64 0, %294, 0, %296, 0, %250, 0, 0, implicit $mode, implicit $exec
+    %298:vreg_64 = nofpexcept V_FMA_F64_e64 0, %297, 0, 0, 0, %257, 0, 0, implicit $mode, implicit $exec
+    %299:vreg_64 = nofpexcept V_FMA_F64_e64 0, %298, 0, 0, 0, %261, 0, 0, implicit $mode, implicit $exec
+    %300:vreg_64 = nofpexcept V_FMA_F64_e64 0, %299, 0, 0, 0, %265, 0, 0, implicit $mode, implicit $exec
+    %301:vreg_64 = nofpexcept V_FMA_F64_e64 0, %300, 0, 0, 0, %269, 0, 0, implicit $mode, implicit $exec
+    %302:vreg_64 = nofpexcept V_FMA_F64_e64 0, %301, 0, 0, 0, %273, 0, 0, implicit $mode, implicit $exec
+    %303:vreg_64 = nofpexcept V_FMA_F64_e64 0, %302, 0, 0, 0, %277, 0, 0, implicit $mode, implicit $exec
+    %304:vreg_64 = nofpexcept V_FMA_F64_e64 0, %303, 0, 0, 0, %281, 0, 0, implicit $mode, implicit $exec
+    %305:vreg_64 = nofpexcept V_FMA_F64_e64 0, %304, 0, 0, 0, %285, 0, 0, implicit $mode, implicit $exec
+    %27:vreg_64 = contract nofpexcept V_ADD_F64_e64 0, %27, 0, %305, 0, 0, implicit $mode, implicit $exec
+    %393:sreg_32 = V_CMP_LE_U32_e64 %74.sub0, %33, implicit $exec
+    %409:sreg_32 = S_MOV_B32 0
+    S_BRANCH %bb.9
+
+  bb.14:
+    S_CBRANCH_SCC1 %bb.18, implicit undef $scc
+    S_BRANCH %bb.15
+
+  bb.15:
+    %377:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %317, implicit $exec
+    $vcc_lo = S_AND_B32 $exec_lo, %377, implicit-def dead $scc
+    S_CBRANCH_VCCNZ %bb.18, implicit killed $vcc
+    S_BRANCH %bb.16
+
+  bb.16:
+    %378:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %320, implicit $exec
+    $vcc_lo = S_AND_B32 $exec_lo, %378, implicit-def dead $scc
+    S_CBRANCH_VCCNZ %bb.16, implicit killed $vcc
+    S_BRANCH %bb.18
+
+  bb.18:
+    %379:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %323, implicit $exec
+    $vcc_lo = S_AND_B32 $exec_lo, %379, implicit-def dead $scc
+    S_CBRANCH_VCCNZ %bb.14, implicit killed $vcc
+    S_BRANCH %bb.20
+
+  bb.20:
+    $exec_lo = S_OR_B32 $exec_lo, %25, implicit-def $scc
+    S_ENDPGM 0
+
+  bb.21:
+    $exec_lo = S_OR_B32 $exec_lo, %26, implicit-def $scc
+    S_BRANCH %bb.2
+
+...