diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def --- a/clang/include/clang/Basic/BuiltinsPPC.def +++ b/clang/include/clang/Basic/BuiltinsPPC.def @@ -165,6 +165,8 @@ BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n") +BUILTIN(__builtin_ppc_kill_canary, "v", "") + // This is just a placeholder, the types and attributes are wrong. BUILTIN(__builtin_altivec_vaddcuw, "V4UiV4UiV4Ui", "") diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -122,6 +122,7 @@ Builder.defineMacro("__fetch_and_orlp", "__builtin_ppc_fetch_and_orlp"); Builder.defineMacro("__fetch_and_swap", "__builtin_ppc_fetch_and_swap"); Builder.defineMacro("__fetch_and_swaplp", "__builtin_ppc_fetch_and_swaplp"); + Builder.defineMacro("__kill_canary", "__builtin_ppc_kill_canary"); Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx"); Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx"); Builder.defineMacro("__lharx", "__builtin_ppc_lharx"); diff --git a/clang/test/CodeGen/PowerPC/builtins-ppc-stackprotect.c b/clang/test/CodeGen/PowerPC/builtins-ppc-stackprotect.c new file mode 100644 --- /dev/null +++ b/clang/test/CodeGen/PowerPC/builtins-ppc-stackprotect.c @@ -0,0 +1,23 @@ +// REQUIRES: powerpc-registered-target +// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-linux-gnu \ +// RUN: -emit-llvm %s -o - -target-cpu pwr7 | \ +// RUN: FileCheck %s +// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-linux-gnu \ +// RUN: -emit-llvm %s -o - -target-cpu pwr8 | \ +// RUN: FileCheck %s +// RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \ +// RUN: -emit-llvm %s -o - -target-cpu pwr7 | \ +// RUN: FileCheck %s +// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \ +// RUN: -emit-llvm %s -o - -target-cpu pwr7 | \ +// RUN: FileCheck %s + +void test_builtin_ppc_kill_canary() { + // CHECK: call void @llvm.ppc.kill.canary() + __builtin_ppc_kill_canary(); +} + +void test_kill_canary() { + // CHECK: call void @llvm.ppc.kill.canary() + __kill_canary(); +} diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td --- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -217,6 +217,11 @@ : Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty, llvm_float_ty, llvm_vararg_ty], [IntrNoMem]>; + def int_ppc_kill_canary + : ClangBuiltin<"__builtin_ppc_kill_canary">, + Intrinsic<[], + [], + [IntrWriteMem, IntrHasSideEffects]>; } let TargetPrefix = "ppc" in { // All PPC intrinsics start with "llvm.ppc.". diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -106,26 +106,38 @@ #define DEBUG_TYPE "ppc-lowering" -static cl::opt DisablePPCPreinc("disable-ppc-preinc", -cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden); +static cl::opt DisablePPCPreinc( + "disable-ppc-preinc", + cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden); -static cl::opt DisableILPPref("disable-ppc-ilp-pref", -cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden); +static cl::opt DisableILPPref( + "disable-ppc-ilp-pref", + cl::desc("disable setting the node scheduling preference to ILP on PPC"), + cl::Hidden); -static cl::opt DisablePPCUnaligned("disable-ppc-unaligned", -cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden); +static cl::opt DisablePPCUnaligned( + "disable-ppc-unaligned", + cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden); -static cl::opt DisableSCO("disable-ppc-sco", -cl::desc("disable sibling call optimization on ppc"), cl::Hidden); +static cl::opt + DisableSCO("disable-ppc-sco", + cl::desc("disable sibling call optimization on ppc"), + cl::Hidden); -static cl::opt DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32", -cl::desc("don't always align innermost loop to 32 bytes on ppc"), cl::Hidden); +static cl::opt DisableInnermostLoopAlign32( + "disable-ppc-innermost-loop-align32", + cl::desc("don't always align innermost loop to 32 bytes on ppc"), + cl::Hidden); -static cl::opt Enable512BitVector("enable-ppc-512bit-vector", -cl::desc("enable the 512 bit vector type"), cl::Hidden, cl::init(true)); +static cl::opt + Enable512BitVector("enable-ppc-512bit-vector", + cl::desc("enable the 512 bit vector type"), cl::Hidden, + cl::init(true)); -static cl::opt Enable256BitVector("enable-ppc-256bit-vector", -cl::desc("enable the 256 bit vector type"), cl::Hidden, cl::init(true)); +static cl::opt + Enable256BitVector("enable-ppc-256bit-vector", + cl::desc("enable the 256 bit vector type"), cl::Hidden, + cl::init(true)); cl::opt DisablePairedVecLd("disable-paired-vec-ld", @@ -147,8 +159,10 @@ cl::desc("disable automatically generated 32byte paired vector loads"), cl::init(true), cl::Hidden); -static cl::opt UseAbsoluteJumpTables("ppc-use-absolute-jumptables", -cl::desc("use absolute jump tables on ppc"), cl::Hidden); +static cl::opt + UseAbsoluteJumpTables("ppc-use-absolute-jumptables", + cl::desc("use absolute jump tables on ppc"), + cl::Hidden); // Notice that this is a temp option for ESSL and will not be maintained for // long time. @@ -300,7 +314,7 @@ } // PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry. - const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 }; + const MVT ScalarIntVTs[] = {MVT::i32, MVT::i64}; for (MVT VT : ScalarIntVTs) { setOperationAction(ISD::ADDC, VT, Legal); setOperationAction(ISD::ADDE, VT, Legal); @@ -320,8 +334,8 @@ isPPC64 ? MVT::i64 : MVT::i32); setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote); - AddPromotedToType (ISD::SINT_TO_FP, MVT::i1, - isPPC64 ? MVT::i64 : MVT::i32); + AddPromotedToType(ISD::SINT_TO_FP, MVT::i1, + isPPC64 ? MVT::i64 : MVT::i32); setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); AddPromotedToType(ISD::UINT_TO_FP, MVT::i1, isPPC64 ? MVT::i64 : MVT::i32); @@ -372,9 +386,9 @@ // We do not currently implement these libm ops for PowerPC. setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand); - setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); + setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand); setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand); - setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); + setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand); setOperationAction(ISD::FREM, MVT::ppcf128, Expand); @@ -437,52 +451,52 @@ if (Subtarget.hasFPRND()) { setOperationAction(ISD::STRICT_FFLOOR, MVT::f32, Legal); - setOperationAction(ISD::STRICT_FCEIL, MVT::f32, Legal); + setOperationAction(ISD::STRICT_FCEIL, MVT::f32, Legal); setOperationAction(ISD::STRICT_FTRUNC, MVT::f32, Legal); setOperationAction(ISD::STRICT_FROUND, MVT::f32, Legal); setOperationAction(ISD::STRICT_FFLOOR, MVT::f64, Legal); - setOperationAction(ISD::STRICT_FCEIL, MVT::f64, Legal); + setOperationAction(ISD::STRICT_FCEIL, MVT::f64, Legal); setOperationAction(ISD::STRICT_FTRUNC, MVT::f64, Legal); setOperationAction(ISD::STRICT_FROUND, MVT::f64, Legal); } // We don't support sin/cos/sqrt/fmod/pow - setOperationAction(ISD::FSIN , MVT::f64, Expand); - setOperationAction(ISD::FCOS , MVT::f64, Expand); + setOperationAction(ISD::FSIN, MVT::f64, Expand); + setOperationAction(ISD::FCOS, MVT::f64, Expand); setOperationAction(ISD::FSINCOS, MVT::f64, Expand); - setOperationAction(ISD::FREM , MVT::f64, Expand); - setOperationAction(ISD::FPOW , MVT::f64, Expand); - setOperationAction(ISD::FSIN , MVT::f32, Expand); - setOperationAction(ISD::FCOS , MVT::f32, Expand); + setOperationAction(ISD::FREM, MVT::f64, Expand); + setOperationAction(ISD::FPOW, MVT::f64, Expand); + setOperationAction(ISD::FSIN, MVT::f32, Expand); + setOperationAction(ISD::FCOS, MVT::f32, Expand); setOperationAction(ISD::FSINCOS, MVT::f32, Expand); - setOperationAction(ISD::FREM , MVT::f32, Expand); - setOperationAction(ISD::FPOW , MVT::f32, Expand); + setOperationAction(ISD::FREM, MVT::f32, Expand); + setOperationAction(ISD::FPOW, MVT::f32, Expand); // MASS transformation for LLVM intrinsics with replicating fast-math flag // to be consistent to PPCGenScalarMASSEntries pass if (TM.getOptLevel() == CodeGenOpt::Aggressive && TM.Options.PPCGenScalarMASSEntries) { - setOperationAction(ISD::FSIN , MVT::f64, Custom); - setOperationAction(ISD::FCOS , MVT::f64, Custom); - setOperationAction(ISD::FPOW , MVT::f64, Custom); + setOperationAction(ISD::FSIN, MVT::f64, Custom); + setOperationAction(ISD::FCOS, MVT::f64, Custom); + setOperationAction(ISD::FPOW, MVT::f64, Custom); setOperationAction(ISD::FLOG, MVT::f64, Custom); setOperationAction(ISD::FLOG10, MVT::f64, Custom); setOperationAction(ISD::FEXP, MVT::f64, Custom); - setOperationAction(ISD::FSIN , MVT::f32, Custom); - setOperationAction(ISD::FCOS , MVT::f32, Custom); - setOperationAction(ISD::FPOW , MVT::f32, Custom); + setOperationAction(ISD::FSIN, MVT::f32, Custom); + setOperationAction(ISD::FCOS, MVT::f32, Custom); + setOperationAction(ISD::FPOW, MVT::f32, Custom); setOperationAction(ISD::FLOG, MVT::f32, Custom); setOperationAction(ISD::FLOG10, MVT::f32, Custom); setOperationAction(ISD::FEXP, MVT::f32, Custom); } if (Subtarget.hasSPE()) { - setOperationAction(ISD::FMA , MVT::f64, Expand); - setOperationAction(ISD::FMA , MVT::f32, Expand); + setOperationAction(ISD::FMA, MVT::f64, Expand); + setOperationAction(ISD::FMA, MVT::f32, Expand); } else { - setOperationAction(ISD::FMA , MVT::f64, Legal); - setOperationAction(ISD::FMA , MVT::f32, Legal); + setOperationAction(ISD::FMA, MVT::f64, Legal); + setOperationAction(ISD::FMA, MVT::f32, Legal); } if (Subtarget.hasSPE()) @@ -491,9 +505,8 @@ setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); // If we're enabling GP optimizations, use hardware square root - if (!Subtarget.hasFSQRT() && - !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() && - Subtarget.hasFRE())) + if (!Subtarget.hasFSQRT() && !(TM.Options.UnsafeFPMath && + Subtarget.hasFRSQRTE() && Subtarget.hasFRE())) setOperationAction(ISD::FSQRT, MVT::f64, Expand); if (!Subtarget.hasFSQRT() && @@ -511,12 +524,12 @@ if (Subtarget.hasFPRND()) { setOperationAction(ISD::FFLOOR, MVT::f64, Legal); - setOperationAction(ISD::FCEIL, MVT::f64, Legal); + setOperationAction(ISD::FCEIL, MVT::f64, Legal); setOperationAction(ISD::FTRUNC, MVT::f64, Legal); setOperationAction(ISD::FROUND, MVT::f64, Legal); setOperationAction(ISD::FFLOOR, MVT::f32, Legal); - setOperationAction(ISD::FCEIL, MVT::f32, Legal); + setOperationAction(ISD::FCEIL, MVT::f32, Legal); setOperationAction(ISD::FTRUNC, MVT::f32, Legal); setOperationAction(ISD::FROUND, MVT::f32, Legal); } @@ -535,24 +548,24 @@ // CTPOP or CTTZ were introduced in P8/P9 respectively if (Subtarget.isISA3_0()) { - setOperationAction(ISD::CTTZ , MVT::i32 , Legal); - setOperationAction(ISD::CTTZ , MVT::i64 , Legal); + setOperationAction(ISD::CTTZ, MVT::i32, Legal); + setOperationAction(ISD::CTTZ, MVT::i64, Legal); } else { - setOperationAction(ISD::CTTZ , MVT::i32 , Expand); - setOperationAction(ISD::CTTZ , MVT::i64 , Expand); + setOperationAction(ISD::CTTZ, MVT::i32, Expand); + setOperationAction(ISD::CTTZ, MVT::i64, Expand); } if (Subtarget.hasPOPCNTD() == PPCSubtarget::POPCNTD_Fast) { - setOperationAction(ISD::CTPOP, MVT::i32 , Legal); - setOperationAction(ISD::CTPOP, MVT::i64 , Legal); + setOperationAction(ISD::CTPOP, MVT::i32, Legal); + setOperationAction(ISD::CTPOP, MVT::i64, Legal); } else { - setOperationAction(ISD::CTPOP, MVT::i32 , Expand); - setOperationAction(ISD::CTPOP, MVT::i64 , Expand); + setOperationAction(ISD::CTPOP, MVT::i32, Expand); + setOperationAction(ISD::CTPOP, MVT::i64, Expand); } // PowerPC does not have ROTR - setOperationAction(ISD::ROTR, MVT::i32 , Expand); - setOperationAction(ISD::ROTR, MVT::i64 , Expand); + setOperationAction(ISD::ROTR, MVT::i32, Expand); + setOperationAction(ISD::ROTR, MVT::i64, Expand); if (!Subtarget.useCRBits()) { // PowerPC does not have Select @@ -584,7 +597,7 @@ if (!Subtarget.useCRBits()) setOperationAction(ISD::BRCOND, MVT::Other, Expand); - setOperationAction(ISD::BR_JT, MVT::Other, Expand); + setOperationAction(ISD::BR_JT, MVT::Other, Expand); if (Subtarget.hasSPE()) { // SPE has built-in conversions @@ -648,14 +661,14 @@ // appropriate instructions to materialize the address. setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); - setOperationAction(ISD::BlockAddress, MVT::i32, Custom); - setOperationAction(ISD::ConstantPool, MVT::i32, Custom); - setOperationAction(ISD::JumpTable, MVT::i32, Custom); + setOperationAction(ISD::BlockAddress, MVT::i32, Custom); + setOperationAction(ISD::ConstantPool, MVT::i32, Custom); + setOperationAction(ISD::JumpTable, MVT::i32, Custom); setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); - setOperationAction(ISD::BlockAddress, MVT::i64, Custom); - setOperationAction(ISD::ConstantPool, MVT::i64, Custom); - setOperationAction(ISD::JumpTable, MVT::i64, Custom); + setOperationAction(ISD::BlockAddress, MVT::i64, Custom); + setOperationAction(ISD::ConstantPool, MVT::i64, Custom); + setOperationAction(ISD::JumpTable, MVT::i64, Custom); // TRAP is legal. setOperationAction(ISD::TRAP, MVT::Other, Legal); @@ -665,7 +678,7 @@ setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); // VASTART needs to be custom lowered to use the VarArgsFrameIndex - setOperationAction(ISD::VASTART , MVT::Other, Custom); + setOperationAction(ISD::VASTART, MVT::Other, Custom); if (Subtarget.is64BitELFABI()) { // VAARG always uses double-word chunks, so promote anything smaller. @@ -687,16 +700,16 @@ // VACOPY is custom lowered with the 32-bit SVR4 ABI. if (Subtarget.is32BitELFABI()) - setOperationAction(ISD::VACOPY , MVT::Other, Custom); + setOperationAction(ISD::VACOPY, MVT::Other, Custom); else - setOperationAction(ISD::VACOPY , MVT::Other, Expand); + setOperationAction(ISD::VACOPY, MVT::Other, Expand); // Use the default implementation. - setOperationAction(ISD::VAEND , MVT::Other, Expand); - setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); - setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); + setOperationAction(ISD::VAEND, MVT::Other, Expand); + setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); + setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i32, Custom); setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, MVT::i64, Custom); setOperationAction(ISD::EH_DWARF_CFA, MVT::i32, Custom); @@ -836,7 +849,7 @@ } if (Subtarget.hasAltivec()) { - for (MVT VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32 }) { + for (MVT VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32}) { setOperationAction(ISD::SADDSAT, VT, Legal); setOperationAction(ISD::SSUBSAT, VT, Legal); setOperationAction(ISD::UADDSAT, VT, Legal); @@ -860,8 +873,7 @@ setOperationAction(ISD::SMIN, VT, Legal); setOperationAction(ISD::UMAX, VT, Legal); setOperationAction(ISD::UMIN, VT, Legal); - } - else { + } else { setOperationAction(ISD::SMAX, VT, Expand); setOperationAction(ISD::SMIN, VT, Expand); setOperationAction(ISD::UMAX, VT, Expand); @@ -877,8 +889,7 @@ if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) { setOperationAction(ISD::CTPOP, VT, Legal); setOperationAction(ISD::CTLZ, VT, Legal); - } - else { + } else { setOperationAction(ISD::CTPOP, VT, Expand); setOperationAction(ISD::CTLZ, VT, Expand); } @@ -891,27 +902,27 @@ // We promote all shuffles to v16i8. setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); - AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); + AddPromotedToType(ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); // We promote all non-typed operations to v4i32. - setOperationAction(ISD::AND , VT, Promote); - AddPromotedToType (ISD::AND , VT, MVT::v4i32); - setOperationAction(ISD::OR , VT, Promote); - AddPromotedToType (ISD::OR , VT, MVT::v4i32); - setOperationAction(ISD::XOR , VT, Promote); - AddPromotedToType (ISD::XOR , VT, MVT::v4i32); - setOperationAction(ISD::LOAD , VT, Promote); - AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); + setOperationAction(ISD::AND, VT, Promote); + AddPromotedToType(ISD::AND, VT, MVT::v4i32); + setOperationAction(ISD::OR, VT, Promote); + AddPromotedToType(ISD::OR, VT, MVT::v4i32); + setOperationAction(ISD::XOR, VT, Promote); + AddPromotedToType(ISD::XOR, VT, MVT::v4i32); + setOperationAction(ISD::LOAD, VT, Promote); + AddPromotedToType(ISD::LOAD, VT, MVT::v4i32); setOperationAction(ISD::SELECT, VT, Promote); - AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); + AddPromotedToType(ISD::SELECT, VT, MVT::v4i32); setOperationAction(ISD::VSELECT, VT, Legal); setOperationAction(ISD::SELECT_CC, VT, Promote); - AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32); + AddPromotedToType(ISD::SELECT_CC, VT, MVT::v4i32); setOperationAction(ISD::STORE, VT, Promote); - AddPromotedToType (ISD::STORE, VT, MVT::v4i32); + AddPromotedToType(ISD::STORE, VT, MVT::v4i32); // No other operations are legal. - setOperationAction(ISD::MUL , VT, Expand); + setOperationAction(ISD::MUL, VT, Expand); setOperationAction(ISD::SDIV, VT, Expand); setOperationAction(ISD::SREM, VT, Expand); setOperationAction(ISD::UDIV, VT, Expand); @@ -929,9 +940,9 @@ setOperationAction(ISD::FCOS, VT, Expand); setOperationAction(ISD::FABS, VT, Expand); setOperationAction(ISD::FFLOOR, VT, Expand); - setOperationAction(ISD::FCEIL, VT, Expand); + setOperationAction(ISD::FCEIL, VT, Expand); setOperationAction(ISD::FTRUNC, VT, Expand); - setOperationAction(ISD::FRINT, VT, Expand); + setOperationAction(ISD::FRINT, VT, Expand); setOperationAction(ISD::FNEARBYINT, VT, Expand); setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand); setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand); @@ -976,13 +987,13 @@ setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom); setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom); - setOperationAction(ISD::AND , MVT::v4i32, Legal); - setOperationAction(ISD::OR , MVT::v4i32, Legal); - setOperationAction(ISD::XOR , MVT::v4i32, Legal); - setOperationAction(ISD::LOAD , MVT::v4i32, Legal); + setOperationAction(ISD::AND, MVT::v4i32, Legal); + setOperationAction(ISD::OR, MVT::v4i32, Legal); + setOperationAction(ISD::XOR, MVT::v4i32, Legal); + setOperationAction(ISD::LOAD, MVT::v4i32, Legal); setOperationAction(ISD::SELECT, MVT::v4i32, Subtarget.useCRBits() ? Legal : Expand); - setOperationAction(ISD::STORE , MVT::v4i32, Legal); + setOperationAction(ISD::STORE, MVT::v4i32, Legal); setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::v4i32, Legal); setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::v4i32, Legal); setOperationAction(ISD::STRICT_SINT_TO_FP, MVT::v4i32, Legal); @@ -1063,7 +1074,7 @@ // Altivec does not contain unordered floating-point compare instructions setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand); setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand); - setCondCodeAction(ISD::SETO, MVT::v4f32, Expand); + setCondCodeAction(ISD::SETO, MVT::v4f32, Expand); setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand); if (Subtarget.hasVSX()) { @@ -1116,7 +1127,7 @@ // Share the Altivec comparison restrictions. setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand); setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand); - setCondCodeAction(ISD::SETO, MVT::v2f64, Expand); + setCondCodeAction(ISD::SETO, MVT::v2f64, Expand); setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand); setOperationAction(ISD::LOAD, MVT::v2f64, Legal); @@ -1147,8 +1158,7 @@ setOperationAction(ISD::SRA, MVT::v1i128, Expand); setOperationAction(ISD::SETCC, MVT::v2i64, Legal); - } - else { + } else { setOperationAction(ISD::SHL, MVT::v2i64, Expand); setOperationAction(ISD::SRA, MVT::v2i64, Expand); setOperationAction(ISD::SRL, MVT::v2i64, Expand); @@ -1166,9 +1176,9 @@ setOperationAction(ISD::SETCC, MVT::v1i128, Expand); setOperationAction(ISD::LOAD, MVT::v2i64, Promote); - AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64); + AddPromotedToType(ISD::LOAD, MVT::v2i64, MVT::v2f64); setOperationAction(ISD::STORE, MVT::v2i64, Promote); - AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64); + AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v2f64); setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); @@ -1224,7 +1234,7 @@ setOperationAction(ISD::STRICT_FMINNUM, MVT::v4f32, Legal); setOperationAction(ISD::STRICT_FRINT, MVT::v4f32, Legal); setOperationAction(ISD::STRICT_FFLOOR, MVT::v4f32, Legal); - setOperationAction(ISD::STRICT_FCEIL, MVT::v4f32, Legal); + setOperationAction(ISD::STRICT_FCEIL, MVT::v4f32, Legal); setOperationAction(ISD::STRICT_FTRUNC, MVT::v4f32, Legal); setOperationAction(ISD::STRICT_FROUND, MVT::v4f32, Legal); @@ -1238,7 +1248,7 @@ setOperationAction(ISD::STRICT_FMINNUM, MVT::v2f64, Legal); setOperationAction(ISD::STRICT_FRINT, MVT::v2f64, Legal); setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f64, Legal); - setOperationAction(ISD::STRICT_FCEIL, MVT::v2f64, Legal); + setOperationAction(ISD::STRICT_FCEIL, MVT::v2f64, Legal); setOperationAction(ISD::STRICT_FTRUNC, MVT::v2f64, Legal); setOperationAction(ISD::STRICT_FROUND, MVT::v2f64, Legal); @@ -1378,10 +1388,10 @@ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); } - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Legal); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i32, Legal); - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Legal); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Legal); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal); @@ -1413,7 +1423,7 @@ setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom); if (!isPPC64) { - setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); + setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand); setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand); } @@ -1506,7 +1516,8 @@ setMinFunctionAlignment(Align(4)); switch (Subtarget.getCPUDirective()) { - default: break; + default: + break; case PPC::DIR_970: case PPC::DIR_A2: case PPC::DIR_E500: @@ -1688,13 +1699,9 @@ return Subtarget.useSoftFloat(); } -bool PPCTargetLowering::hasSPE() const { - return Subtarget.hasSPE(); -} +bool PPCTargetLowering::hasSPE() const { return Subtarget.hasSPE(); } -bool PPCTargetLowering::isISA3_1() const { - return Subtarget.isISA3_1(); -} +bool PPCTargetLowering::isISA3_1() const { return Subtarget.isISA3_1(); } bool PPCTargetLowering::preferIncOfAddToSubOfNot(EVT VT) const { return VT.isScalarInteger(); @@ -1702,160 +1709,278 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { switch ((PPCISD::NodeType)Opcode) { - case PPCISD::FIRST_NUMBER: break; - case PPCISD::FSEL: return "PPCISD::FSEL"; - case PPCISD::XSMAXC: return "PPCISD::XSMAXC"; - case PPCISD::XSMINC: return "PPCISD::XSMINC"; - case PPCISD::FCFID: return "PPCISD::FCFID"; - case PPCISD::FCFIDU: return "PPCISD::FCFIDU"; - case PPCISD::FCFIDS: return "PPCISD::FCFIDS"; - case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS"; - case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ"; - case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ"; - case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ"; - case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ"; + case PPCISD::FIRST_NUMBER: + break; + case PPCISD::FSEL: + return "PPCISD::FSEL"; + case PPCISD::XSMAXC: + return "PPCISD::XSMAXC"; + case PPCISD::XSMINC: + return "PPCISD::XSMINC"; + case PPCISD::FCFID: + return "PPCISD::FCFID"; + case PPCISD::FCFIDU: + return "PPCISD::FCFIDU"; + case PPCISD::FCFIDS: + return "PPCISD::FCFIDS"; + case PPCISD::FCFIDUS: + return "PPCISD::FCFIDUS"; + case PPCISD::FCTIDZ: + return "PPCISD::FCTIDZ"; + case PPCISD::FCTIWZ: + return "PPCISD::FCTIWZ"; + case PPCISD::FCTIDUZ: + return "PPCISD::FCTIDUZ"; + case PPCISD::FCTIWUZ: + return "PPCISD::FCTIWUZ"; case PPCISD::FP_TO_UINT_IN_VSR: - return "PPCISD::FP_TO_UINT_IN_VSR,"; + return "PPCISD::FP_TO_UINT_IN_VSR,"; case PPCISD::FP_TO_SINT_IN_VSR: - return "PPCISD::FP_TO_SINT_IN_VSR"; - case PPCISD::FRE: return "PPCISD::FRE"; - case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE"; + return "PPCISD::FP_TO_SINT_IN_VSR"; + case PPCISD::FRE: + return "PPCISD::FRE"; + case PPCISD::FRSQRTE: + return "PPCISD::FRSQRTE"; case PPCISD::FTSQRT: return "PPCISD::FTSQRT"; case PPCISD::FSQRT: return "PPCISD::FSQRT"; - case PPCISD::STFIWX: return "PPCISD::STFIWX"; - case PPCISD::VPERM: return "PPCISD::VPERM"; - case PPCISD::VSUM_TO_SCALAR: return "PPCISD::VSUM_TO_SCALAR"; - case PPCISD::VSUMS_TO_VEC: return "PPCISD::VSUMS_TO_VEC"; - case PPCISD::VSUMU_TO_VEC: return "PPCISD::VSUMU_TO_VEC"; - case PPCISD::XXSPLT: return "PPCISD::XXSPLT"; + case PPCISD::STFIWX: + return "PPCISD::STFIWX"; + case PPCISD::VPERM: + return "PPCISD::VPERM"; + case PPCISD::VSUM_TO_SCALAR: + return "PPCISD::VSUM_TO_SCALAR"; + case PPCISD::VSUMS_TO_VEC: + return "PPCISD::VSUMS_TO_VEC"; + case PPCISD::VSUMU_TO_VEC: + return "PPCISD::VSUMU_TO_VEC"; + case PPCISD::XXSPLT: + return "PPCISD::XXSPLT"; case PPCISD::XXSPLTI_SP_TO_DP: return "PPCISD::XXSPLTI_SP_TO_DP"; case PPCISD::XXSPLTI32DX: return "PPCISD::XXSPLTI32DX"; - case PPCISD::VECINSERT: return "PPCISD::VECINSERT"; - case PPCISD::XXPERMDI: return "PPCISD::XXPERMDI"; - case PPCISD::VECSHL: return "PPCISD::VECSHL"; - case PPCISD::CMPB: return "PPCISD::CMPB"; - case PPCISD::Hi: return "PPCISD::Hi"; - case PPCISD::Lo: return "PPCISD::Lo"; - case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY"; - case PPCISD::ATOMIC_CMP_SWAP_8: return "PPCISD::ATOMIC_CMP_SWAP_8"; - case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16"; - case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC"; - case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET"; - case PPCISD::PROBED_ALLOCA: return "PPCISD::PROBED_ALLOCA"; - case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg"; - case PPCISD::SRL: return "PPCISD::SRL"; - case PPCISD::SRA: return "PPCISD::SRA"; - case PPCISD::SHL: return "PPCISD::SHL"; - case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE"; - case PPCISD::CALL: return "PPCISD::CALL"; - case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP"; - case PPCISD::CALL_NOTOC: return "PPCISD::CALL_NOTOC"; + case PPCISD::VECINSERT: + return "PPCISD::VECINSERT"; + case PPCISD::XXPERMDI: + return "PPCISD::XXPERMDI"; + case PPCISD::VECSHL: + return "PPCISD::VECSHL"; + case PPCISD::CMPB: + return "PPCISD::CMPB"; + case PPCISD::Hi: + return "PPCISD::Hi"; + case PPCISD::Lo: + return "PPCISD::Lo"; + case PPCISD::TOC_ENTRY: + return "PPCISD::TOC_ENTRY"; + case PPCISD::ATOMIC_CMP_SWAP_8: + return "PPCISD::ATOMIC_CMP_SWAP_8"; + case PPCISD::ATOMIC_CMP_SWAP_16: + return "PPCISD::ATOMIC_CMP_SWAP_16"; + case PPCISD::DYNALLOC: + return "PPCISD::DYNALLOC"; + case PPCISD::DYNAREAOFFSET: + return "PPCISD::DYNAREAOFFSET"; + case PPCISD::PROBED_ALLOCA: + return "PPCISD::PROBED_ALLOCA"; + case PPCISD::GlobalBaseReg: + return "PPCISD::GlobalBaseReg"; + case PPCISD::SRL: + return "PPCISD::SRL"; + case PPCISD::SRA: + return "PPCISD::SRA"; + case PPCISD::SHL: + return "PPCISD::SHL"; + case PPCISD::SRA_ADDZE: + return "PPCISD::SRA_ADDZE"; + case PPCISD::CALL: + return "PPCISD::CALL"; + case PPCISD::CALL_NOP: + return "PPCISD::CALL_NOP"; + case PPCISD::CALL_NOTOC: + return "PPCISD::CALL_NOTOC"; case PPCISD::CALL_RM: return "PPCISD::CALL_RM"; case PPCISD::CALL_NOP_RM: return "PPCISD::CALL_NOP_RM"; case PPCISD::CALL_NOTOC_RM: return "PPCISD::CALL_NOTOC_RM"; - case PPCISD::MTCTR: return "PPCISD::MTCTR"; - case PPCISD::BCTRL: return "PPCISD::BCTRL"; - case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC"; + case PPCISD::MTCTR: + return "PPCISD::MTCTR"; + case PPCISD::BCTRL: + return "PPCISD::BCTRL"; + case PPCISD::BCTRL_LOAD_TOC: + return "PPCISD::BCTRL_LOAD_TOC"; case PPCISD::BCTRL_RM: return "PPCISD::BCTRL_RM"; case PPCISD::BCTRL_LOAD_TOC_RM: return "PPCISD::BCTRL_LOAD_TOC_RM"; - case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG"; - case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE"; - case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP"; - case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP"; - case PPCISD::MFOCRF: return "PPCISD::MFOCRF"; - case PPCISD::MFVSR: return "PPCISD::MFVSR"; - case PPCISD::MTVSRA: return "PPCISD::MTVSRA"; - case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ"; - case PPCISD::SINT_VEC_TO_FP: return "PPCISD::SINT_VEC_TO_FP"; - case PPCISD::UINT_VEC_TO_FP: return "PPCISD::UINT_VEC_TO_FP"; + case PPCISD::RET_FLAG: + return "PPCISD::RET_FLAG"; + case PPCISD::READ_TIME_BASE: + return "PPCISD::READ_TIME_BASE"; + case PPCISD::EH_SJLJ_SETJMP: + return "PPCISD::EH_SJLJ_SETJMP"; + case PPCISD::EH_SJLJ_LONGJMP: + return "PPCISD::EH_SJLJ_LONGJMP"; + case PPCISD::MFOCRF: + return "PPCISD::MFOCRF"; + case PPCISD::MFVSR: + return "PPCISD::MFVSR"; + case PPCISD::MTVSRA: + return "PPCISD::MTVSRA"; + case PPCISD::MTVSRZ: + return "PPCISD::MTVSRZ"; + case PPCISD::SINT_VEC_TO_FP: + return "PPCISD::SINT_VEC_TO_FP"; + case PPCISD::UINT_VEC_TO_FP: + return "PPCISD::UINT_VEC_TO_FP"; case PPCISD::SCALAR_TO_VECTOR_PERMUTED: return "PPCISD::SCALAR_TO_VECTOR_PERMUTED"; case PPCISD::ANDI_rec_1_EQ_BIT: return "PPCISD::ANDI_rec_1_EQ_BIT"; case PPCISD::ANDI_rec_1_GT_BIT: return "PPCISD::ANDI_rec_1_GT_BIT"; - case PPCISD::VCMP: return "PPCISD::VCMP"; - case PPCISD::VCMP_rec: return "PPCISD::VCMP_rec"; - case PPCISD::LBRX: return "PPCISD::LBRX"; - case PPCISD::STBRX: return "PPCISD::STBRX"; - case PPCISD::LFIWAX: return "PPCISD::LFIWAX"; - case PPCISD::LFIWZX: return "PPCISD::LFIWZX"; - case PPCISD::LXSIZX: return "PPCISD::LXSIZX"; - case PPCISD::VEC_PAIR_LD: return "PPCISD::VEC_PAIR_LD"; - case PPCISD::VEC_PAIR_ST: return "PPCISD::VEC_PAIR_ST"; - case PPCISD::STXSIX: return "PPCISD::STXSIX"; - case PPCISD::VEXTS: return "PPCISD::VEXTS"; - case PPCISD::LXVD2X: return "PPCISD::LXVD2X"; - case PPCISD::STXVD2X: return "PPCISD::STXVD2X"; - case PPCISD::LOAD_VEC_BE: return "PPCISD::LOAD_VEC_BE"; - case PPCISD::STORE_VEC_BE: return "PPCISD::STORE_VEC_BE"; + case PPCISD::VCMP: + return "PPCISD::VCMP"; + case PPCISD::VCMP_rec: + return "PPCISD::VCMP_rec"; + case PPCISD::LBRX: + return "PPCISD::LBRX"; + case PPCISD::STBRX: + return "PPCISD::STBRX"; + case PPCISD::LFIWAX: + return "PPCISD::LFIWAX"; + case PPCISD::LFIWZX: + return "PPCISD::LFIWZX"; + case PPCISD::LXSIZX: + return "PPCISD::LXSIZX"; + case PPCISD::VEC_PAIR_LD: + return "PPCISD::VEC_PAIR_LD"; + case PPCISD::VEC_PAIR_ST: + return "PPCISD::VEC_PAIR_ST"; + case PPCISD::STXSIX: + return "PPCISD::STXSIX"; + case PPCISD::VEXTS: + return "PPCISD::VEXTS"; + case PPCISD::LXVD2X: + return "PPCISD::LXVD2X"; + case PPCISD::STXVD2X: + return "PPCISD::STXVD2X"; + case PPCISD::LOAD_VEC_BE: + return "PPCISD::LOAD_VEC_BE"; + case PPCISD::STORE_VEC_BE: + return "PPCISD::STORE_VEC_BE"; case PPCISD::ST_VSR_SCAL_INT: - return "PPCISD::ST_VSR_SCAL_INT"; - case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH"; - case PPCISD::BDNZ: return "PPCISD::BDNZ"; - case PPCISD::BDZ: return "PPCISD::BDZ"; - case PPCISD::MFFS: return "PPCISD::MFFS"; - case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ"; - case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN"; - case PPCISD::CR6SET: return "PPCISD::CR6SET"; - case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET"; - case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT"; - case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT"; - case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA"; - case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L"; - case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS"; - case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA"; - case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L"; - case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR"; - case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR"; - case PPCISD::TLSGD_AIX: return "PPCISD::TLSGD_AIX"; - case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA"; - case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L"; - case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR"; - case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR"; - case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA"; - case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L"; + return "PPCISD::ST_VSR_SCAL_INT"; + case PPCISD::COND_BRANCH: + return "PPCISD::COND_BRANCH"; + case PPCISD::BDNZ: + return "PPCISD::BDNZ"; + case PPCISD::BDZ: + return "PPCISD::BDZ"; + case PPCISD::MFFS: + return "PPCISD::MFFS"; + case PPCISD::FADDRTZ: + return "PPCISD::FADDRTZ"; + case PPCISD::TC_RETURN: + return "PPCISD::TC_RETURN"; + case PPCISD::CR6SET: + return "PPCISD::CR6SET"; + case PPCISD::CR6UNSET: + return "PPCISD::CR6UNSET"; + case PPCISD::PPC32_GOT: + return "PPCISD::PPC32_GOT"; + case PPCISD::PPC32_PICGOT: + return "PPCISD::PPC32_PICGOT"; + case PPCISD::ADDIS_GOT_TPREL_HA: + return "PPCISD::ADDIS_GOT_TPREL_HA"; + case PPCISD::LD_GOT_TPREL_L: + return "PPCISD::LD_GOT_TPREL_L"; + case PPCISD::ADD_TLS: + return "PPCISD::ADD_TLS"; + case PPCISD::ADDIS_TLSGD_HA: + return "PPCISD::ADDIS_TLSGD_HA"; + case PPCISD::ADDI_TLSGD_L: + return "PPCISD::ADDI_TLSGD_L"; + case PPCISD::GET_TLS_ADDR: + return "PPCISD::GET_TLS_ADDR"; + case PPCISD::ADDI_TLSGD_L_ADDR: + return "PPCISD::ADDI_TLSGD_L_ADDR"; + case PPCISD::TLSGD_AIX: + return "PPCISD::TLSGD_AIX"; + case PPCISD::ADDIS_TLSLD_HA: + return "PPCISD::ADDIS_TLSLD_HA"; + case PPCISD::ADDI_TLSLD_L: + return "PPCISD::ADDI_TLSLD_L"; + case PPCISD::GET_TLSLD_ADDR: + return "PPCISD::GET_TLSLD_ADDR"; + case PPCISD::ADDI_TLSLD_L_ADDR: + return "PPCISD::ADDI_TLSLD_L_ADDR"; + case PPCISD::ADDIS_DTPREL_HA: + return "PPCISD::ADDIS_DTPREL_HA"; + case PPCISD::ADDI_DTPREL_L: + return "PPCISD::ADDI_DTPREL_L"; case PPCISD::PADDI_DTPREL: return "PPCISD::PADDI_DTPREL"; - case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT"; - case PPCISD::SC: return "PPCISD::SC"; - case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB"; - case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE"; - case PPCISD::RFEBB: return "PPCISD::RFEBB"; - case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD"; - case PPCISD::SWAP_NO_CHAIN: return "PPCISD::SWAP_NO_CHAIN"; - case PPCISD::VABSD: return "PPCISD::VABSD"; - case PPCISD::VABSDU: return "PPCISD::VABSDU"; - case PPCISD::VAVGU: return "PPCISD::VAVGU"; - case PPCISD::VAVGS: return "PPCISD::VAVGS"; - case PPCISD::BUILD_FP128: return "PPCISD::BUILD_FP128"; - case PPCISD::BUILD_SPE64: return "PPCISD::BUILD_SPE64"; - case PPCISD::EXTRACT_SPE: return "PPCISD::EXTRACT_SPE"; - case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI"; - case PPCISD::LD_VSX_LH: return "PPCISD::LD_VSX_LH"; - case PPCISD::FP_EXTEND_HALF: return "PPCISD::FP_EXTEND_HALF"; - case PPCISD::MAT_PCREL_ADDR: return "PPCISD::MAT_PCREL_ADDR"; + case PPCISD::VADD_SPLAT: + return "PPCISD::VADD_SPLAT"; + case PPCISD::SC: + return "PPCISD::SC"; + case PPCISD::CLRBHRB: + return "PPCISD::CLRBHRB"; + case PPCISD::MFBHRBE: + return "PPCISD::MFBHRBE"; + case PPCISD::RFEBB: + return "PPCISD::RFEBB"; + case PPCISD::XXSWAPD: + return "PPCISD::XXSWAPD"; + case PPCISD::SWAP_NO_CHAIN: + return "PPCISD::SWAP_NO_CHAIN"; + case PPCISD::VABSD: + return "PPCISD::VABSD"; + case PPCISD::VABSDU: + return "PPCISD::VABSDU"; + case PPCISD::VAVGU: + return "PPCISD::VAVGU"; + case PPCISD::VAVGS: + return "PPCISD::VAVGS"; + case PPCISD::BUILD_FP128: + return "PPCISD::BUILD_FP128"; + case PPCISD::BUILD_SPE64: + return "PPCISD::BUILD_SPE64"; + case PPCISD::EXTRACT_SPE: + return "PPCISD::EXTRACT_SPE"; + case PPCISD::EXTSWSLI: + return "PPCISD::EXTSWSLI"; + case PPCISD::LD_VSX_LH: + return "PPCISD::LD_VSX_LH"; + case PPCISD::FP_EXTEND_HALF: + return "PPCISD::FP_EXTEND_HALF"; + case PPCISD::MAT_PCREL_ADDR: + return "PPCISD::MAT_PCREL_ADDR"; case PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR: return "PPCISD::TLS_DYNAMIC_MAT_PCREL_ADDR"; case PPCISD::TLS_LOCAL_EXEC_MAT_ADDR: return "PPCISD::TLS_LOCAL_EXEC_MAT_ADDR"; - case PPCISD::ACC_BUILD: return "PPCISD::ACC_BUILD"; - case PPCISD::PAIR_BUILD: return "PPCISD::PAIR_BUILD"; - case PPCISD::EXTRACT_VSX_REG: return "PPCISD::EXTRACT_VSX_REG"; - case PPCISD::XXMFACC: return "PPCISD::XXMFACC"; - case PPCISD::LD_SPLAT: return "PPCISD::LD_SPLAT"; - case PPCISD::ZEXT_LD_SPLAT: return "PPCISD::ZEXT_LD_SPLAT"; - case PPCISD::SEXT_LD_SPLAT: return "PPCISD::SEXT_LD_SPLAT"; - case PPCISD::FNMSUB: return "PPCISD::FNMSUB"; + case PPCISD::ACC_BUILD: + return "PPCISD::ACC_BUILD"; + case PPCISD::PAIR_BUILD: + return "PPCISD::PAIR_BUILD"; + case PPCISD::EXTRACT_VSX_REG: + return "PPCISD::EXTRACT_VSX_REG"; + case PPCISD::XXMFACC: + return "PPCISD::XXMFACC"; + case PPCISD::LD_SPLAT: + return "PPCISD::LD_SPLAT"; + case PPCISD::ZEXT_LD_SPLAT: + return "PPCISD::ZEXT_LD_SPLAT"; + case PPCISD::SEXT_LD_SPLAT: + return "PPCISD::SEXT_LD_SPLAT"; + case PPCISD::FNMSUB: + return "PPCISD::FNMSUB"; case PPCISD::STRICT_FADDRTZ: return "PPCISD::STRICT_FADDRTZ"; case PPCISD::STRICT_FCTIDZ: @@ -1874,7 +1999,8 @@ return "PPCISD::STRICT_FCFIDS"; case PPCISD::STRICT_FCFIDUS: return "PPCISD::STRICT_FCFIDUS"; - case PPCISD::LXVRZX: return "PPCISD::LXVRZX"; + case PPCISD::LXVRZX: + return "PPCISD::LXVRZX"; case PPCISD::LXVL: return "PPCISD::LXVL"; case PPCISD::STXVL: @@ -1924,9 +2050,7 @@ /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return /// true if Op is undef or if it matches the specified value. -static bool isConstantOrUndef(int Op, int Val) { - return Op < 0 || Op == Val; -} +static bool isConstantOrUndef(int Op, int Val) { return Op < 0 || Op == Val; } /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a /// VPKUHUM instruction. @@ -1941,19 +2065,19 @@ if (IsLE) return false; for (unsigned i = 0; i != 16; ++i) - if (!isConstantOrUndef(N->getMaskElt(i), i*2+1)) + if (!isConstantOrUndef(N->getMaskElt(i), i * 2 + 1)) return false; } else if (ShuffleKind == 2) { if (!IsLE) return false; for (unsigned i = 0; i != 16; ++i) - if (!isConstantOrUndef(N->getMaskElt(i), i*2)) + if (!isConstantOrUndef(N->getMaskElt(i), i * 2)) return false; } else if (ShuffleKind == 1) { unsigned j = IsLE ? 0 : 1; for (unsigned i = 0; i != 8; ++i) - if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) || - !isConstantOrUndef(N->getMaskElt(i+8), i*2+j)) + if (!isConstantOrUndef(N->getMaskElt(i), i * 2 + j) || + !isConstantOrUndef(N->getMaskElt(i + 8), i * 2 + j)) return false; } return true; @@ -1972,23 +2096,23 @@ if (IsLE) return false; for (unsigned i = 0; i != 16; i += 2) - if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) || - !isConstantOrUndef(N->getMaskElt(i+1), i*2+3)) + if (!isConstantOrUndef(N->getMaskElt(i), i * 2 + 2) || + !isConstantOrUndef(N->getMaskElt(i + 1), i * 2 + 3)) return false; } else if (ShuffleKind == 2) { if (!IsLE) return false; for (unsigned i = 0; i != 16; i += 2) - if (!isConstantOrUndef(N->getMaskElt(i ), i*2) || - !isConstantOrUndef(N->getMaskElt(i+1), i*2+1)) + if (!isConstantOrUndef(N->getMaskElt(i), i * 2) || + !isConstantOrUndef(N->getMaskElt(i + 1), i * 2 + 1)) return false; } else if (ShuffleKind == 1) { unsigned j = IsLE ? 0 : 2; for (unsigned i = 0; i != 8; i += 2) - if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) || - !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) || - !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) || - !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1)) + if (!isConstantOrUndef(N->getMaskElt(i), i * 2 + j) || + !isConstantOrUndef(N->getMaskElt(i + 1), i * 2 + j + 1) || + !isConstantOrUndef(N->getMaskElt(i + 8), i * 2 + j) || + !isConstantOrUndef(N->getMaskElt(i + 9), i * 2 + j + 1)) return false; } return true; @@ -2013,31 +2137,31 @@ if (IsLE) return false; for (unsigned i = 0; i != 16; i += 4) - if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) || - !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) || - !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) || - !isConstantOrUndef(N->getMaskElt(i+3), i*2+7)) + if (!isConstantOrUndef(N->getMaskElt(i), i * 2 + 4) || + !isConstantOrUndef(N->getMaskElt(i + 1), i * 2 + 5) || + !isConstantOrUndef(N->getMaskElt(i + 2), i * 2 + 6) || + !isConstantOrUndef(N->getMaskElt(i + 3), i * 2 + 7)) return false; } else if (ShuffleKind == 2) { if (!IsLE) return false; for (unsigned i = 0; i != 16; i += 4) - if (!isConstantOrUndef(N->getMaskElt(i ), i*2) || - !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) || - !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) || - !isConstantOrUndef(N->getMaskElt(i+3), i*2+3)) + if (!isConstantOrUndef(N->getMaskElt(i), i * 2) || + !isConstantOrUndef(N->getMaskElt(i + 1), i * 2 + 1) || + !isConstantOrUndef(N->getMaskElt(i + 2), i * 2 + 2) || + !isConstantOrUndef(N->getMaskElt(i + 3), i * 2 + 3)) return false; } else if (ShuffleKind == 1) { unsigned j = IsLE ? 0 : 4; for (unsigned i = 0; i != 8; i += 4) - if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) || - !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) || - !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) || - !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) || - !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) || - !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) || - !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) || - !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3)) + if (!isConstantOrUndef(N->getMaskElt(i), i * 2 + j) || + !isConstantOrUndef(N->getMaskElt(i + 1), i * 2 + j + 1) || + !isConstantOrUndef(N->getMaskElt(i + 2), i * 2 + j + 2) || + !isConstantOrUndef(N->getMaskElt(i + 3), i * 2 + j + 3) || + !isConstantOrUndef(N->getMaskElt(i + 8), i * 2 + j) || + !isConstantOrUndef(N->getMaskElt(i + 9), i * 2 + j + 1) || + !isConstantOrUndef(N->getMaskElt(i + 10), i * 2 + j + 2) || + !isConstantOrUndef(N->getMaskElt(i + 11), i * 2 + j + 3)) return false; } return true; @@ -2052,12 +2176,12 @@ assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && "Unsupported merge size!"); - for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units - for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit - if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j), - LHSStart+j+i*UnitSize) || - !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j), - RHSStart+j+i*UnitSize)) + for (unsigned i = 0; i != 8 / UnitSize; ++i) // Step over units + for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit + if (!isConstantOrUndef(N->getMaskElt(i * UnitSize * 2 + j), + LHSStart + j + i * UnitSize) || + !isConstantOrUndef(N->getMaskElt(i * UnitSize * 2 + UnitSize + j), + RHSStart + j + i * UnitSize)) return false; } return true; @@ -2162,10 +2286,10 @@ for (unsigned i = 0; i < 2; ++i) for (unsigned j = 0; j < 4; ++j) - if (!isConstantOrUndef(N->getMaskElt(i*4+j), - i*RHSStartValue+j+IndexOffset) || - !isConstantOrUndef(N->getMaskElt(i*4+j+8), - i*RHSStartValue+j+IndexOffset+8)) + if (!isConstantOrUndef(N->getMaskElt(i * 4 + j), + i * RHSStartValue + j + IndexOffset) || + !isConstantOrUndef(N->getMaskElt(i * 4 + j + 8), + i * RHSStartValue + j + IndexOffset + 8)) return false; return true; } @@ -2194,8 +2318,7 @@ return isVMerge(N, indexOffset, 16); else return false; - } - else { + } else { unsigned indexOffset = CheckEven ? 0 : 4; if (ShuffleKind == 1) // Unary return isVMerge(N, indexOffset, 0); @@ -2225,12 +2348,14 @@ for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i) /*search*/; - if (i == 16) return -1; // all undef. + if (i == 16) + return -1; // all undef. // Otherwise, check to see if the rest of the elements are consecutively // numbered from this value. unsigned ShiftAmt = SVOp->getMaskElt(i); - if (ShiftAmt < i) return -1; + if (ShiftAmt < i) + return -1; ShiftAmt -= i; bool isLE = DAG.getDataLayout().isLittleEndian(); @@ -2238,12 +2363,12 @@ if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) { // Check the rest of the elements to see if they are consecutive. for (++i; i != 16; ++i) - if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) + if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt + i)) return -1; } else if (ShuffleKind == 1) { // Check the rest of the elements to see if they are consecutive. for (++i; i != 16; ++i) - if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) + if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt + i) & 15)) return -1; } else return -1; @@ -2262,8 +2387,8 @@ if (VT == MVT::v2i64 || VT == MVT::v2f64) return EltSize == 8 && N->getMaskElt(0) == N->getMaskElt(1); - assert(VT == MVT::v16i8 && isPowerOf2_32(EltSize) && - EltSize <= 8 && "Can only handle 1,2,4,8 byte element sizes"); + assert(VT == MVT::v16i8 && isPowerOf2_32(EltSize) && EltSize <= 8 && + "Can only handle 1,2,4,8 byte element sizes"); // The consecutive indices need to specify an element, not part of two // different elements. So abandon ship early if this isn't the case. @@ -2281,13 +2406,14 @@ // Check that the indices are consecutive, in the case of a multi-byte element // splatted with a v16i8 mask. for (unsigned i = 1; i != EltSize; ++i) - if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase)) + if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i + ElementBase)) return false; for (unsigned i = EltSize, e = 16; i != e; i += EltSize) { - if (N->getMaskElt(i) < 0) continue; + if (N->getMaskElt(i) < 0) + continue; for (unsigned j = 0; j != EltSize; ++j) - if (N->getMaskElt(i+j) != N->getMaskElt(j)) + if (N->getMaskElt(i + j) != N->getMaskElt(j)) return false; } return true; @@ -2320,7 +2446,7 @@ for (unsigned int j = 1; j < Width; ++j) { MaskVal[j] = N->getMaskElt(i * Width + j); - if (MaskVal[j] != MaskVal[j-1] + StepLen) { + if (MaskVal[j] != MaskVal[j - 1] + StepLen) { return false; } } @@ -2339,8 +2465,8 @@ unsigned M1 = N->getMaskElt(4) / 4; unsigned M2 = N->getMaskElt(8) / 4; unsigned M3 = N->getMaskElt(12) / 4; - unsigned LittleEndianShifts[] = { 2, 1, 0, 3 }; - unsigned BigEndianShifts[] = { 3, 0, 1, 2 }; + unsigned LittleEndianShifts[] = {2, 1, 0, 3}; + unsigned BigEndianShifts[] = {3, 0, 1, 2}; // Below, let H and L be arbitrary elements of the shuffle mask // where H is in the range [4,7] and L is in the range [0,3]. @@ -2449,7 +2575,7 @@ } return true; - } else { // BE + } else { // BE if (M0 == 0 || M0 == 1 || M0 == 2 || M0 == 3) { // Input vectors don't need to be swapped if the leading element // of the result is one of the 4 elements of the first vector. @@ -2504,7 +2630,7 @@ /// \return true iff the given mask of shuffle node \p N is a XXPERMDI shuffle /// mask. bool PPC::isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &DM, - bool &Swap, bool IsLE) { + bool &Swap, bool IsLE) { assert(N->getValueType(0) == MVT::v16i8 && "Shuffle vector expects v16i8"); // Ensure each byte index of the double word is consecutive. @@ -2555,7 +2681,6 @@ } } - /// getSplatIdxForPPCMnemonics - Return the splat index as a value that is /// appropriate for PPC mnemonics (which have a big endian bias - namely /// elements are counted from the left of the vector register). @@ -2586,22 +2711,24 @@ // build_vector, then we have a case where we are checking for a splat where // multiple elements of the buildvector are folded together into a single // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8). - unsigned EltSize = 16/N->getNumOperands(); + unsigned EltSize = 16 / N->getNumOperands(); if (EltSize < ByteSize) { - unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval. + unsigned Multiple = ByteSize / EltSize; // Number of BV entries per spltval. SDValue UniquedVals[4]; assert(Multiple > 1 && Multiple <= 4 && "How can this happen?"); // See if all of the elements in the buildvector agree across. for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { - if (N->getOperand(i).isUndef()) continue; + if (N->getOperand(i).isUndef()) + continue; // If the element isn't a constant, bail fully out. - if (!isa(N->getOperand(i))) return SDValue(); + if (!isa(N->getOperand(i))) + return SDValue(); - if (!UniquedVals[i&(Multiple-1)].getNode()) - UniquedVals[i&(Multiple-1)] = N->getOperand(i); - else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i)) - return SDValue(); // no match. + if (!UniquedVals[i & (Multiple - 1)].getNode()) + UniquedVals[i & (Multiple - 1)] = N->getOperand(i); + else if (UniquedVals[i & (Multiple - 1)] != N->getOperand(i)) + return SDValue(); // no match. } // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains @@ -2612,25 +2739,26 @@ // neither, then this won't fit into the immediate field. bool LeadingZero = true; bool LeadingOnes = true; - for (unsigned i = 0; i != Multiple-1; ++i) { - if (!UniquedVals[i].getNode()) continue; // Must have been undefs. + for (unsigned i = 0; i != Multiple - 1; ++i) { + if (!UniquedVals[i].getNode()) + continue; // Must have been undefs. LeadingZero &= isNullConstant(UniquedVals[i]); LeadingOnes &= isAllOnesConstant(UniquedVals[i]); } // Finally, check the least significant entry. if (LeadingZero) { - if (!UniquedVals[Multiple-1].getNode()) - return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef - int Val = cast(UniquedVals[Multiple-1])->getZExtValue(); - if (Val < 16) // 0,0,0,4 -> vspltisw(4) + if (!UniquedVals[Multiple - 1].getNode()) + return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef + int Val = cast(UniquedVals[Multiple - 1])->getZExtValue(); + if (Val < 16) // 0,0,0,4 -> vspltisw(4) return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32); } if (LeadingOnes) { - if (!UniquedVals[Multiple-1].getNode()) + if (!UniquedVals[Multiple - 1].getNode()) return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef - int Val =cast(UniquedVals[Multiple-1])->getSExtValue(); - if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) + int Val = cast(UniquedVals[Multiple - 1])->getSExtValue(); + if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32); } @@ -2639,14 +2767,16 @@ // Check to see if this buildvec has a single non-undef value in its elements. for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { - if (N->getOperand(i).isUndef()) continue; + if (N->getOperand(i).isUndef()) + continue; if (!OpVal.getNode()) OpVal = N->getOperand(i); else if (OpVal != N->getOperand(i)) return SDValue(); } - if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def. + if (!OpVal.getNode()) + return SDValue(); // All UNDEF: use implicit def. unsigned ValSizeInBytes = EltSize; uint64_t Value = 0; @@ -2660,7 +2790,8 @@ // If the splat value is larger than the element value, then we can never do // this splat. The only case that we could fit the replicated bits into our // immediate field for would be zero, and we prefer to use vxor for it. - if (ValSizeInBytes < ByteSize) return SDValue(); + if (ValSizeInBytes < ByteSize) + return SDValue(); // If the element value is larger than the splat value, check if it consists // of a repeated bit pattern of size ByteSize. @@ -2671,7 +2802,8 @@ int MaskVal = SignExtend32(Value, ByteSize * 8); // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros. - if (MaskVal == 0) return SDValue(); + if (MaskVal == 0) + return SDValue(); // Finally, if this value fits in a 5 bit sext field, return it if (SignExtend32<5>(MaskVal) == MaskVal) @@ -2724,9 +2856,9 @@ for (SDNode *U : N->uses()) { if (MemSDNode *Memop = dyn_cast(U)) { if (Memop->getMemoryVT() == MVT::f64) { - Base = N.getOperand(0); - Index = N.getOperand(1); - return true; + Base = N.getOperand(0); + Index = N.getOperand(1); + return true; } } } @@ -2766,12 +2898,12 @@ // Is there any SPE load/store (f64), which can't handle 16bit offset? // SPE load/store can only handle 8-bit offsets. if (hasSPE() && SelectAddressEVXRegReg(N, Base, Index, DAG)) - return true; + return true; if (isIntS16Immediate(N.getOperand(1), Imm) && (!EncodingAlignment || isAligned(*EncodingAlignment, Imm))) return false; // r+i if (N.getOperand(1).getOpcode() == PPCISD::Lo) - return false; // r+i + return false; // r+i Base = N.getOperand(0); Index = N.getOperand(1); @@ -2873,15 +3005,16 @@ return true; // [r+i] } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) { // Match LOAD (ADD (X, Lo(G))). - assert(!cast(N.getOperand(1).getOperand(1))->getZExtValue() - && "Cannot handle constant offsets yet!"); - Disp = N.getOperand(1).getOperand(0); // The global address. + assert(!cast(N.getOperand(1).getOperand(1)) + ->getZExtValue() && + "Cannot handle constant offsets yet!"); + Disp = N.getOperand(1).getOperand(0); // The global address. assert(Disp.getOpcode() == ISD::TargetGlobalAddress || Disp.getOpcode() == ISD::TargetGlobalTLSAddress || Disp.getOpcode() == ISD::TargetConstantPool || Disp.getOpcode() == ISD::TargetJumpTable); Base = N.getOperand(0); - return true; // [&g+r] + return true; // [&g+r] } } else if (N.getOpcode() == ISD::OR) { int16_t imm = 0; @@ -2892,11 +3025,11 @@ // provably disjoint. KnownBits LHSKnown = DAG.computeKnownBits(N.getOperand(0)); - if ((LHSKnown.Zero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { + if ((LHSKnown.Zero.getZExtValue() | ~(uint64_t)imm) == ~0ULL) { // If all of the bits are known zero on the LHS or RHS, the add won't // carry. if (FrameIndexSDNode *FI = - dyn_cast(N.getOperand(0))) { + dyn_cast(N.getOperand(0))) { Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); fixupFuncForFI(DAG, FI->getIndex(), N.getValueType()); } else { @@ -2944,7 +3077,7 @@ fixupFuncForFI(DAG, FI->getIndex(), N.getValueType()); } else Base = N; - return true; // [r+0] + return true; // [r+0] } /// Similar to the 16-bit case but for instructions that take a 34-bit @@ -3051,7 +3184,7 @@ /// Returns true if we should use a direct load into vector instruction /// (such as lxsd or lfd), instead of a load into gpr + direct move sequence. -static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) { +static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget &ST) { // If there are any other uses other than scalar to vector, then we should // keep it as a scalar load -> direct move pattern to prevent multiple @@ -3063,7 +3196,7 @@ EVT MemVT = LD->getMemoryVT(); if (!MemVT.isSimple()) return false; - switch(MemVT.getSimpleVT().SimpleTy) { + switch (MemVT.getSimpleVT().SimpleTy) { case MVT::i64: break; case MVT::i32: @@ -3083,8 +3216,8 @@ if (!LoadedVal.hasOneUse()) return false; - for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); - UI != UE; ++UI) + for (SDNode::use_iterator UI = LD->use_begin(), UE = LD->use_end(); UI != UE; + ++UI) if (UI.getUse().get().getResNo() == 0 && UI->getOpcode() != ISD::SCALAR_TO_VECTOR && UI->getOpcode() != PPCISD::SCALAR_TO_VECTOR_PERMUTED) @@ -3100,7 +3233,8 @@ SDValue &Offset, ISD::MemIndexedMode &AM, SelectionDAG &DAG) const { - if (DisablePPCPreinc) return false; + if (DisablePPCPreinc) + return false; bool isLoad = true; SDValue Ptr; @@ -3112,7 +3246,7 @@ Alignment = LD->getAlign(); } else if (StoreSDNode *ST = dyn_cast(N)) { Ptr = ST->getBasePtr(); - VT = ST->getMemoryVT(); + VT = ST->getMemoryVT(); Alignment = ST->getAlign(); isLoad = false; } else @@ -3168,8 +3302,7 @@ // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of // sext i32 to i64 when addr mode is r+i. if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && - LD->getExtensionType() == ISD::SEXTLOAD && - isa(Offset)) + LD->getExtensionType() == ISD::SEXTLOAD && isa(Offset)) return false; } @@ -3229,10 +3362,10 @@ const bool Is64Bit = Subtarget.isPPC64(); EVT VT = Is64Bit ? MVT::i64 : MVT::i32; SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) - : Subtarget.isAIXABI() - ? DAG.getRegister(PPC::R2, VT) - : DAG.getNode(PPCISD::GlobalBaseReg, dl, VT); - SDValue Ops[] = { GA, Reg }; + : Subtarget.isAIXABI() + ? DAG.getRegister(PPC::R2, VT) + : DAG.getNode(PPCISD::GlobalBaseReg, dl, VT); + SDValue Ops[] = {GA, Reg}; return DAG.getMemIntrinsicNode( PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT, MachinePointerInfo::getGOT(DAG.getMachineFunction()), None, @@ -3257,8 +3390,9 @@ } setUsesTOCBasePtr(DAG); - assert(!Subtarget.isAIXABI() || CP->getAlign() <= 16 && - "Not expecting constants with alignment greater than 16."); + assert(!Subtarget.isAIXABI() || + CP->getAlign() <= 16 && + "Not expecting constants with alignment greater than 16."); SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlign(), 0); return getTOCEntry(DAG, SDLoc(CP), GA); @@ -3314,10 +3448,8 @@ } } -const MCExpr * -PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, - unsigned JTI, - MCContext &Ctx) const { +const MCExpr *PPCTargetLowering::getPICJumpTableRelocBaseExpr( + const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const { if (!Subtarget.isPPC64() || Subtarget.isAIXABI()) return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); @@ -3357,8 +3489,8 @@ getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag); if (IsPIC && Subtarget.isSVR4ABI()) { - SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, - PPCII::MO_PIC_FLAG); + SDValue GA = + DAG.getTargetJumpTable(JT->getIndex(), PtrVT, PPCII::MO_PIC_FLAG); return getTOCEntry(DAG, SDLoc(GA), GA); } @@ -3406,7 +3538,7 @@ } SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, - SelectionDAG &DAG) const { + SelectionDAG &DAG) const { if (Subtarget.isAIXABI()) return LowerGlobalTLSAddressAIX(Op, DAG); @@ -3470,10 +3602,10 @@ return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TLSReg, MatAddr); } - SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, - PPCII::MO_TPREL_HA); - SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, - PPCII::MO_TPREL_LO); + SDValue TGAHi = + DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TPREL_HA); + SDValue TGALo = + DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, PPCII::MO_TPREL_LO); SDValue TLSReg = is64bit ? DAG.getRegister(PPC::X13, MVT::i64) : DAG.getRegister(PPC::R2, MVT::i32); @@ -3525,16 +3657,14 @@ if (is64bit) { setUsesTOCBasePtr(DAG); SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); - GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT, - GOTReg, TGA); + GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT, GOTReg, TGA); } else { if (picLevel == PICLevel::SmallPIC) GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT); else GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT); } - return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT, - GOTPtr, TGA, TGA); + return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT, GOTPtr, TGA, TGA); } if (Model == TLSModel::LocalDynamic) { @@ -3551,18 +3681,17 @@ if (is64bit) { setUsesTOCBasePtr(DAG); SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64); - GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT, - GOTReg, TGA); + GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT, GOTReg, TGA); } else { if (picLevel == PICLevel::SmallPIC) GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT); else GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT); } - SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl, - PtrVT, GOTPtr, TGA, TGA); - SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, - PtrVT, TLSAddr, TGA); + SDValue TLSAddr = + DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl, PtrVT, GOTPtr, TGA, TGA); + SDValue DtvOffsetHi = + DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT, TLSAddr, TGA); return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA); } @@ -3605,16 +3734,15 @@ getLabelAccessInfo(IsPIC, Subtarget, MOHiFlag, MOLoFlag, GV); if (IsPIC && Subtarget.isSVR4ABI()) { - SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, - GSDN->getOffset(), + SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), PPCII::MO_PIC_FLAG); return getTOCEntry(DAG, DL, GA); } SDValue GAHi = - DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag); + DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag); SDValue GALo = - DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag); + DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag); return LowerLabelRef(GAHi, GALo, IsPIC, DAG); } @@ -3720,8 +3848,8 @@ SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex, DAG.getConstant(1, dl, MVT::i32)); // Align GprIndex to be even if it isn't - GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne, - GprIndex); + GprIndex = + DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne, GprIndex); } // fpr index is 1 byte after gpr @@ -3753,14 +3881,12 @@ DAG.getConstant(8, dl, MVT::i32), ISD::SETLT); // adjustment constant gpr_index * 4/8 - SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, - VT.isInteger() ? GprIndex : FprIndex, - DAG.getConstant(VT.isInteger() ? 4 : 8, dl, - MVT::i32)); + SDValue RegConstant = + DAG.getNode(ISD::MUL, dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, + DAG.getConstant(VT.isInteger() ? 4 : 8, dl, MVT::i32)); // OurReg = RegSaveArea + RegConstant - SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea, - RegConstant); + SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea, RegConstant); // Floating types are 32 bytes into RegSaveArea if (VT.isFloatingPoint()) @@ -3768,22 +3894,22 @@ DAG.getConstant(32, dl, MVT::i32)); // increase {f,g}pr_index by 1 (or 2 if VT is i64) - SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32, - VT.isInteger() ? GprIndex : FprIndex, - DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl, - MVT::i32)); + SDValue IndexPlus1 = + DAG.getNode(ISD::ADD, dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, + DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl, MVT::i32)); InChain = DAG.getTruncStore(InChain, dl, IndexPlus1, VT.isInteger() ? VAListPtr : FprPtr, MachinePointerInfo(SV), MVT::i8); // determine if we should load from reg_save_area or overflow_area - SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea); + SDValue Result = + DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea); // increase overflow_area by 4/8 if gpr/fpr > 8 - SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea, - DAG.getConstant(VT.isInteger() ? 4 : 8, - dl, MVT::i32)); + SDValue OverflowAreaPlusN = + DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea, + DAG.getConstant(VT.isInteger() ? 4 : 8, dl, MVT::i32)); OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea, OverflowAreaPlusN); @@ -3883,15 +4009,18 @@ TargetLowering::ArgListEntry Entry; Entry.Ty = IntPtrTy; - Entry.Node = Trmp; Args.push_back(Entry); + Entry.Node = Trmp; + Args.push_back(Entry); // TrampSize == (isPPC64 ? 48 : 40); - Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl, - isPPC64 ? MVT::i64 : MVT::i32); + Entry.Node = + DAG.getConstant(isPPC64 ? 48 : 40, dl, isPPC64 ? MVT::i64 : MVT::i32); Args.push_back(Entry); - Entry.Node = FPtr; Args.push_back(Entry); - Entry.Node = Nest; Args.push_back(Entry); + Entry.Node = FPtr; + Args.push_back(Entry); + Entry.Node = Nest; + Args.push_back(Entry); // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) TargetLowering::CallLoweringInfo CLI(DAG); @@ -3945,15 +4074,14 @@ SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32); SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32); - SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(), - PtrVT); - SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), - PtrVT); + SDValue StackOffsetFI = + DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(), PtrVT); + SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); - uint64_t FrameOffset = PtrVT.getSizeInBits()/8; + uint64_t FrameOffset = PtrVT.getSizeInBits() / 8; SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT); - uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1; + uint64_t StackOffset = PtrVT.getSizeInBits() / 8 - 1; SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT); uint64_t FPROffset = 1; @@ -3966,8 +4094,8 @@ DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, Op.getOperand(1), MachinePointerInfo(SV), MVT::i8); uint64_t nextOffset = FPROffset; - SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), - ConstFPROffset); + SDValue nextPtr = + DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), ConstFPROffset); // Store second byte : number of float regs SDValue secondStore = @@ -4004,7 +4132,7 @@ // Round up to multiples of the pointer size, except for array members, // which are always packed. if (!Flags.isInConsecutiveRegs()) - ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; + ArgSize = ((ArgSize + PtrByteSize - 1) / PtrByteSize) * PtrByteSize; return ArgSize; } @@ -4017,9 +4145,8 @@ Align Alignment(PtrByteSize); // Altivec parameters are padded to a 16 byte boundary. - if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || - ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || - ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || + if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || ArgVT == MVT::v8i16 || + ArgVT == MVT::v16i8 || ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || ArgVT == MVT::v1i128 || ArgVT == MVT::f128) Alignment = Align(16); @@ -4072,7 +4199,7 @@ // Allocate argument on the stack. ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); if (Flags.isInConsecutiveRegsLast()) - ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; + ArgOffset = ((ArgOffset + PtrByteSize - 1) / PtrByteSize) * PtrByteSize; // If we overran the argument save area, we must use memory // (this check catches arguments passed partially in memory) if (ArgOffset > LinkageSize + ParamAreaSize) @@ -4086,9 +4213,8 @@ --AvailableFPRs; return false; } - if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || - ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 || - ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || + if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 || ArgVT == MVT::v8i16 || + ArgVT == MVT::v16i8 || ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 || ArgVT == MVT::v1i128 || ArgVT == MVT::f128) if (AvailableVRs > 0) { --AvailableVRs; @@ -4168,7 +4294,7 @@ // Assign locations to all of the incoming arguments. SmallVector ArgLocs; PPCCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs, - *DAG.getContext()); + *DAG.getContext()); // Reserve space for the linkage area on the stack. unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); @@ -4188,41 +4314,41 @@ EVT ValVT = VA.getValVT(); switch (ValVT.getSimpleVT().SimpleTy) { - default: - llvm_unreachable("ValVT not supported by formal arguments Lowering"); - case MVT::i1: - case MVT::i32: + default: + llvm_unreachable("ValVT not supported by formal arguments Lowering"); + case MVT::i1: + case MVT::i32: + RC = &PPC::GPRCRegClass; + break; + case MVT::f32: + if (Subtarget.hasP8Vector()) + RC = &PPC::VSSRCRegClass; + else if (Subtarget.hasSPE()) RC = &PPC::GPRCRegClass; - break; - case MVT::f32: - if (Subtarget.hasP8Vector()) - RC = &PPC::VSSRCRegClass; - else if (Subtarget.hasSPE()) - RC = &PPC::GPRCRegClass; - else - RC = &PPC::F4RCRegClass; - break; - case MVT::f64: - if (Subtarget.hasVSX()) - RC = &PPC::VSFRCRegClass; - else if (Subtarget.hasSPE()) - // SPE passes doubles in GPR pairs. - RC = &PPC::GPRCRegClass; - else - RC = &PPC::F8RCRegClass; - break; - case MVT::v16i8: - case MVT::v8i16: - case MVT::v4i32: - RC = &PPC::VRRCRegClass; - break; - case MVT::v4f32: - RC = &PPC::VRRCRegClass; - break; - case MVT::v2f64: - case MVT::v2i64: - RC = &PPC::VRRCRegClass; - break; + else + RC = &PPC::F4RCRegClass; + break; + case MVT::f64: + if (Subtarget.hasVSX()) + RC = &PPC::VSFRCRegClass; + else if (Subtarget.hasSPE()) + // SPE passes doubles in GPR pairs. + RC = &PPC::GPRCRegClass; + else + RC = &PPC::F8RCRegClass; + break; + case MVT::v16i8: + case MVT::v8i16: + case MVT::v4i32: + RC = &PPC::VRRCRegClass; + break; + case MVT::v4f32: + RC = &PPC::VRRCRegClass; + break; + case MVT::v2f64: + case MVT::v2i64: + RC = &PPC::VRRCRegClass; + break; } SDValue ArgValue; @@ -4235,7 +4361,7 @@ SDValue ArgValueLo = DAG.getCopyFromReg(Chain, dl, RegLo, MVT::i32); SDValue ArgValueHi = DAG.getCopyFromReg(Chain, dl, RegHi, MVT::i32); if (!Subtarget.isLittleEndian()) - std::swap (ArgValueLo, ArgValueHi); + std::swap(ArgValueLo, ArgValueHi); ArgValue = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, ArgValueLo, ArgValueHi); } else { @@ -4297,30 +4423,26 @@ // the start of the first vararg value... for expansion of llvm.va_start. if (isVarArg) { static const MCPhysReg GPArgRegs[] = { - PPC::R3, PPC::R4, PPC::R5, PPC::R6, - PPC::R7, PPC::R8, PPC::R9, PPC::R10, + PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, }; const unsigned NumGPArgRegs = array_lengthof(GPArgRegs); - static const MCPhysReg FPArgRegs[] = { - PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, - PPC::F8 - }; + static const MCPhysReg FPArgRegs[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, + PPC::F5, PPC::F6, PPC::F7, PPC::F8}; unsigned NumFPArgRegs = array_lengthof(FPArgRegs); if (useSoftFloat() || hasSPE()) - NumFPArgRegs = 0; + NumFPArgRegs = 0; FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs)); FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs)); // Make room for NumGPArgRegs and NumFPArgRegs. - int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + - NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8; + int Depth = NumGPArgRegs * PtrVT.getSizeInBits() / 8 + + NumFPArgRegs * MVT(MVT::f64).getSizeInBits() / 8; - FuncInfo->setVarArgsStackOffset( - MFI.CreateFixedObject(PtrVT.getSizeInBits()/8, - CCInfo.getNextStackOffset(), true)); + FuncInfo->setVarArgsStackOffset(MFI.CreateFixedObject( + PtrVT.getSizeInBits() / 8, CCInfo.getNextStackOffset(), true)); FuncInfo->setVarArgsFrameIndex( MFI.CreateStackObject(Depth, Align(8), false)); @@ -4340,7 +4462,7 @@ DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo()); MemOps.push_back(Store); // Increment the address by four for the next argument to store - SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT); + SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits() / 8, dl, PtrVT); FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); } @@ -4359,8 +4481,8 @@ DAG.getStore(Val.getValue(1), dl, Val, FIN, MachinePointerInfo()); MemOps.push_back(Store); // Increment the address by eight for the next argument to store - SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl, - PtrVT); + SDValue PtrOff = + DAG.getConstant(MVT(MVT::f64).getSizeInBits() / 8, dl, PtrVT); FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); } } @@ -4410,17 +4532,15 @@ unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); static const MCPhysReg GPR[] = { - PPC::X3, PPC::X4, PPC::X5, PPC::X6, - PPC::X7, PPC::X8, PPC::X9, PPC::X10, - }; - static const MCPhysReg VR[] = { - PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, - PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 + PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, }; + static const MCPhysReg VR[] = {PPC::V2, PPC::V3, PPC::V4, PPC::V5, + PPC::V6, PPC::V7, PPC::V8, PPC::V9, + PPC::V10, PPC::V11, PPC::V12, PPC::V13}; const unsigned Num_GPR_Regs = array_lengthof(GPR); const unsigned Num_FPR_Regs = useSoftFloat() ? 0 : 13; - const unsigned Num_VR_Regs = array_lengthof(VR); + const unsigned Num_VR_Regs = array_lengthof(VR); // Do a first pass over the arguments to determine whether the ABI // guarantees that our caller has allocated the parameter save area @@ -4495,7 +4615,7 @@ // ObjSize is the true size, ArgSize rounded up to multiple of registers. ObjSize = Flags.getByValSize(); - ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; + ArgSize = ((ObjSize + PtrByteSize - 1) / PtrByteSize) * PtrByteSize; // Empty aggregate parameters do not take up registers. Examples: // struct { } a; // union { } b; @@ -4581,7 +4701,8 @@ } switch (ObjectVT.getSimpleVT().SimpleTy) { - default: llvm_unreachable("Unhandled argument type!"); + default: + llvm_unreachable("Unhandled argument type!"); case MVT::i1: case MVT::i32: case MVT::i64: @@ -4628,10 +4749,9 @@ unsigned VReg; if (ObjectVT == MVT::f32) - VReg = MF.addLiveIn(FPR[FPR_idx], - Subtarget.hasP8Vector() - ? &PPC::VSSRCRegClass - : &PPC::F4RCRegClass); + VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasP8Vector() + ? &PPC::VSSRCRegClass + : &PPC::F4RCRegClass); else VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ? &PPC::VSFRCRegClass @@ -4672,7 +4792,8 @@ ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize; ArgOffset += ArgSize; if (Flags.isInConsecutiveRegsLast()) - ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; + ArgOffset = + ((ArgOffset + PtrByteSize - 1) / PtrByteSize) * PtrByteSize; } break; case MVT::v4f32: @@ -4738,7 +4859,7 @@ int Depth = ArgOffset; FuncInfo->setVarArgsFrameIndex( - MFI.CreateFixedObject(PtrByteSize, Depth, true)); + MFI.CreateFixedObject(PtrByteSize, Depth, true)); SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); // If this function is vararg, store any remaining integer argument regs @@ -4765,10 +4886,11 @@ /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be /// adjusted to accommodate the arguments for the tailcall. -static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, +static int CalculateTailCallSPDiff(SelectionDAG &DAG, bool isTailCall, unsigned ParamSize) { - if (!isTailCall) return 0; + if (!isTailCall) + return 0; PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo(); unsigned CallerMinReservedArea = FI->getMinReservedArea(); @@ -4870,13 +4992,11 @@ const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize(); static const MCPhysReg GPR[] = { - PPC::X3, PPC::X4, PPC::X5, PPC::X6, - PPC::X7, PPC::X8, PPC::X9, PPC::X10, - }; - static const MCPhysReg VR[] = { - PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, - PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 + PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, }; + static const MCPhysReg VR[] = {PPC::V2, PPC::V3, PPC::V4, PPC::V5, + PPC::V6, PPC::V7, PPC::V8, PPC::V9, + PPC::V10, PPC::V11, PPC::V12, PPC::V13}; const unsigned NumGPRs = array_lengthof(GPR); const unsigned NumFPRs = 13; @@ -4887,8 +5007,9 @@ unsigned AvailableFPRs = NumFPRs; unsigned AvailableVRs = NumVRs; - for (const ISD::OutputArg& Param : Outs) { - if (Param.Flags.isNest()) continue; + for (const ISD::OutputArg &Param : Outs) { + if (Param.Flags.isNest()) + continue; if (CalculateStackSlotUsed(Param.VT, Param.ArgVT, Param.Flags, PtrByteSize, LinkageSize, ParamAreaSize, NumBytes, @@ -4907,8 +5028,8 @@ Function::const_arg_iterator CallerArgIter = CallerFn->arg_begin(); for (; CalleeArgIter != CalleeArgEnd; ++CalleeArgIter, ++CallerArgIter) { - const Value* CalleeArg = *CalleeArgIter; - const Value* CallerArg = &(*CallerArgIter); + const Value *CalleeArg = *CalleeArgIter; + const Value *CallerArg = &(*CallerArgIter); if (CalleeArg == CallerArg) continue; @@ -4928,12 +5049,11 @@ // Returns true if TCO is possible between the callers and callees // calling conventions. -static bool -areCallingConvEligibleForTCO_64SVR4(CallingConv::ID CallerCC, - CallingConv::ID CalleeCC) { +static bool areCallingConvEligibleForTCO_64SVR4(CallingConv::ID CallerCC, + CallingConv::ID CalleeCC) { // Tail calls are possible with fastcc and ccc. - auto isTailCallableCC = [] (CallingConv::ID CC){ - return CC == CallingConv::C || CC == CallingConv::Fast; + auto isTailCallableCC = [](CallingConv::ID CC) { + return CC == CallingConv::C || CC == CallingConv::Fast; }; if (!isTailCallableCC(CallerCC) || !isTailCallableCC(CalleeCC)) return false; @@ -4951,10 +5071,12 @@ const SmallVectorImpl &Ins, SelectionDAG &DAG) const { bool TailCallOpt = getTargetMachine().Options.GuaranteedTailCallOpt; - if (DisableSCO && !TailCallOpt) return false; + if (DisableSCO && !TailCallOpt) + return false; // Variadic argument functions are not supported. - if (isVarArg) return false; + if (isVarArg) + return false; auto &Caller = DAG.getMachineFunction().getFunction(); // Check that the calling conventions are compatible for tco. @@ -4981,7 +5103,7 @@ // void caller1(struct test a, struct test c, struct test *b) { // callee(gTest, b); } // void caller2(struct test *b) { callee(gTest, b); } - if (any_of(Outs, [](const ISD::OutputArg& OA) { return OA.Flags.isByVal(); })) + if (any_of(Outs, [](const ISD::OutputArg &OA) { return OA.Flags.isByVal(); })) return false; // If callee and caller use different calling conventions, we cannot pass @@ -4999,8 +5121,8 @@ // When PC-Relative addressing is used, the concept of the TOC is no longer // applicable so this check is not required. // Check first for indirect calls. - if (!Subtarget.isUsingPCRelativeCalls() && - !isFunctionGlobalAddress(Callee) && !isa(Callee)) + if (!Subtarget.isUsingPCRelativeCalls() && !isFunctionGlobalAddress(Callee) && + !isa(Callee)) return false; // Check if we share the TOC base. @@ -5012,7 +5134,8 @@ if (CalleeCC == CallingConv::Fast && TailCallOpt) return true; - if (DisableSCO) return false; + if (DisableSCO) + return false; // If callee use the same argument list that caller is using, then we can // apply SCO on this case. If it is not, then we need to check if callee needs @@ -5032,12 +5155,9 @@ /// IsEligibleForTailCallOptimization - Check whether the call is eligible /// for tail call optimization. Targets which want to do tail call /// optimization should implement this function. -bool -PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, - CallingConv::ID CalleeCC, - bool isVarArg, - const SmallVectorImpl &Ins, - SelectionDAG& DAG) const { +bool PPCTargetLowering::IsEligibleForTailCallOptimization( + SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, + const SmallVectorImpl &Ins, SelectionDAG &DAG) const { if (!getTargetMachine().Options.GuaranteedTailCallOpt) return false; @@ -5050,8 +5170,9 @@ if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) { // Functions containing by val parameters are not supported. for (unsigned i = 0; i != Ins.size(); i++) { - ISD::ArgFlagsTy Flags = Ins[i].Flags; - if (Flags.isByVal()) return false; + ISD::ArgFlagsTy Flags = Ins[i].Flags; + if (Flags.isByVal()) + return false; } // Non-PIC/GOT tail calls are supported. @@ -5061,8 +5182,8 @@ // At the moment we can only do local tail calls (in same module, hidden // or protected) if we are generating PIC. if (GlobalAddressSDNode *G = dyn_cast(Callee)) - return G->getGlobal()->hasHiddenVisibility() - || G->getGlobal()->hasProtectedVisibility(); + return G->getGlobal()->hasHiddenVisibility() || + G->getGlobal()->hasProtectedVisibility(); } return false; @@ -5072,12 +5193,13 @@ /// 32-bit value is representable in the immediate field of a BxA instruction. static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) { ConstantSDNode *C = dyn_cast(Op); - if (!C) return nullptr; + if (!C) + return nullptr; int Addr = C->getZExtValue(); - if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. + if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero. SignExtend32<26>(Addr) != Addr) - return nullptr; // Top 6 bits have to be sext of immediate. + return nullptr; // Top 6 bits have to be sext of immediate. return DAG .getConstant( @@ -5127,8 +5249,8 @@ bool isPPC64 = Subtarget.isPPC64(); int SlotSize = isPPC64 ? 8 : 4; int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset(); - int NewRetAddr = MF.getFrameInfo().CreateFixedObject(SlotSize, - NewRetAddrLoc, true); + int NewRetAddr = + MF.getFrameInfo().CreateFixedObject(SlotSize, NewRetAddrLoc, true); EVT VT = isPPC64 ? MVT::i64 : MVT::i32; SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, @@ -5139,10 +5261,10 @@ /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate /// the position of the argument. -static void -CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, - SDValue Arg, int SPDiff, unsigned ArgOffset, - SmallVectorImpl& TailCallArguments) { +static void CalculateTailCallArgDest( + SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, SDValue Arg, + int SPDiff, unsigned ArgOffset, + SmallVectorImpl &TailCallArguments) { int Offset = ArgOffset + SPDiff; uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8; int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true); @@ -5207,8 +5329,9 @@ MemOpChains.push_back( DAG.getStore(Chain, dl, Arg, PtrOff, MachinePointerInfo())); // Calculate and remember argument location. - } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, - TailCallArguments); + } else + CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset, + TailCallArguments); } static void @@ -5221,8 +5344,8 @@ SmallVector MemOpChains2; // Do not flag preceding copytoreg stuff together with the following stuff. InFlag = SDValue(); - StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, - MemOpChains2, dl); + StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, MemOpChains2, + dl); if (!MemOpChains2.empty()) Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2); @@ -5270,28 +5393,30 @@ SDValue Val; if (Subtarget.hasSPE() && VA.getLocVT() == MVT::f64) { - SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, - InFlag); + SDValue Lo = + DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); Chain = Lo.getValue(1); InFlag = Lo.getValue(2); VA = RVLocs[++i]; // skip ahead to next loc - SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, - InFlag); + SDValue Hi = + DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); Chain = Hi.getValue(1); InFlag = Hi.getValue(2); if (!Subtarget.isLittleEndian()) - std::swap (Lo, Hi); + std::swap(Lo, Hi); Val = DAG.getNode(PPCISD::BUILD_SPE64, dl, MVT::f64, Lo, Hi); } else { - Val = DAG.getCopyFromReg(Chain, dl, - VA.getLocReg(), VA.getLocVT(), InFlag); + Val = + DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), InFlag); Chain = Val.getValue(1); InFlag = Val.getValue(2); } switch (VA.getLocInfo()) { - default: llvm_unreachable("Unknown loc info!"); - case CCValAssign::Full: break; + default: + llvm_unreachable("Unknown loc info!"); + case CCValAssign::Full: + break; case CCValAssign::AExt: Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val); break; @@ -5559,8 +5684,8 @@ const unsigned Alignment = Subtarget.isPPC64() ? 8 : 4; // One load for the functions entry point address. - SDValue LoadFuncPtr = DAG.getLoad(RegVT, dl, LDChain, Callee, MPI, - Alignment, MMOFlags); + SDValue LoadFuncPtr = + DAG.getLoad(RegVT, dl, LDChain, Callee, MPI, Alignment, MMOFlags); // One for loading the TOC anchor for the module that contains the called // function. @@ -5574,9 +5699,8 @@ SDValue PtrOff = DAG.getIntPtrConstant(EnvPtrOffset, dl); SDValue AddPtr = DAG.getNode(ISD::ADD, dl, RegVT, Callee, PtrOff); SDValue LoadEnvPtr = - DAG.getLoad(RegVT, dl, LDChain, AddPtr, - MPI.getWithOffset(EnvPtrOffset), Alignment, MMOFlags); - + DAG.getLoad(RegVT, dl, LDChain, AddPtr, MPI.getWithOffset(EnvPtrOffset), + Alignment, MMOFlags); // Then copy the newly loaded TOC anchor to the TOC pointer. SDValue TOCVal = DAG.getCopyToReg(Chain, dl, TOCReg, TOCPtr, Glue); @@ -5598,13 +5722,11 @@ prepareIndirectCall(DAG, LoadFuncPtr, Glue, Chain, dl); } -static void -buildCallOperands(SmallVectorImpl &Ops, - PPCTargetLowering::CallFlags CFlags, const SDLoc &dl, - SelectionDAG &DAG, - SmallVector, 8> &RegsToPass, - SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff, - const PPCSubtarget &Subtarget) { +static void buildCallOperands( + SmallVectorImpl &Ops, PPCTargetLowering::CallFlags CFlags, + const SDLoc &dl, SelectionDAG &DAG, + SmallVector, 8> &RegsToPass, SDValue Glue, + SDValue Chain, SDValue &Callee, int SPDiff, const PPCSubtarget &Subtarget) { const bool IsPPC64 = Subtarget.isPPC64(); // MVT for a general purpose register. const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32; @@ -5639,9 +5761,8 @@ // Add the register used for the environment pointer. if (Subtarget.usesFunctionDescriptors() && !CFlags.HasNest) - Ops.push_back(DAG.getRegister(Subtarget.getEnvironmentPointerRegister(), - RegVT)); - + Ops.push_back( + DAG.getRegister(Subtarget.getEnvironmentPointerRegister(), RegVT)); // Add CTR register as callee so a bctr can be emitted later. if (CFlags.IsTailCall) @@ -5662,7 +5783,7 @@ // no way to mark dependencies as implicit here. // We will add the R2/X2 dependency in EmitInstrWithCustomInserter. if ((Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) && - !CFlags.IsPatchPoint && !Subtarget.isUsingPCRelativeCalls()) + !CFlags.IsPatchPoint && !Subtarget.isUsingPCRelativeCalls()) Ops.push_back(DAG.getRegister(Subtarget.getTOCPointerRegister(), RegVT)); // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls @@ -5751,21 +5872,20 @@ DAG, InVals); } -SDValue -PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, - SmallVectorImpl &InVals) const { - SelectionDAG &DAG = CLI.DAG; - SDLoc &dl = CLI.DL; +SDValue PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, + SmallVectorImpl &InVals) const { + SelectionDAG &DAG = CLI.DAG; + SDLoc &dl = CLI.DL; SmallVectorImpl &Outs = CLI.Outs; - SmallVectorImpl &OutVals = CLI.OutVals; - SmallVectorImpl &Ins = CLI.Ins; - SDValue Chain = CLI.Chain; - SDValue Callee = CLI.Callee; - bool &isTailCall = CLI.IsTailCall; - CallingConv::ID CallConv = CLI.CallConv; - bool isVarArg = CLI.IsVarArg; - bool isPatchPoint = CLI.IsPatchPoint; - const CallBase *CB = CLI.CB; + SmallVectorImpl &OutVals = CLI.OutVals; + SmallVectorImpl &Ins = CLI.Ins; + SDValue Chain = CLI.Chain; + SDValue Callee = CLI.Callee; + bool &isTailCall = CLI.IsTailCall; + CallingConv::ID CallConv = CLI.CallConv; + bool isVarArg = CLI.IsVarArg; + bool isPatchPoint = CLI.IsPatchPoint; + const CallBase *CB = CLI.CB; if (isTailCall) { if (Subtarget.useLongCalls() && !(CB && CB->isMustTailCall())) @@ -5842,9 +5962,9 @@ const bool IsVarArg = CFlags.IsVarArg; const bool IsTailCall = CFlags.IsTailCall; - assert((CallConv == CallingConv::C || - CallConv == CallingConv::Cold || - CallConv == CallingConv::Fast) && "Unknown calling convention!"); + assert((CallConv == CallingConv::C || CallConv == CallingConv::Cold || + CallConv == CallingConv::Fast) && + "Unknown calling convention!"); const Align PtrAlign(4); @@ -5885,8 +6005,8 @@ bool Result; if (Outs[i].IsFixed) { - Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, - CCInfo); + Result = + CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); } else { Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, CCInfo); @@ -5895,7 +6015,7 @@ if (Result) { #ifndef NDEBUG errs() << "Call operand #" << i << " has unhandled type " - << EVT(ArgVT).getEVTString() << "\n"; + << EVT(ArgVT).getEVTString() << "\n"; #endif llvm_unreachable(nullptr); } @@ -5948,8 +6068,7 @@ // i - Tracks the index into the list of registers allocated for the call // RealArgIdx - Tracks the index into the list of actual function arguments // j - Tracks the index into the list of byval arguments - for (unsigned i = 0, RealArgIdx = 0, j = 0, e = ArgLocs.size(); - i != e; + for (unsigned i = 0, RealArgIdx = 0, j = 0, e = ArgLocs.size(); i != e; ++i, ++RealArgIdx) { CCValAssign &VA = ArgLocs[i]; SDValue Arg = OutVals[RealArgIdx]; @@ -5973,16 +6092,13 @@ // Create a copy of the argument in the local area of the current // stack frame. - SDValue MemcpyCall = - CreateCopyOfByValArgument(Arg, PtrOff, - CallSeqStart.getNode()->getOperand(0), - Flags, DAG, dl); + SDValue MemcpyCall = CreateCopyOfByValArgument( + Arg, PtrOff, CallSeqStart.getNode()->getOperand(0), Flags, DAG, dl); // This must go outside the CALLSEQ_START..END. - SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, NumBytes, 0, - SDLoc(MemcpyCall)); - DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), - NewCallSeqStart.getNode()); + SDValue NewCallSeqStart = + DAG.getCALLSEQ_START(MemcpyCall, NumBytes, 0, SDLoc(MemcpyCall)); + DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode()); Chain = CallSeqStart = NewCallSeqStart; // Pass the address of the aggregate copy on the stack either in a @@ -6005,12 +6121,12 @@ if (Subtarget.hasSPE() && Arg.getValueType() == MVT::f64) { bool IsLE = Subtarget.isLittleEndian(); SDValue SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg, - DAG.getIntPtrConstant(IsLE ? 0 : 1, dl)); + DAG.getIntPtrConstant(IsLE ? 0 : 1, dl)); RegsToPass.push_back(std::make_pair(VA.getLocReg(), SVal.getValue(0))); SVal = DAG.getNode(PPCISD::EXTRACT_SPE, dl, MVT::i32, Arg, DAG.getIntPtrConstant(IsLE ? 1 : 0, dl)); - RegsToPass.push_back(std::make_pair(ArgLocs[++i].getLocReg(), - SVal.getValue(0))); + RegsToPass.push_back( + std::make_pair(ArgLocs[++i].getLocReg(), SVal.getValue(0))); } else RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); } else { @@ -6049,10 +6165,10 @@ // registers. if (IsVarArg) { SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue); - SDValue Ops[] = { Chain, InFlag }; + SDValue Ops[] = {Chain, InFlag}; - Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET, - dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1)); + Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET, dl, + VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1)); InFlag = Chain.getValue(1); } @@ -6070,15 +6186,13 @@ SDValue PPCTargetLowering::createMemcpyOutsideCallSeq( SDValue Arg, SDValue PtrOff, SDValue CallSeqStart, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) const { - SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, - CallSeqStart.getNode()->getOperand(0), - Flags, DAG, dl); + SDValue MemcpyCall = CreateCopyOfByValArgument( + Arg, PtrOff, CallSeqStart.getNode()->getOperand(0), Flags, DAG, dl); // The MEMCPY must go outside the CALLSEQ_START..END. int64_t FrameSize = CallSeqStart.getConstantOperandVal(1); - SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, FrameSize, 0, - SDLoc(MemcpyCall)); - DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), - NewCallSeqStart.getNode()); + SDValue NewCallSeqStart = + DAG.getCALLSEQ_START(MemcpyCall, FrameSize, 0, SDLoc(MemcpyCall)); + DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode()); return NewCallSeqStart; } @@ -6123,17 +6237,15 @@ unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; static const MCPhysReg GPR[] = { - PPC::X3, PPC::X4, PPC::X5, PPC::X6, - PPC::X7, PPC::X8, PPC::X9, PPC::X10, - }; - static const MCPhysReg VR[] = { - PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, - PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 + PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, }; + static const MCPhysReg VR[] = {PPC::V2, PPC::V3, PPC::V4, PPC::V5, + PPC::V6, PPC::V7, PPC::V8, PPC::V9, + PPC::V10, PPC::V11, PPC::V12, PPC::V13}; const unsigned NumGPRs = array_lengthof(GPR); const unsigned NumFPRs = useSoftFloat() ? 0 : 13; - const unsigned NumVRs = array_lengthof(VR); + const unsigned NumVRs = array_lengthof(VR); // On ELFv2, we can avoid allocating the parameter area if all the arguments // can be passed to the callee in registers. @@ -6146,7 +6258,8 @@ unsigned AvailableVRs = NumVRs; unsigned NumBytesTmp = NumBytes; for (unsigned i = 0; i != NumOps; ++i) { - if (Outs[i].Flags.isNest()) continue; + if (Outs[i].Flags.isNest()) + continue; if (CalculateStackSlotUsed(Outs[i].VT, Outs[i].ArgVT, Outs[i].Flags, PtrByteSize, LinkageSize, ParamAreaSize, NumBytesTmp, AvailableFPRs, AvailableVRs)) @@ -6174,12 +6287,13 @@ if (IsFastCall) { if (Flags.isByVal()) { - NumGPRsUsed += (Flags.getByValSize()+7)/8; + NumGPRsUsed += (Flags.getByValSize() + 7) / 8; if (NumGPRsUsed > NumGPRs) HasParameterArea = true; } else { switch (ArgVT.getSimpleVT().SimpleTy) { - default: llvm_unreachable("Unexpected ValueType for argument!"); + default: + llvm_unreachable("Unexpected ValueType for argument!"); case MVT::i1: case MVT::i32: case MVT::i64: @@ -6217,7 +6331,7 @@ NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize); if (Flags.isInConsecutiveRegsLast()) - NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; + NumBytes = ((NumBytes + PtrByteSize - 1) / PtrByteSize) * PtrByteSize; } unsigned NumBytesActuallyUsed = NumBytes; @@ -6336,8 +6450,8 @@ ComputePtrOff(); // All aggregates smaller than 8 bytes must be passed right-justified. - if (Size==1 || Size==2 || Size==4) { - EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32); + if (Size == 1 || Size == 2 || Size == 4) { + EVT VT = (Size == 1) ? MVT::i8 : ((Size == 2) ? MVT::i16 : MVT::i32); if (GPR_idx != NumGPRs) { SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, MachinePointerInfo(), VT); @@ -6352,26 +6466,24 @@ if (GPR_idx == NumGPRs && Size < 8) { SDValue AddPtr = PtrOff; if (!isLittleEndian) { - SDValue Const = DAG.getConstant(PtrByteSize - Size, dl, - PtrOff.getValueType()); + SDValue Const = + DAG.getConstant(PtrByteSize - Size, dl, PtrOff.getValueType()); AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); } - Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, - CallSeqStart, - Flags, DAG, dl); + Chain = CallSeqStart = createMemcpyOutsideCallSeq( + Arg, AddPtr, CallSeqStart, Flags, DAG, dl); ArgOffset += PtrByteSize; continue; } - // Copy the object to parameter save area if it can not be entirely passed + // Copy the object to parameter save area if it can not be entirely passed // by registers. // FIXME: we only need to copy the parts which need to be passed in // parameter save area. For the parts passed by registers, we don't need // to copy them to the stack although we need to allocate space for them // in parameter save area. if ((NumGPRs - GPR_idx) * PtrByteSize < Size) - Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff, - CallSeqStart, - Flags, DAG, dl); + Chain = CallSeqStart = createMemcpyOutsideCallSeq( + Arg, PtrOff, CallSeqStart, Flags, DAG, dl); // When a register is available, pass a small aggregate right-justified. if (Size < 8 && GPR_idx != NumGPRs) { @@ -6388,9 +6500,8 @@ SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType()); AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); } - Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, - CallSeqStart, - Flags, DAG, dl); + Chain = CallSeqStart = createMemcpyOutsideCallSeq( + Arg, AddPtr, CallSeqStart, Flags, DAG, dl); // Load the slot into the register. SDValue Load = @@ -6405,7 +6516,7 @@ // For aggregates larger than PtrByteSize, copy the pieces of the // object that fit into registers from the parameter save area. - for (unsigned j=0; j | Back chain | ---+ -// | +--------------------------------------------+ | +// | +--------------------------------------------+ | // | | Saved Condition Register | | // | +--------------------------------------------+ | // | | Saved Linkage Register | | @@ -7666,11 +7781,9 @@ Callee, SPDiff, NumBytes, Ins, InVals, CB); } -bool -PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv, - MachineFunction &MF, bool isVarArg, - const SmallVectorImpl &Outs, - LLVMContext &Context) const { +bool PPCTargetLowering::CanLowerReturn( + CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, + const SmallVectorImpl &Outs, LLVMContext &Context) const { SmallVector RVLocs; CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context); return CCInfo.CheckReturn( @@ -7704,8 +7817,10 @@ SDValue Arg = OutVals[RealResIdx]; switch (VA.getLocInfo()) { - default: llvm_unreachable("Unknown loc info!"); - case CCValAssign::Full: break; + default: + llvm_unreachable("Unknown loc info!"); + case CCValAssign::Full: + break; case CCValAssign::AExt: Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); break; @@ -7735,7 +7850,7 @@ RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); } - RetOps[0] = Chain; // Update chain. + RetOps[0] = Chain; // Update chain. // Add the flag if we have it. if (Flag.getNode()) @@ -7804,15 +7919,15 @@ // Find out what the fix offset of the frame pointer save area. int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset(); // Allocate the frame index for frame pointer save area. - RASI = MF.getFrameInfo().CreateFixedObject(isPPC64? 8 : 4, LROffset, false); + RASI = + MF.getFrameInfo().CreateFixedObject(isPPC64 ? 8 : 4, LROffset, false); // Save the result. FI->setReturnAddrSaveIndex(RASI); } return DAG.getFrameIndex(RASI, PtrVT); } -SDValue -PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { +SDValue PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG &DAG) const { MachineFunction &MF = DAG.getMachineFunction(); bool isPPC64 = Subtarget.isPPC64(); EVT PtrVT = getPointerTy(MF.getDataLayout()); @@ -7827,7 +7942,7 @@ // Find out what the fix offset of the frame pointer save area. int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset(); // Allocate the frame index for frame pointer save area. - FPSI = MF.getFrameInfo().CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); + FPSI = MF.getFrameInfo().CreateFixedObject(isPPC64 ? 8 : 4, FPOffset, true); // Save the result. FI->setFramePointerSaveIndex(FPSI); } @@ -7839,17 +7954,17 @@ MachineFunction &MF = DAG.getMachineFunction(); // Get the inputs. SDValue Chain = Op.getOperand(0); - SDValue Size = Op.getOperand(1); + SDValue Size = Op.getOperand(1); SDLoc dl(Op); // Get the correct type for pointers. EVT PtrVT = getPointerTy(DAG.getDataLayout()); // Negate the size. - SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, - DAG.getConstant(0, dl, PtrVT), Size); + SDValue NegSize = + DAG.getNode(ISD::SUB, dl, PtrVT, DAG.getConstant(0, dl, PtrVT), Size); // Construct a node for the frame pointer save index. SDValue FPSIdx = getFramePointerFrameIndex(DAG); - SDValue Ops[3] = { Chain, NegSize, FPSIdx }; + SDValue Ops[3] = {Chain, NegSize, FPSIdx}; SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); if (hasInlineStackProbe(MF)) return DAG.getNode(PPCISD::PROBED_ALLOCA, dl, VTs, Ops); @@ -7857,7 +7972,7 @@ } SDValue PPCTargetLowering::LowerEH_DWARF_CFA(SDValue Op, - SelectionDAG &DAG) const { + SelectionDAG &DAG) const { MachineFunction &MF = DAG.getMachineFunction(); bool isPPC64 = Subtarget.isPPC64(); @@ -7871,23 +7986,22 @@ SelectionDAG &DAG) const { SDLoc DL(Op); return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL, - DAG.getVTList(MVT::i32, MVT::Other), - Op.getOperand(0), Op.getOperand(1)); + DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0), + Op.getOperand(1)); } SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); - return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other, - Op.getOperand(0), Op.getOperand(1)); + return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other, Op.getOperand(0), + Op.getOperand(1)); } SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const { if (Op.getValueType().isVector()) return LowerVectorLoad(Op, DAG); - assert(Op.getValueType() == MVT::i1 && - "Custom lowering only for i1 loads"); + assert(Op.getValueType() == MVT::i1 && "Custom lowering only for i1 loads"); // First, load 8 bits into 32 bits, then truncate to 1 bit. @@ -7903,7 +8017,7 @@ BasePtr, MVT::i8, MMO); SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD); - SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) }; + SDValue Ops[] = {Result, SDValue(NewLD.getNode(), 1)}; return DAG.getMergeValues(Ops, dl); } @@ -7931,8 +8045,7 @@ // FIXME: Remove this once the ANDI glue bug is fixed: SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const { - assert(Op.getValueType() == MVT::i1 && - "Custom lowering only for i1 results"); + assert(Op.getValueType() == MVT::i1 && "Custom lowering only for i1 results"); SDLoc DL(Op); return DAG.getNode(PPCISD::ANDI_rec_1_GT_BIT, DL, MVT::i1, Op.getOperand(0)); @@ -7972,8 +8085,7 @@ SDValue N1 = Op.getOperand(0); EVT SrcVT = N1.getValueType(); unsigned SrcSize = SrcVT.getSizeInBits(); - if (SrcSize > 256 || - !isPowerOf2_32(SrcVT.getVectorNumElements()) || + if (SrcSize > 256 || !isPowerOf2_32(SrcVT.getVectorNumElements()) || !isPowerOf2_32(SrcVT.getVectorElementType().getSizeInBits())) return SDValue(); if (SrcSize == 256 && SrcVT.getVectorNumElements() < 2) @@ -7993,8 +8105,7 @@ DAG.getConstant(0, DL, VecIdxTy)); Op2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SplitVT, N1, DAG.getConstant(SplitNumElts, DL, VecIdxTy)); - } - else { + } else { Op1 = SrcSize == 128 ? N1 : widenVec(DAG, N1, DL, DAG.getUNDEF(SrcVT)); Op2 = DAG.getUNDEF(WideVT); } @@ -8026,11 +8137,11 @@ EVT ResVT = Op.getValueType(); EVT CmpVT = Op.getOperand(0).getValueType(); SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); - SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); + SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); SDLoc dl(Op); - // Without power9-vector, we don't have native instruction for f128 comparison. - // Following transformation to libcall is needed for setcc: + // Without power9-vector, we don't have native instruction for f128 + // comparison. Following transformation to libcall is needed for setcc: // select_cc lhs, rhs, tv, fv, cc -> select_cc (setcc cc, x, y), 0, tv, fv, NE if (!Subtarget.hasP9Vector() && CmpVT == MVT::f128) { SDValue Z = DAG.getSetCC( @@ -8075,34 +8186,35 @@ SDValue Sel1; if (isFloatingPointZero(RHS)) switch (CC) { - default: break; // SETUO etc aren't handled by fsel. + default: + break; // SETUO etc aren't handled by fsel. case ISD::SETNE: std::swap(TV, FV); LLVM_FALLTHROUGH; case ISD::SETEQ: - if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits + if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); - if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits + if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); return DAG.getNode(PPCISD::FSEL, dl, ResVT, DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV); case ISD::SETULT: case ISD::SETLT: - std::swap(TV, FV); // fsel is natively setge, swap operands for setlt + std::swap(TV, FV); // fsel is natively setge, swap operands for setlt LLVM_FALLTHROUGH; case ISD::SETOGE: case ISD::SETGE: - if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits + if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); case ISD::SETUGT: case ISD::SETGT: - std::swap(TV, FV); // fsel is natively setge, swap operands for setlt + std::swap(TV, FV); // fsel is natively setge, swap operands for setlt LLVM_FALLTHROUGH; case ISD::SETOLE: case ISD::SETLE: - if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits + if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); return DAG.getNode(PPCISD::FSEL, dl, ResVT, DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); @@ -8110,41 +8222,42 @@ SDValue Cmp; switch (CC) { - default: break; // SETUO etc aren't handled by fsel. + default: + break; // SETUO etc aren't handled by fsel. case ISD::SETNE: std::swap(TV, FV); LLVM_FALLTHROUGH; case ISD::SETEQ: Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags); - if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits + if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); - if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits + if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1); return DAG.getNode(PPCISD::FSEL, dl, ResVT, DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV); case ISD::SETULT: case ISD::SETLT: Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags); - if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits + if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); case ISD::SETOGE: case ISD::SETGE: Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags); - if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits + if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); case ISD::SETUGT: case ISD::SETGT: Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags); - if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits + if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); case ISD::SETOLE: case ISD::SETLE: Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags); - if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits + if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); } @@ -8201,7 +8314,8 @@ SDValue Conv; unsigned Opc = ISD::DELETED_NODE; switch (Op.getSimpleValueType().SimpleTy) { - default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); + default: + llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); case MVT::i32: Opc = IsSigned ? PPCISD::FCTIWZ : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ); @@ -8245,9 +8359,9 @@ Alignment = Align(4); MachineMemOperand *MMO = MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, Alignment); - SDValue Ops[] = { Chain, Tmp, FIPtr }; - Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl, - DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO); + SDValue Ops[] = {Chain, Tmp, FIPtr}; + Chain = DAG.getMemIntrinsicNode( + PPCISD::STFIWX, dl, DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO); } else Chain = DAG.getStore(Chain, dl, Tmp, FIPtr, MPI, Alignment); @@ -8336,8 +8450,8 @@ getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), SrcVT); EVT DstSetCCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), DstVT); - SDValue Sel = DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT, - Chain, true); + SDValue Sel = + DAG.getSetCC(dl, SetCCVT, Src, Cst, ISD::SETLT, Chain, true); Chain = Sel.getValue(1); SDValue FltOfs = DAG.getSelect( @@ -8425,8 +8539,7 @@ RLI.Ptr = LD->getBasePtr(); if (LD->isIndexed() && !LD->getOffset().isUndef()) { - assert(LD->getAddressingMode() == ISD::PRE_INC && - "Non-pre-inc AM on PPC?"); + assert(LD->getAddressingMode() == ISD::PRE_INC && "Non-pre-inc AM on PPC?"); RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr, LD->getOffset()); } @@ -8447,16 +8560,15 @@ // it and NewResChain, and make users of ResChain now be users of that token // factor. // TODO: Remove and use DAG::makeEquivalentMemoryOrdering() instead. -void PPCTargetLowering::spliceIntoChain(SDValue ResChain, - SDValue NewResChain, +void PPCTargetLowering::spliceIntoChain(SDValue ResChain, SDValue NewResChain, SelectionDAG &DAG) const { if (!ResChain) return; SDLoc dl(NewResChain); - SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, - NewResChain, DAG.getUNDEF(MVT::Other)); + SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, NewResChain, + DAG.getUNDEF(MVT::Other)); assert(TF.getNode() != NewResChain.getNode() && "A new TF really is required here"); @@ -8478,8 +8590,7 @@ if (!Subtarget.hasP9Vector() && MMO->getSize() <= 2) return true; - for (SDNode::use_iterator UI = Origin->use_begin(), - UE = Origin->use_end(); + for (SDNode::use_iterator UI = Origin->use_begin(), UE = Origin->use_end(); UI != UE; ++UI) { // Only look at the users of the loaded value. @@ -8528,8 +8639,7 @@ SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG, const SDLoc &dl) const { - assert((Op.getValueType() == MVT::f32 || - Op.getValueType() == MVT::f64) && + assert((Op.getValueType() == MVT::f32 || Op.getValueType() == MVT::f64) && "Invalid floating point type as target of conversion"); assert(Subtarget.hasFPCVT() && "Int to FP conversions with direct moves require FPCVT"); @@ -8630,8 +8740,7 @@ return DAG.getNode(Opc, dl, Op.getValueType(), Extend); } -SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op, - SelectionDAG &DAG) const { +SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const { SDLoc dl(Op); bool IsSigned = Op.getOpcode() == ISD::SINT_TO_FP || Op.getOpcode() == ISD::STRICT_SINT_TO_FP; @@ -8688,8 +8797,7 @@ // // However, if -enable-unsafe-fp-math is in effect, accept double // rounding to avoid the extra overhead. - if (Op.getValueType() == MVT::f32 && - !Subtarget.hasFPCVT() && + if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT() && !DAG.getTarget().Options.UnsafeFPMath) { // Twiddle input to make sure the low 11 bits are zero. (If this @@ -8698,13 +8806,13 @@ // If any of those low 11 bits were not zero originally, make sure // bit 12 (value 2048) is set instead, so that the final rounding // to single-precision gets the correct result. - SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64, - SINT, DAG.getConstant(2047, dl, MVT::i64)); - Round = DAG.getNode(ISD::ADD, dl, MVT::i64, - Round, DAG.getConstant(2047, dl, MVT::i64)); + SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64, SINT, + DAG.getConstant(2047, dl, MVT::i64)); + Round = DAG.getNode(ISD::ADD, dl, MVT::i64, Round, + DAG.getConstant(2047, dl, MVT::i64)); Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT); - Round = DAG.getNode(ISD::AND, dl, MVT::i64, - Round, DAG.getConstant(-2048, dl, MVT::i64)); + Round = DAG.getNode(ISD::AND, dl, MVT::i64, Round, + DAG.getConstant(-2048, dl, MVT::i64)); // However, we cannot use that value unconditionally: if the magnitude // of the input value is small, the bit-twiddling we did above might @@ -8714,10 +8822,10 @@ // construct a conditional to use the original value if the top 11 // bits are all sign-bit copies, and use the rounded value computed // above otherwise. - SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64, - SINT, DAG.getConstant(53, dl, MVT::i32)); - Cond = DAG.getNode(ISD::ADD, dl, MVT::i64, - Cond, DAG.getConstant(1, dl, MVT::i64)); + SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64, SINT, + DAG.getConstant(53, dl, MVT::i32)); + Cond = DAG.getNode(ISD::ADD, dl, MVT::i64, Cond, + DAG.getConstant(1, dl, MVT::i64)); Cond = DAG.getSetCC( dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::i64), @@ -8737,22 +8845,22 @@ } else if (Subtarget.hasLFIWAX() && canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) { MachineMemOperand *MMO = - MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4, - RLI.Alignment, RLI.AAInfo, RLI.Ranges); - SDValue Ops[] = { RLI.Chain, RLI.Ptr }; + MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4, + RLI.Alignment, RLI.AAInfo, RLI.Ranges); + SDValue Ops[] = {RLI.Chain, RLI.Ptr}; Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl, - DAG.getVTList(MVT::f64, MVT::Other), - Ops, MVT::i32, MMO); + DAG.getVTList(MVT::f64, MVT::Other), Ops, + MVT::i32, MMO); spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG); } else if (Subtarget.hasFPCVT() && canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) { MachineMemOperand *MMO = - MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4, - RLI.Alignment, RLI.AAInfo, RLI.Ranges); - SDValue Ops[] = { RLI.Chain, RLI.Ptr }; + MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4, + RLI.Alignment, RLI.AAInfo, RLI.Ranges); + SDValue Ops[] = {RLI.Chain, RLI.Ptr}; Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl, - DAG.getVTList(MVT::f64, MVT::Other), - Ops, MVT::i32, MMO); + DAG.getVTList(MVT::f64, MVT::Other), Ops, + MVT::i32, MMO); spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG); } else if (((Subtarget.hasLFIWAX() && SINT.getOpcode() == ISD::SIGN_EXTEND) || @@ -8780,13 +8888,13 @@ RLI.Alignment = Align(4); MachineMemOperand *MMO = - MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4, - RLI.Alignment, RLI.AAInfo, RLI.Ranges); - SDValue Ops[] = { RLI.Chain, RLI.Ptr }; - Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ? - PPCISD::LFIWZX : PPCISD::LFIWAX, - dl, DAG.getVTList(MVT::f64, MVT::Other), - Ops, MVT::i32, MMO); + MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4, + RLI.Alignment, RLI.AAInfo, RLI.Ranges); + SDValue Ops[] = {RLI.Chain, RLI.Ptr}; + Bits = DAG.getMemIntrinsicNode( + SINT.getOpcode() == ISD::ZERO_EXTEND ? PPCISD::LFIWZX + : PPCISD::LFIWAX, + dl, DAG.getVTList(MVT::f64, MVT::Other), Ops, MVT::i32, MMO); Chain = Bits.getValue(1); } else Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT); @@ -8841,9 +8949,9 @@ } MachineMemOperand *MMO = - MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4, - RLI.Alignment, RLI.AAInfo, RLI.Ranges); - SDValue Ops[] = { RLI.Chain, RLI.Ptr }; + MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4, + RLI.Alignment, RLI.AAInfo, RLI.Ranges); + SDValue Ops[] = {RLI.Chain, RLI.Ptr}; Ld = DAG.getMemIntrinsicNode(IsSigned ? PPCISD::LFIWAX : PPCISD::LFIWZX, dl, DAG.getVTList(MVT::f64, MVT::Other), Ops, MVT::i32, MMO); @@ -8939,19 +9047,17 @@ } // Transform as necessary - SDValue CWD1 = - DAG.getNode(ISD::AND, dl, MVT::i32, - CWD, DAG.getConstant(3, dl, MVT::i32)); + SDValue CWD1 = DAG.getNode(ISD::AND, dl, MVT::i32, CWD, + DAG.getConstant(3, dl, MVT::i32)); SDValue CWD2 = - DAG.getNode(ISD::SRL, dl, MVT::i32, - DAG.getNode(ISD::AND, dl, MVT::i32, - DAG.getNode(ISD::XOR, dl, MVT::i32, - CWD, DAG.getConstant(3, dl, MVT::i32)), - DAG.getConstant(3, dl, MVT::i32)), - DAG.getConstant(1, dl, MVT::i32)); + DAG.getNode(ISD::SRL, dl, MVT::i32, + DAG.getNode(ISD::AND, dl, MVT::i32, + DAG.getNode(ISD::XOR, dl, MVT::i32, CWD, + DAG.getConstant(3, dl, MVT::i32)), + DAG.getConstant(3, dl, MVT::i32)), + DAG.getConstant(1, dl, MVT::i32)); - SDValue RetVal = - DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); + SDValue RetVal = DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); RetVal = DAG.getNode((VT.getSizeInBits() < 16 ? ISD::TRUNCATE : ISD::ZERO_EXTEND), @@ -8964,8 +9070,7 @@ EVT VT = Op.getValueType(); unsigned BitWidth = VT.getSizeInBits(); SDLoc dl(Op); - assert(Op.getNumOperands() == 3 && - VT == Op.getOperand(1).getValueType() && + assert(Op.getNumOperands() == 3 && VT == Op.getOperand(1).getValueType() && "Unexpected SHL!"); // Expand into a bunch of logical ops. Note that these ops @@ -8979,13 +9084,13 @@ DAG.getConstant(BitWidth, dl, AmtVT), Amt); SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); - SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); + SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, DAG.getConstant(-BitWidth, dl, AmtVT)); SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); - SDValue OutOps[] = { OutLo, OutHi }; + SDValue OutOps[] = {OutLo, OutHi}; return DAG.getMergeValues(OutOps, dl); } @@ -8993,8 +9098,7 @@ EVT VT = Op.getValueType(); SDLoc dl(Op); unsigned BitWidth = VT.getSizeInBits(); - assert(Op.getNumOperands() == 3 && - VT == Op.getOperand(1).getValueType() && + assert(Op.getNumOperands() == 3 && VT == Op.getOperand(1).getValueType() && "Unexpected SRL!"); // Expand into a bunch of logical ops. Note that these ops @@ -9014,7 +9118,7 @@ SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5); SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6); SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt); - SDValue OutOps[] = { OutLo, OutHi }; + SDValue OutOps[] = {OutLo, OutHi}; return DAG.getMergeValues(OutOps, dl); } @@ -9022,8 +9126,7 @@ SDLoc dl(Op); EVT VT = Op.getValueType(); unsigned BitWidth = VT.getSizeInBits(); - assert(Op.getNumOperands() == 3 && - VT == Op.getOperand(1).getValueType() && + assert(Op.getNumOperands() == 3 && VT == Op.getOperand(1).getValueType() && "Unexpected SRA!"); // Expand into a bunch of logical ops, followed by a select_cc. @@ -9041,9 +9144,9 @@ DAG.getConstant(-BitWidth, dl, AmtVT)); SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5); SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt); - SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT), - Tmp4, Tmp6, ISD::SETLE); - SDValue OutOps[] = { OutLo, OutHi }; + SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT), Tmp4, + Tmp6, ISD::SETLE); + SDValue OutOps[] = {OutLo, OutHi}; return DAG.getMergeValues(OutOps, dl); } @@ -9080,11 +9183,10 @@ /// element size of SplatSize. Cast the result to VT. static SDValue getCanonicalConstSplat(uint64_t Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, const SDLoc &dl) { - static const MVT VTys[] = { // canonical VT to use for each size. - MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 - }; + static const MVT VTys[] = {// canonical VT to use for each size. + MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32}; - EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; + EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize - 1]; // For a splat with all ones, turn it to vspltisb 0xFF to canonicalize. if (Val == ((1LLU << (SplatSize * 8)) - 1)) { @@ -9092,7 +9194,7 @@ Val = 0xFF; } - EVT CanonicalVT = VTys[SplatSize-1]; + EVT CanonicalVT = VTys[SplatSize - 1]; // Build a canonical splat for this value. return DAG.getBitcast(ReqVT, DAG.getConstant(Val, dl, CanonicalVT)); @@ -9102,7 +9204,8 @@ /// specified intrinsic ID. static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) { - if (DestVT == MVT::Other) DestVT = Op.getValueType(); + if (DestVT == MVT::Other) + DestVT = Op.getValueType(); return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, DAG.getConstant(IID, dl, MVT::i32), Op); } @@ -9112,7 +9215,8 @@ static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) { - if (DestVT == MVT::Other) DestVT = LHS.getValueType(); + if (DestVT == MVT::Other) + DestVT = LHS.getValueType(); return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, DAG.getConstant(IID, dl, MVT::i32), LHS, RHS); } @@ -9122,7 +9226,8 @@ static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, SDValue Op2, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) { - if (DestVT == MVT::Other) DestVT = Op0.getValueType(); + if (DestVT == MVT::Other) + DestVT = Op0.getValueType(); return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2); } @@ -9158,9 +9263,9 @@ bool HasDirectMove, bool HasP8Vector) { EVT VecVT = V->getValueType(0); - bool RightType = VecVT == MVT::v2f64 || - (HasP8Vector && VecVT == MVT::v4f32) || - (HasDirectMove && (VecVT == MVT::v2i64 || VecVT == MVT::v4i32)); + bool RightType = + VecVT == MVT::v2f64 || (HasP8Vector && VecVT == MVT::v4f32) || + (HasDirectMove && (VecVT == MVT::v2i64 || VecVT == MVT::v4i32)); if (!RightType) return false; @@ -9347,8 +9452,7 @@ uint32_t Hi = (uint32_t)((APSplatBits.getZExtValue() & 0xFFFFFFFF00000000LL) >> 32); - uint32_t Lo = - (uint32_t)(APSplatBits.getZExtValue() & 0xFFFFFFFF); + uint32_t Lo = (uint32_t)(APSplatBits.getZExtValue() & 0xFFFFFFFF); SDValue SplatNode = DAG.getUNDEF(MVT::v2i64); if (!Hi || !Lo) @@ -9356,16 +9460,14 @@ SplatNode = DAG.getTargetConstant(0, dl, MVT::v2i64); if (Hi) - SplatNode = DAG.getNode( - PPCISD::XXSPLTI32DX, dl, MVT::v2i64, SplatNode, - DAG.getTargetConstant(0, dl, MVT::i32), - DAG.getTargetConstant(Hi, dl, MVT::i32)); + SplatNode = DAG.getNode(PPCISD::XXSPLTI32DX, dl, MVT::v2i64, SplatNode, + DAG.getTargetConstant(0, dl, MVT::i32), + DAG.getTargetConstant(Hi, dl, MVT::i32)); if (Lo) - SplatNode = - DAG.getNode(PPCISD::XXSPLTI32DX, dl, MVT::v2i64, SplatNode, - DAG.getTargetConstant(1, dl, MVT::i32), - DAG.getTargetConstant(Lo, dl, MVT::i32)); + SplatNode = DAG.getNode(PPCISD::XXSPLTI32DX, dl, MVT::v2i64, SplatNode, + DAG.getTargetConstant(1, dl, MVT::i32), + DAG.getTargetConstant(Lo, dl, MVT::i32)); return DAG.getBitcast(Op.getValueType(), SplatNode); } @@ -9432,9 +9534,9 @@ if (InputLoad->getNode()->hasNUsesOfValue(NumUsesOfInputLD, 0) && Subtarget.hasVSX()) { SDValue Ops[] = { - LD->getChain(), // Chain - LD->getBasePtr(), // Ptr - DAG.getValueType(Op.getValueType()) // VT + LD->getChain(), // Chain + LD->getBasePtr(), // Ptr + DAG.getValueType(Op.getValueType()) // VT }; SDValue LdSplt = DAG.getMemIntrinsicNode( NewOpcode, dl, DAG.getVTList(Op.getValueType(), MVT::Other), Ops, @@ -9492,8 +9594,8 @@ dl); // If the sign extended value is in the range [-16,15], use VSPLTI[bhw]. - int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >> - (32-SplatBitSize)); + int32_t SextVal = + (int32_t(SplatBits << (32 - SplatBitSize)) >> (32 - SplatBitSize)); if (SextVal >= -16 && SextVal <= 15) return getCanonicalConstSplat(SextVal, SplatSize, Op.getValueType(), DAG, dl); @@ -9512,8 +9614,8 @@ // we convert to a pseudo that will be expanded later into one of // the above forms. SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32); - EVT VT = (SplatSize == 1 ? MVT::v16i8 : - (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32)); + EVT VT = (SplatSize == 1 ? MVT::v16i8 + : (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32)); SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32); SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize); if (VT == Op.getValueType()) @@ -9525,13 +9627,13 @@ // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important // for fneg/fabs. - if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { + if (SplatSize == 4 && SplatBits == (0x7FFFFFFF & ~SplatUndef)) { // Make -1 and vspltisw -1: SDValue OnesV = getCanonicalConstSplat(-1, 4, MVT::v4i32, DAG, dl); // Make the VSLW intrinsic, computing 0x8000_0000. - SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, - OnesV, DAG, dl); + SDValue Res = + BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, OnesV, DAG, dl); // xor by OnesV to invert it. Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); @@ -9540,9 +9642,8 @@ // Check to see if this is a wide variety of vsplti*, binop self cases. static const signed char SplatCsts[] = { - -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, - -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16 - }; + -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, -8, 8, + -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16}; for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) { // Indirect through the SplatCsts array so that we favor 'vsplti -1' for @@ -9551,39 +9652,39 @@ // Figure out what shift amount will be used by altivec if shifted by i in // this splat size. - unsigned TypeShiftAmt = i & (SplatBitSize-1); + unsigned TypeShiftAmt = i & (SplatBitSize - 1); // vsplti + shl self. if (SextVal == (int)((unsigned)i << TypeShiftAmt)) { SDValue Res = getCanonicalConstSplat(i, SplatSize, MVT::Other, DAG, dl); - static const unsigned IIDs[] = { // Intrinsic to use for each size. - Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, - Intrinsic::ppc_altivec_vslw - }; - Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); + static const unsigned IIDs[] = {// Intrinsic to use for each size. + Intrinsic::ppc_altivec_vslb, + Intrinsic::ppc_altivec_vslh, 0, + Intrinsic::ppc_altivec_vslw}; + Res = BuildIntrinsicOp(IIDs[SplatSize - 1], Res, Res, DAG, dl); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); } // vsplti + srl self. if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { SDValue Res = getCanonicalConstSplat(i, SplatSize, MVT::Other, DAG, dl); - static const unsigned IIDs[] = { // Intrinsic to use for each size. - Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, - Intrinsic::ppc_altivec_vsrw - }; - Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); + static const unsigned IIDs[] = {// Intrinsic to use for each size. + Intrinsic::ppc_altivec_vsrb, + Intrinsic::ppc_altivec_vsrh, 0, + Intrinsic::ppc_altivec_vsrw}; + Res = BuildIntrinsicOp(IIDs[SplatSize - 1], Res, Res, DAG, dl); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); } // vsplti + rol self. if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | - ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { + ((unsigned)i >> (SplatBitSize - TypeShiftAmt)))) { SDValue Res = getCanonicalConstSplat(i, SplatSize, MVT::Other, DAG, dl); - static const unsigned IIDs[] = { // Intrinsic to use for each size. - Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, - Intrinsic::ppc_altivec_vrlw - }; - Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl); + static const unsigned IIDs[] = {// Intrinsic to use for each size. + Intrinsic::ppc_altivec_vrlb, + Intrinsic::ppc_altivec_vrlh, 0, + Intrinsic::ppc_altivec_vrlw}; + Res = BuildIntrinsicOp(IIDs[SplatSize - 1], Res, Res, DAG, dl); return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res); } @@ -9616,11 +9717,11 @@ SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) { unsigned OpNum = (PFEntry >> 26) & 0x0F; - unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1); - unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); + unsigned LHSID = (PFEntry >> 13) & ((1 << 13) - 1); + unsigned RHSID = (PFEntry >> 0) & ((1 << 13) - 1); enum { - OP_COPY = 0, // Copy, used for things like to say it is <0,1,2,3> + OP_COPY = 0, // Copy, used for things like to say it is <0,1,2,3> OP_VMRGHW, OP_VMRGLW, OP_VSPLTISW0, @@ -9633,8 +9734,9 @@ }; if (OpNum == OP_COPY) { - if (LHSID == (1*9+2)*9+3) return LHS; - assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!"); + if (LHSID == (1 * 9 + 2) * 9 + 3) + return LHS; + assert(LHSID == ((4 * 9 + 5) * 9 + 6) * 9 + 7 && "Illegal OP_COPY!"); return RHS; } @@ -9644,34 +9746,59 @@ int ShufIdxs[16]; switch (OpNum) { - default: llvm_unreachable("Unknown i32 permute!"); + default: + llvm_unreachable("Unknown i32 permute!"); case OP_VMRGHW: - ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3; - ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19; - ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7; - ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23; + ShufIdxs[0] = 0; + ShufIdxs[1] = 1; + ShufIdxs[2] = 2; + ShufIdxs[3] = 3; + ShufIdxs[4] = 16; + ShufIdxs[5] = 17; + ShufIdxs[6] = 18; + ShufIdxs[7] = 19; + ShufIdxs[8] = 4; + ShufIdxs[9] = 5; + ShufIdxs[10] = 6; + ShufIdxs[11] = 7; + ShufIdxs[12] = 20; + ShufIdxs[13] = 21; + ShufIdxs[14] = 22; + ShufIdxs[15] = 23; break; case OP_VMRGLW: - ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11; - ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27; - ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15; - ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31; + ShufIdxs[0] = 8; + ShufIdxs[1] = 9; + ShufIdxs[2] = 10; + ShufIdxs[3] = 11; + ShufIdxs[4] = 24; + ShufIdxs[5] = 25; + ShufIdxs[6] = 26; + ShufIdxs[7] = 27; + ShufIdxs[8] = 12; + ShufIdxs[9] = 13; + ShufIdxs[10] = 14; + ShufIdxs[11] = 15; + ShufIdxs[12] = 28; + ShufIdxs[13] = 29; + ShufIdxs[14] = 30; + ShufIdxs[15] = 31; break; case OP_VSPLTISW0: for (unsigned i = 0; i != 16; ++i) - ShufIdxs[i] = (i&3)+0; + ShufIdxs[i] = (i & 3) + 0; break; case OP_VSPLTISW1: for (unsigned i = 0; i != 16; ++i) - ShufIdxs[i] = (i&3)+4; + ShufIdxs[i] = (i & 3) + 4; break; case OP_VSPLTISW2: for (unsigned i = 0; i != 16; ++i) - ShufIdxs[i] = (i&3)+8; + ShufIdxs[i] = (i & 3) + 8; break; case OP_VSPLTISW3: for (unsigned i = 0; i != 16; ++i) - ShufIdxs[i] = (i&3)+12; + ShufIdxs[i] = (i & 3) + 12; break; case OP_VSLDOI4: return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl); @@ -9758,7 +9885,8 @@ ShiftElts = 0; Swap = false; } else { - // Only need the last 4-bits for shifts because operands will be swapped if CurrentElement is >= 2^4. + // Only need the last 4-bits for shifts because operands will be swapped + // if CurrentElement is >= 2^4. ShiftElts = IsLE ? LittleEndianShifts[CurrentElement & 0xF] : BigEndianShifts[CurrentElement & 0xF]; Swap = CurrentElement < BytesInVector; @@ -9831,7 +9959,8 @@ // 0, 1, 2, 3, 4, X, 6, 7 // 0, 1, 2, 3, 4, 5, X, 7 // 0, 1, 2, 3, 4, 5, 6, X - // Inserting from V1 into V2 will be similar, except mask range will be [8,15]. + // Inserting from V1 into V2 will be similar, except mask range will be + // [8,15]. bool FoundCandidate = false; // Go through the mask of half-words to find an element that's being moved @@ -10039,7 +10168,7 @@ InputLoad->hasOneUse()) { bool IsFourByte = PPC::isSplatShuffleMask(SVOp, 4); int SplatIdx = - PPC::getSplatIdxForPPCMnemonics(SVOp, IsFourByte ? 4 : 8, DAG); + PPC::getSplatIdxForPPCMnemonics(SVOp, IsFourByte ? 4 : 8, DAG); // The splat index for permuted loads will be in the left half of the vector // which is strictly wider than the loaded value by 8 bytes. So we need to @@ -10071,15 +10200,15 @@ BasePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()), BasePtr, DAG.getIntPtrConstant(Offset, dl)); SDValue Ops[] = { - LD->getChain(), // Chain - BasePtr, // BasePtr - DAG.getValueType(Op.getValueType()) // VT + LD->getChain(), // Chain + BasePtr, // BasePtr + DAG.getValueType(Op.getValueType()) // VT }; SDVTList VTL = - DAG.getVTList(IsFourByte ? MVT::v4i32 : MVT::v2i64, MVT::Other); + DAG.getVTList(IsFourByte ? MVT::v4i32 : MVT::v2i64, MVT::Other); SDValue LdSplt = - DAG.getMemIntrinsicNode(PPCISD::LD_SPLAT, dl, VTL, - Ops, LD->getMemoryVT(), LD->getMemOperand()); + DAG.getMemIntrinsicNode(PPCISD::LD_SPLAT, dl, VTL, Ops, + LD->getMemoryVT(), LD->getMemOperand()); DAG.ReplaceAllUsesOfValueWith(InputLoad->getValue(1), LdSplt.getValue(1)); if (LdSplt.getValueType() != SVOp->getValueType(0)) LdSplt = DAG.getBitcast(SVOp->getValueType(0), LdSplt); @@ -10139,7 +10268,7 @@ } if (Subtarget.hasVSX() && - PPC::isXXPERMDIShuffleMask(SVOp, ShiftElts, Swap, isLittleEndian)) { + PPC::isXXPERMDIShuffleMask(SVOp, ShiftElts, Swap, isLittleEndian)) { if (Swap) std::swap(V1, V2); SDValue Conv1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1); @@ -10147,12 +10276,12 @@ DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2.isUndef() ? V1 : V2); SDValue PermDI = DAG.getNode(PPCISD::XXPERMDI, dl, MVT::v2i64, Conv1, Conv2, - DAG.getConstant(ShiftElts, dl, MVT::i32)); + DAG.getConstant(ShiftElts, dl, MVT::i32)); return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, PermDI); } if (Subtarget.hasP9Vector()) { - if (PPC::isXXBRHShuffleMask(SVOp)) { + if (PPC::isXXBRHShuffleMask(SVOp)) { SDValue Conv = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); SDValue ReveHWord = DAG.getNode(ISD::BSWAP, dl, MVT::v8i16, Conv); return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, ReveHWord); @@ -10193,8 +10322,7 @@ // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be // selected by the instruction selector. if (V2.isUndef()) { - if (PPC::isSplatShuffleMask(SVOp, 1) || - PPC::isSplatShuffleMask(SVOp, 2) || + if (PPC::isSplatShuffleMask(SVOp, 1) || PPC::isSplatShuffleMask(SVOp, 2) || PPC::isSplatShuffleMask(SVOp, 4) || PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) || PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) || @@ -10205,10 +10333,10 @@ PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) || PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) || PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) || - (Subtarget.hasP8Altivec() && ( - PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) || - PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) || - PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)))) { + (Subtarget.hasP8Altivec() && + (PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) || + PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) || + PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)))) { return Op; } } @@ -10226,10 +10354,10 @@ PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) || PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) || PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) || - (Subtarget.hasP8Altivec() && ( - PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) || - PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) || - PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG)))) + (Subtarget.hasP8Altivec() && + (PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) || + PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) || + PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG)))) return Op; // Check to see if this is a shuffle of 4-byte values. If so, we can use our @@ -10293,7 +10421,8 @@ // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant // vector that will get spilled to the constant pool. - if (V2.isUndef()) V2 = V1; + if (V2.isUndef()) + V2 = V1; // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except // that it is in input element units, not in bytes. Convert now. @@ -10303,7 +10432,7 @@ // necessary to produce proper semantics with the big-endian-biased vperm // instruction. EVT EltVT = V1.getValueType().getVectorElementType(); - unsigned BytesPerElement = EltVT.getSizeInBits()/8; + unsigned BytesPerElement = EltVT.getSizeInBits() / 8; SmallVector ResultMask; for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) { @@ -10311,11 +10440,11 @@ for (unsigned j = 0; j != BytesPerElement; ++j) if (isLittleEndian) - ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement + j), - dl, MVT::i32)); + ResultMask.push_back( + DAG.getConstant(31 - (SrcElt * BytesPerElement + j), dl, MVT::i32)); else - ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement + j, dl, - MVT::i32)); + ResultMask.push_back( + DAG.getConstant(SrcElt * BytesPerElement + j, dl, MVT::i32)); } ShufflesHandledWithVPERM++; @@ -10326,18 +10455,16 @@ LLVM_DEBUG(VPermMask.dump()); if (isLittleEndian) - return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), - V2, V1, VPermMask); + return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V2, V1, VPermMask); else - return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), - V1, V2, VPermMask); + return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); } /// getVectorCompareInfo - Given an intrinsic, return false if it is not a /// vector comparison. If it is, return true and fill in Opc/isDot with /// information about the intrinsic. -static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc, - bool &isDot, const PPCSubtarget &Subtarget) { +static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc, bool &isDot, + const PPCSubtarget &Subtarget) { unsigned IntrinsicID = cast(Intrin.getOperand(0))->getZExtValue(); CompareOpc = -1; @@ -10881,10 +11008,10 @@ } // end switch(type). } // end case reduce. case Intrinsic::ppc_vector_absdu: { - SDValue V1 = fitVectorToRegSize(DAG, Op.getOperand(1), dl, - DAG.getUNDEF(OpTy)); - SDValue V2 = fitVectorToRegSize(DAG, Op.getOperand(2), dl, - DAG.getUNDEF(OpTy)); + SDValue V1 = + fitVectorToRegSize(DAG, Op.getOperand(1), dl, DAG.getUNDEF(OpTy)); + SDValue V2 = + fitVectorToRegSize(DAG, Op.getOperand(2), dl, DAG.getUNDEF(OpTy)); if (Subtarget.hasP9Vector()) return DAG.getNode(PPCISD::VABSDU, dl, OpTy, V1, V2); @@ -10895,20 +11022,19 @@ } case Intrinsic::ppc_vector_avgu: case Intrinsic::ppc_vector_avgs: { - SDValue V1 = fitVectorToRegSize(DAG, Op.getOperand(1), dl, - DAG.getUNDEF(OpTy)); - SDValue V2 = fitVectorToRegSize(DAG, Op.getOperand(2), dl, - DAG.getUNDEF(OpTy)); + SDValue V1 = + fitVectorToRegSize(DAG, Op.getOperand(1), dl, DAG.getUNDEF(OpTy)); + SDValue V2 = + fitVectorToRegSize(DAG, Op.getOperand(2), dl, DAG.getUNDEF(OpTy)); if (Subtarget.hasAltivec()) return DAG.getNode(getStandardVectorOp(IntrinsicID), dl, V1.getValueType(), V1, V2); // Expand to ((A + 1) + B) >> 1) - SDValue LhsPlusOne = - DAG.getNode(ISD::ADD, dl, V1.getValueType(), V1, - DAG.getConstant(1, dl, V1.getValueType())); + SDValue LhsPlusOne = DAG.getNode(ISD::ADD, dl, V1.getValueType(), V1, + DAG.getConstant(1, dl, V1.getValueType())); SDValue Sum = - DAG.getNode(ISD::ADD, dl, LhsPlusOne.getValueType(), LhsPlusOne, V2); + DAG.getNode(ISD::ADD, dl, LhsPlusOne.getValueType(), LhsPlusOne, V2); return DAG.getNode(ISD::SRL, dl, Sum.getValueType(), Sum, DAG.getConstant(1, dl, Sum.getValueType())); } @@ -10936,9 +11062,9 @@ auto *Idx = dyn_cast(Op.getOperand(2)); assert(Idx && (Idx->getSExtValue() == 0 || Idx->getSExtValue() == 1) && "Argument of long double unpack must be 0 or 1!"); - return DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::f64, Op.getOperand(1), - DAG.getConstant(!!(Idx->getSExtValue()), dl, - Idx->getValueType(0))); + return DAG.getNode( + ISD::EXTRACT_ELEMENT, dl, MVT::f64, Op.getOperand(1), + DAG.getConstant(!!(Idx->getSExtValue()), dl, Idx->getValueType(0))); } case Intrinsic::ppc_compare_exp_lt: @@ -11038,7 +11164,7 @@ int CompareOpc; bool isDot; if (!getVectorCompareInfo(Op, CompareOpc, isDot, Subtarget)) - return SDValue(); // Don't custom lower most intrinsics. + return SDValue(); // Don't custom lower most intrinsics. // If this is a non-dot comparison, make the VCMP node and we are done. if (!isDot) { @@ -11049,36 +11175,38 @@ } // Create the PPCISD altivec 'dot' comparison node. - SDValue Ops[] = { - Op.getOperand(2), // LHS - Op.getOperand(3), // RHS - DAG.getConstant(CompareOpc, dl, MVT::i32) - }; - EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue }; + SDValue Ops[] = {Op.getOperand(2), // LHS + Op.getOperand(3), // RHS + DAG.getConstant(CompareOpc, dl, MVT::i32)}; + EVT VTs[] = {Op.getOperand(2).getValueType(), MVT::Glue}; SDValue CompNode = DAG.getNode(PPCISD::VCMP_rec, dl, VTs, Ops); // Now that we have the comparison, emit a copy from the CR to a GPR. // This is flagged to the above dot comparison. - SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32, - DAG.getRegister(PPC::CR6, MVT::i32), - CompNode.getValue(1)); + SDValue Flags = + DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32, + DAG.getRegister(PPC::CR6, MVT::i32), CompNode.getValue(1)); // Unpack the result based on how the target uses it. - unsigned BitNo; // Bit # of CR6. - bool InvertBit; // Invert result? + unsigned BitNo; // Bit # of CR6. + bool InvertBit; // Invert result? switch (cast(Op.getOperand(1))->getZExtValue()) { - default: // Can't happen, don't crash on invalid number though. - case 0: // Return the value of the EQ bit of CR6. - BitNo = 0; InvertBit = false; + default: // Can't happen, don't crash on invalid number though. + case 0: // Return the value of the EQ bit of CR6. + BitNo = 0; + InvertBit = false; break; - case 1: // Return the inverted value of the EQ bit of CR6. - BitNo = 0; InvertBit = true; + case 1: // Return the inverted value of the EQ bit of CR6. + BitNo = 0; + InvertBit = true; break; - case 2: // Return the value of the LT bit of CR6. - BitNo = 2; InvertBit = false; + case 2: // Return the value of the LT bit of CR6. + BitNo = 2; + InvertBit = false; break; - case 3: // Return the inverted value of the LT bit of CR6. - BitNo = 2; InvertBit = true; + case 3: // Return the inverted value of the LT bit of CR6. + BitNo = 2; + InvertBit = true; break; } @@ -11127,6 +11255,72 @@ } break; } + case Intrinsic::ppc_kill_canary: { + MachineFunction &MF = DAG.getMachineFunction(); + const Module *M = MF.getMMI().getModule(); + + /* If SafeStack or !StackProtector, kill_canary not supported */ + if (MF.getFunction().hasFnAttribute(Attribute::SafeStack) || + !MF.getFunction().hasStackProtectorFnAttr()) { + DAG.ReplaceAllUsesOfValueWith( + SDValue(Op.getNode(), 0), + Op->getOperand(0)); // prepare node for deletion + break; + } + + EVT VT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout()); + + SDValue Load; + SDValue Store; + + const uint64_t XORWord = + 0xFFFFFFFFFFFFFFFF; // XORing with 0b111...111 will never + // result in the original word + + if (useLoadStackGuardNode()) { // linux uses LOAD_STACK_GUARD node instead + // of having a canary word global value + MachineSDNode *LSG = + DAG.getMachineNode(PPC::LOAD_STACK_GUARD, DL, VT, Op->getOperand(0)); + Load = SDValue(LSG, 0); + + /* frame index used to determine stack guard location if + * LOAD_STACK_GUARD is used */ + MachineFrameInfo &MFI = MF.getFrameInfo(); + int SPI = MFI.getStackProtectorIndex(); // should return -1 + PPCFunctionInfo *FuncInfo = MF.getInfo(); + SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), VT); + + // XOR canary word and store back + Store = DAG.getStore( + Op->getOperand(0), DL, + DAG.getNode(ISD::XOR, DL, VT, Load, DAG.getConstant(XORWord, DL, VT)), + DAG.getNode( // add frame index, stack protector index, return node + // result + ISD::ADD, DL, VT, FIN, DAG.getConstant(SPI, DL, VT)), + MachinePointerInfo()); + + } else if (Value *GV = + getSDagStackGuard(*M)) { // on aix, load from global value + VT = DAG.getTargetLoweringInfo().getValueType(DAG.getDataLayout(), + GV->getType(), true); + SDValue CanaryLoc = + DAG.getGlobalAddress(dyn_cast(GV), DL, VT); + + // Load from global value + Load = DAG.getLoad(VT, DL, Op->getOperand(0), CanaryLoc, + MachinePointerInfo()); + + // XOR canary word and store back + Store = DAG.getStore( + Op->getOperand(0), DL, + DAG.getNode(ISD::XOR, DL, VT, Load, DAG.getConstant(XORWord, DL, VT)), + CanaryLoc, MachinePointerInfo()); + } else { + llvm_unreachable("Unhandled stack guard case"); + } + + return Store; + } default: break; } @@ -11172,9 +11366,8 @@ // Clear the high bits of the compare operand. unsigned MaskVal = (1 << MemVT.getSizeInBits()) - 1; - SDValue NewCmpOp = - DAG.getNode(ISD::AND, dl, MVT::i32, CmpOp, - DAG.getConstant(MaskVal, dl, MVT::i32)); + SDValue NewCmpOp = DAG.getNode(ISD::AND, dl, MVT::i32, CmpOp, + DAG.getConstant(MaskVal, dl, MVT::i32)); // Replace the existing compare operand with the properly zero-extended one. SmallVector Ops; @@ -11183,8 +11376,8 @@ Ops[2] = NewCmpOp; MachineMemOperand *MMO = AtomicNode->getMemOperand(); SDVTList Tys = DAG.getVTList(MVT::i32, MVT::Other); - auto NodeTy = - (MemVT == MVT::i8) ? PPCISD::ATOMIC_CMP_SWAP_8 : PPCISD::ATOMIC_CMP_SWAP_16; + auto NodeTy = (MemVT == MVT::i8) ? PPCISD::ATOMIC_CMP_SWAP_8 + : PPCISD::ATOMIC_CMP_SWAP_16; return DAG.getMemIntrinsicNode(NodeTy, dl, Tys, Ops, MemVT, MMO); } @@ -11201,8 +11394,7 @@ // The input to STXVL is the number of bytes to store, where as the input // length of VARLEN_STORE is the number of elements. Here we calculate the // number of bytes based on input vector type and length. - unsigned EltBytes = - Op.getOperand(1).getValueType().getScalarSizeInBits() / 8; + unsigned EltBytes = Op.getOperand(1).getValueType().getScalarSizeInBits() / 8; SDValue ExtLength = DAG.getZExtOrTrunc(Length, DL, MVT::i64); SDValue ShiftedLength = DAG.getNode(ISD::SHL, DL, MVT::i64, ExtLength, @@ -11490,8 +11682,9 @@ } for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { unsigned VecNum = Subtarget.isLittleEndian() ? NumVecs - 1 - Idx : Idx; - SDValue Elt = DAG.getNode(PPCISD::EXTRACT_VSX_REG, dl, MVT::v16i8, Value, - DAG.getConstant(VecNum, dl, getPointerTy(DAG.getDataLayout()))); + SDValue Elt = DAG.getNode( + PPCISD::EXTRACT_VSX_REG, dl, MVT::v16i8, Value, + DAG.getConstant(VecNum, dl, getPointerTy(DAG.getDataLayout()))); SDValue Store = DAG.getStore(StoreChain, dl, Elt, BasePtr, SN->getPointerInfo().getWithOffset(Idx * 16), @@ -11513,8 +11706,8 @@ SDValue Zero = getCanonicalConstSplat(0, 1, MVT::v4i32, DAG, dl); // +16 as shift amt. SDValue Neg16 = getCanonicalConstSplat(-16, 4, MVT::v4i32, DAG, dl); - SDValue RHSSwap = // = vrlw RHS, 16 - BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); + SDValue RHSSwap = // = vrlw RHS, 16 + BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); // Shrinkify inputs to v8i16. LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS); @@ -11523,27 +11716,27 @@ // Low parts multiplied together, generating 32-bit results (we ignore the // top parts). - SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, - LHS, RHS, DAG, dl, MVT::v4i32); + SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, LHS, RHS, + DAG, dl, MVT::v4i32); - SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, - LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); + SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, LHS, + RHSSwap, Zero, DAG, dl, MVT::v4i32); // Shift the high parts up 16 bits. - HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, - Neg16, DAG, dl); + HiProd = + BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG, dl); return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); } else if (Op.getValueType() == MVT::v16i8) { SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); bool isLittleEndian = Subtarget.isLittleEndian(); // Multiply the even 8-bit parts, producing 16-bit sums. - SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, - LHS, RHS, DAG, dl, MVT::v8i16); + SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, LHS, + RHS, DAG, dl, MVT::v8i16); EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts); // Multiply the odd 8-bit parts, producing 16-bit sums. - SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, - LHS, RHS, DAG, dl, MVT::v8i16); + SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, LHS, + RHS, DAG, dl, MVT::v8i16); OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts); // Merge the results together. Because vmuleub and vmuloub are @@ -11553,11 +11746,11 @@ int Ops[16]; for (unsigned i = 0; i != 8; ++i) { if (isLittleEndian) { - Ops[i*2 ] = 2*i; - Ops[i*2+1] = 2*i+16; + Ops[i * 2] = 2 * i; + Ops[i * 2 + 1] = 2 * i + 16; } else { - Ops[i*2 ] = 2*i+1; - Ops[i*2+1] = 2*i+1+16; + Ops[i * 2] = 2 * i + 1; + Ops[i * 2 + 1] = 2 * i + 1 + 16; } } if (isLittleEndian) @@ -11581,8 +11774,7 @@ // Currently only handles 4-word sum into single word SDValue InitialVec = DAG.getConstant(0, DL, MVT::v4i32); SDValue Rdx = DAG.getNode(PPCISD::VSUM_TO_SCALAR, DL, - VecOp.getSimpleValueType(), - VecOp, InitialVec); + VecOp.getSimpleValueType(), VecOp, InitialVec); return DAG.getNode( ISD::EXTRACT_VECTOR_ELT, DL, ScalarOp.getValueType(), Rdx, DAG.getConstant(ElemToExtract, DL, getPointerTy(DAG.getDataLayout()))); @@ -11678,85 +11870,134 @@ /// SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { - default: llvm_unreachable("Wasn't expecting to be able to lower this!"); - case ISD::FPOW: return lowerPow(Op, DAG); - case ISD::FSIN: return lowerSin(Op, DAG); - case ISD::FCOS: return lowerCos(Op, DAG); - case ISD::FLOG: return lowerLog(Op, DAG); - case ISD::FLOG10: return lowerLog10(Op, DAG); - case ISD::FEXP: return lowerExp(Op, DAG); - case ISD::ConstantPool: return LowerConstantPool(Op, DAG); - case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); - case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); - case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); - case ISD::JumpTable: return LowerJumpTable(Op, DAG); + default: + llvm_unreachable("Wasn't expecting to be able to lower this!"); + case ISD::FPOW: + return lowerPow(Op, DAG); + case ISD::FSIN: + return lowerSin(Op, DAG); + case ISD::FCOS: + return lowerCos(Op, DAG); + case ISD::FLOG: + return lowerLog(Op, DAG); + case ISD::FLOG10: + return lowerLog10(Op, DAG); + case ISD::FEXP: + return lowerExp(Op, DAG); + case ISD::ConstantPool: + return LowerConstantPool(Op, DAG); + case ISD::BlockAddress: + return LowerBlockAddress(Op, DAG); + case ISD::GlobalAddress: + return LowerGlobalAddress(Op, DAG); + case ISD::GlobalTLSAddress: + return LowerGlobalTLSAddress(Op, DAG); + case ISD::JumpTable: + return LowerJumpTable(Op, DAG); case ISD::STRICT_FSETCC: case ISD::STRICT_FSETCCS: - case ISD::SETCC: return LowerSETCC(Op, DAG); - case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); - case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); + case ISD::SETCC: + return LowerSETCC(Op, DAG); + case ISD::INIT_TRAMPOLINE: + return LowerINIT_TRAMPOLINE(Op, DAG); + case ISD::ADJUST_TRAMPOLINE: + return LowerADJUST_TRAMPOLINE(Op, DAG); case ISD::INLINEASM: - case ISD::INLINEASM_BR: return LowerINLINEASM(Op, DAG); + case ISD::INLINEASM_BR: + return LowerINLINEASM(Op, DAG); // Variable argument lowering. - case ISD::VASTART: return LowerVASTART(Op, DAG); - case ISD::VAARG: return LowerVAARG(Op, DAG); - case ISD::VACOPY: return LowerVACOPY(Op, DAG); - - case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG); - case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); + case ISD::VASTART: + return LowerVASTART(Op, DAG); + case ISD::VAARG: + return LowerVAARG(Op, DAG); + case ISD::VACOPY: + return LowerVACOPY(Op, DAG); + + case ISD::STACKRESTORE: + return LowerSTACKRESTORE(Op, DAG); + case ISD::DYNAMIC_STACKALLOC: + return LowerDYNAMIC_STACKALLOC(Op, DAG); case ISD::GET_DYNAMIC_AREA_OFFSET: return LowerGET_DYNAMIC_AREA_OFFSET(Op, DAG); // Exception handling lowering. - case ISD::EH_DWARF_CFA: return LowerEH_DWARF_CFA(Op, DAG); - case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG); - case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG); - - case ISD::LOAD: return LowerLOAD(Op, DAG); - case ISD::STORE: return LowerSTORE(Op, DAG); - case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG); - case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); + case ISD::EH_DWARF_CFA: + return LowerEH_DWARF_CFA(Op, DAG); + case ISD::EH_SJLJ_SETJMP: + return lowerEH_SJLJ_SETJMP(Op, DAG); + case ISD::EH_SJLJ_LONGJMP: + return lowerEH_SJLJ_LONGJMP(Op, DAG); + + case ISD::LOAD: + return LowerLOAD(Op, DAG); + case ISD::STORE: + return LowerSTORE(Op, DAG); + case ISD::TRUNCATE: + return LowerTRUNCATE(Op, DAG); + case ISD::SELECT_CC: + return LowerSELECT_CC(Op, DAG); case ISD::STRICT_FP_TO_UINT: case ISD::STRICT_FP_TO_SINT: case ISD::FP_TO_UINT: - case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG, SDLoc(Op)); + case ISD::FP_TO_SINT: + return LowerFP_TO_INT(Op, DAG, SDLoc(Op)); case ISD::STRICT_UINT_TO_FP: case ISD::STRICT_SINT_TO_FP: case ISD::UINT_TO_FP: - case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG); - case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); + case ISD::SINT_TO_FP: + return LowerINT_TO_FP(Op, DAG); + case ISD::FLT_ROUNDS_: + return LowerFLT_ROUNDS_(Op, DAG); // Lower 64-bit shifts. - case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG); - case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG); - case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG); + case ISD::SHL_PARTS: + return LowerSHL_PARTS(Op, DAG); + case ISD::SRL_PARTS: + return LowerSRL_PARTS(Op, DAG); + case ISD::SRA_PARTS: + return LowerSRA_PARTS(Op, DAG); - case ISD::FSHL: return LowerFunnelShift(Op, DAG); - case ISD::FSHR: return LowerFunnelShift(Op, DAG); + case ISD::FSHL: + return LowerFunnelShift(Op, DAG); + case ISD::FSHR: + return LowerFunnelShift(Op, DAG); // Vector-related lowering. - case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); - case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); - case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); - case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); - case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); - case ISD::MUL: return LowerMUL(Op, DAG); - case ISD::VECREDUCE_ADD: return LowerVECREDUCE(Op,DAG); - case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG); + case ISD::BUILD_VECTOR: + return LowerBUILD_VECTOR(Op, DAG); + case ISD::VECTOR_SHUFFLE: + return LowerVECTOR_SHUFFLE(Op, DAG); + case ISD::INTRINSIC_WO_CHAIN: + return LowerINTRINSIC_WO_CHAIN(Op, DAG); + case ISD::SCALAR_TO_VECTOR: + return LowerSCALAR_TO_VECTOR(Op, DAG); + case ISD::INSERT_VECTOR_ELT: + return LowerINSERT_VECTOR_ELT(Op, DAG); + case ISD::MUL: + return LowerMUL(Op, DAG); + case ISD::VECREDUCE_ADD: + return LowerVECREDUCE(Op, DAG); + case ISD::FP_EXTEND: + return LowerFP_EXTEND(Op, DAG); case ISD::STRICT_FP_ROUND: case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG); - case ISD::ROTL: return LowerROTL(Op, DAG); + case ISD::ROTL: + return LowerROTL(Op, DAG); // For counter-based loop handling. - case ISD::INTRINSIC_W_CHAIN: return SDValue(); + case ISD::INTRINSIC_W_CHAIN: + return SDValue(); - case ISD::BITCAST: return LowerBITCAST(Op, DAG); + case ISD::BITCAST: + return LowerBITCAST(Op, DAG); // Frame & Return address. - case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); - case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); + case ISD::RETURNADDR: + return LowerRETURNADDR(Op, DAG); + case ISD::FRAMEADDR: + return LowerFRAMEADDR(Op, DAG); case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG); @@ -11788,7 +12029,8 @@ } case ISD::READCYCLECOUNTER: { SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); - SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0)); + SDValue RTB = + DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0)); Results.push_back( DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, RTB, RTB.getValue(1))); @@ -11930,12 +12172,9 @@ return nullptr; } -MachineBasicBlock * -PPCTargetLowering::EmitAtomicBinary(MachineInstr &MI, MachineBasicBlock *BB, - unsigned AtomicSize, - unsigned BinOpcode, - unsigned CmpOpcode, - unsigned CmpPred) const { +MachineBasicBlock *PPCTargetLowering::EmitAtomicBinary( + MachineInstr &MI, MachineBasicBlock *BB, unsigned AtomicSize, + unsigned BinOpcode, unsigned CmpOpcode, unsigned CmpPred) const { // This also handles ATOMIC_SWAP, indicated by BinOpcode==0. const TargetInstrInfo *TII = Subtarget.getInstrInfo(); @@ -11976,7 +12215,7 @@ MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB); MachineBasicBlock *loop2MBB = - CmpOpcode ? F->CreateMachineBasicBlock(LLVM_BB) : nullptr; + CmpOpcode ? F->CreateMachineBasicBlock(LLVM_BB) : nullptr; MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB); F->insert(It, loopMBB); if (CmpOpcode) @@ -11987,9 +12226,11 @@ exitMBB->transferSuccessorsAndUpdatePHIs(BB); MachineRegisterInfo &RegInfo = F->getRegInfo(); - Register TmpReg = (!BinOpcode) ? incr : - RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass - : &PPC::GPRCRegClass); + Register TmpReg = + (!BinOpcode) + ? incr + : RegInfo.createVirtualRegister(AtomicSize == 8 ? &PPC::G8RCRegClass + : &PPC::GPRCRegClass); // thisMBB: // ... @@ -12014,8 +12255,7 @@ // fallthrough --> exitMBB BB = loopMBB; - BuildMI(BB, dl, TII->get(LoadMnemonic), dest) - .addReg(ptrA).addReg(ptrB); + BuildMI(BB, dl, TII->get(LoadMnemonic), dest).addReg(ptrA).addReg(ptrB); if (BinOpcode) BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest); if (CmpOpcode) { @@ -12023,23 +12263,30 @@ if (CmpOpcode == PPC::CMPW && AtomicSize < 4) { Register ExtReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); BuildMI(BB, dl, TII->get(AtomicSize == 1 ? PPC::EXTSB : PPC::EXTSH), - ExtReg).addReg(dest); + ExtReg) + .addReg(dest); BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0) - .addReg(incr).addReg(ExtReg); + .addReg(incr) + .addReg(ExtReg); } else - BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0) - .addReg(incr).addReg(dest); + BuildMI(BB, dl, TII->get(CmpOpcode), PPC::CR0).addReg(incr).addReg(dest); BuildMI(BB, dl, TII->get(PPC::BCC)) - .addImm(CmpPred).addReg(PPC::CR0).addMBB(exitMBB); + .addImm(CmpPred) + .addReg(PPC::CR0) + .addMBB(exitMBB); BB->addSuccessor(loop2MBB); BB->addSuccessor(exitMBB); BB = loop2MBB; } BuildMI(BB, dl, TII->get(StoreMnemonic)) - .addReg(TmpReg).addReg(ptrA).addReg(ptrB); + .addReg(TmpReg) + .addReg(ptrA) + .addReg(ptrB); BuildMI(BB, dl, TII->get(PPC::BCC)) - .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB); + .addImm(PPC::PRED_NE) + .addReg(PPC::CR0) + .addMBB(loopMBB); BB->addSuccessor(loopMBB); BB->addSuccessor(exitMBB); @@ -12050,7 +12297,7 @@ } static bool isSignExtended(MachineInstr &MI, const PPCInstrInfo *TII) { - switch(MI.getOpcode()) { + switch (MI.getOpcode()) { default: return false; case PPC::COPY: @@ -12118,7 +12365,7 @@ MachineRegisterInfo &RegInfo = F->getRegInfo(); Register incr = MI.getOperand(3).getReg(); bool IsSignExtended = Register::isVirtualRegister(incr) && - isSignExtended(*RegInfo.getVRegDef(incr), TII); + isSignExtended(*RegInfo.getVRegDef(incr), TII); if (CmpOpcode == PPC::CMPW && !IsSignExtended) { Register ValueReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); @@ -12338,8 +12585,7 @@ Register restoreDstReg = MRI.createVirtualRegister(RC); MVT PVT = getPointerTy(MF->getDataLayout()); - assert((PVT == MVT::i64 || PVT == MVT::i32) && - "Invalid Pointer Size!"); + assert((PVT == MVT::i64 || PVT == MVT::i32) && "Invalid Pointer Size!"); // For v = setjmp(buf), we generate // // thisMBB: @@ -12382,8 +12628,8 @@ // thisMBB: const int64_t LabelOffset = 1 * PVT.getStoreSize(); - const int64_t TOCOffset = 3 * PVT.getStoreSize(); - const int64_t BPOffset = 4 * PVT.getStoreSize(); + const int64_t TOCOffset = 3 * PVT.getStoreSize(); + const int64_t BPOffset = 4 * PVT.getStoreSize(); // Prepare IP either in reg. const TargetRegisterClass *PtrRC = getRegClassFor(PVT); @@ -12420,8 +12666,7 @@ BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1); - MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup)) - .addMBB(mainMBB); + MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup)).addMBB(mainMBB); MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB); thisMBB->addSuccessor(mainMBB, BranchProbability::getZero()); @@ -12436,14 +12681,14 @@ // Store IP if (Subtarget.isPPC64()) { MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD)) - .addReg(LabelReg) - .addImm(LabelOffset) - .addReg(BufReg); + .addReg(LabelReg) + .addImm(LabelOffset) + .addReg(BufReg); } else { MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW)) - .addReg(LabelReg) - .addImm(LabelOffset) - .addReg(BufReg); + .addReg(LabelReg) + .addImm(LabelOffset) + .addReg(BufReg); } MIB.cloneMemRefs(MI); @@ -12451,10 +12696,11 @@ mainMBB->addSuccessor(sinkMBB); // sinkMBB: - BuildMI(*sinkMBB, sinkMBB->begin(), DL, - TII->get(PPC::PHI), DstReg) - .addReg(mainDstReg).addMBB(mainMBB) - .addReg(restoreDstReg).addMBB(thisMBB); + BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(PPC::PHI), DstReg) + .addReg(mainDstReg) + .addMBB(mainMBB) + .addReg(restoreDstReg) + .addMBB(thisMBB); MI.eraseFromParent(); return sinkMBB; @@ -12470,15 +12716,14 @@ MachineRegisterInfo &MRI = MF->getRegInfo(); MVT PVT = getPointerTy(MF->getDataLayout()); - assert((PVT == MVT::i64 || PVT == MVT::i32) && - "Invalid Pointer Size!"); + assert((PVT == MVT::i64 || PVT == MVT::i32) && "Invalid Pointer Size!"); const TargetRegisterClass *RC = - (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; + (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass; Register Tmp = MRI.createVirtualRegister(RC); // Since FP is only updated here but NOT referenced, it's treated as GPR. - unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31; - unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1; + unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31; + unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1; unsigned BP = (PVT == MVT::i64) ? PPC::X30 @@ -12488,9 +12733,9 @@ MachineInstrBuilder MIB; const int64_t LabelOffset = 1 * PVT.getStoreSize(); - const int64_t SPOffset = 2 * PVT.getStoreSize(); - const int64_t TOCOffset = 3 * PVT.getStoreSize(); - const int64_t BPOffset = 4 * PVT.getStoreSize(); + const int64_t SPOffset = 2 * PVT.getStoreSize(); + const int64_t TOCOffset = 3 * PVT.getStoreSize(); + const int64_t BPOffset = 4 * PVT.getStoreSize(); Register BufReg = MI.getOperand(0).getReg(); @@ -12498,49 +12743,46 @@ // frame pointer, and if so, then its r31 will be restored // as necessary). if (PVT == MVT::i64) { - MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP) - .addImm(0) - .addReg(BufReg); + MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP).addImm(0).addReg(BufReg); } else { - MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP) - .addImm(0) - .addReg(BufReg); + MIB = + BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP).addImm(0).addReg(BufReg); } MIB.cloneMemRefs(MI); // Reload IP if (PVT == MVT::i64) { MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp) - .addImm(LabelOffset) - .addReg(BufReg); + .addImm(LabelOffset) + .addReg(BufReg); } else { MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp) - .addImm(LabelOffset) - .addReg(BufReg); + .addImm(LabelOffset) + .addReg(BufReg); } MIB.cloneMemRefs(MI); // Reload SP if (PVT == MVT::i64) { MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP) - .addImm(SPOffset) - .addReg(BufReg); + .addImm(SPOffset) + .addReg(BufReg); } else { MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP) - .addImm(SPOffset) - .addReg(BufReg); + .addImm(SPOffset) + .addReg(BufReg); } MIB.cloneMemRefs(MI); // Reload BP if (PVT == MVT::i64) { MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP) - .addImm(BPOffset) - .addReg(BufReg); + .addImm(BPOffset) + .addReg(BufReg); } else { MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP) - .addImm(BPOffset) - .addReg(BufReg); + .addImm(BPOffset) + .addReg(BufReg); } MIB.cloneMemRefs(MI); @@ -12554,8 +12796,8 @@ } // Jump - BuildMI(*MBB, MI, DL, - TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp); + BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)) + .addReg(Tmp); BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR)); MI.eraseFromParent(); @@ -13427,10 +13669,10 @@ // If the target doesn't have DirectMove, we should use stack to do the // conversion, because the target doesn't have the instructions like mtvsrd // or mfvsrd to do this conversion directly. - auto copyRegFromG8RCOrF8RC = [&] (unsigned DestReg, unsigned SrcReg) { + auto copyRegFromG8RCOrF8RC = [&](unsigned DestReg, unsigned SrcReg) { if (Subtarget.hasDirectMove()) { BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), DestReg) - .addReg(SrcReg); + .addReg(SrcReg); } else { // Use stack to do the register copy. unsigned StoreOp = PPC::STD, LoadOp = PPC::LFD; @@ -13460,10 +13702,10 @@ // Store the SrcReg into the stack. BuildMI(*BB, MI, dl, TII->get(StoreOp)) - .addReg(SrcReg) - .addImm(0) - .addFrameIndex(FrameIdx) - .addMemOperand(MMOStore); + .addReg(SrcReg) + .addImm(0) + .addFrameIndex(FrameIdx) + .addMemOperand(MMOStore); MachineMemOperand *MMOLoad = F->getMachineMemOperand( MachinePointerInfo::getFixedStack(*F, FrameIdx, 0), @@ -13474,9 +13716,9 @@ // so we have done the RegClass conversion from RegClass::SrcReg to // RegClass::DestReg. BuildMI(*BB, MI, dl, TII->get(LoadOp), DestReg) - .addImm(0) - .addFrameIndex(FrameIdx) - .addMemOperand(MMOLoad); + .addImm(0) + .addFrameIndex(FrameIdx) + .addMemOperand(MMOLoad); } }; @@ -13507,16 +13749,16 @@ // IMPLICIT_DEF register. BuildMI(*BB, MI, dl, TII->get(TargetOpcode::IMPLICIT_DEF), ImDefReg); BuildMI(*BB, MI, dl, TII->get(PPC::INSERT_SUBREG), ExtSrcReg) - .addReg(ImDefReg) - .add(SrcOp) - .addImm(1); + .addReg(ImDefReg) + .add(SrcOp) + .addImm(1); Register NewFPSCRTmpReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); BuildMI(*BB, MI, dl, TII->get(PPC::RLDIMI), NewFPSCRTmpReg) - .addReg(OldFPSCRTmpReg) - .addReg(ExtSrcReg) - .addImm(0) - .addImm(62); + .addReg(OldFPSCRTmpReg) + .addReg(ExtSrcReg) + .addImm(0) + .addImm(62); Register NewFPSCRReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); copyRegFromG8RCOrF8RC(NewFPSCRReg, NewFPSCRTmpReg); @@ -13524,10 +13766,10 @@ // The mask 255 means that put the 32:63 bits of NewFPSCRReg to the 32:63 // bits of FPSCR. BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)) - .addImm(255) - .addReg(NewFPSCRReg) - .addImm(0) - .addImm(0); + .addImm(255) + .addReg(NewFPSCRReg) + .addImm(0) + .addImm(0); } else if (MI.getOpcode() == PPC::SETFLM) { DebugLoc Dl = MI.getDebugLoc(); @@ -13702,7 +13944,7 @@ // isConsecutiveLSLoc needs to work even if all adds have not yet been // collapsed, and so we need to look through chains of them. static void getBaseWithConstantOffset(SDValue Loc, SDValue &Base, - int64_t& Offset, SelectionDAG &DAG) { + int64_t &Offset, SelectionDAG &DAG) { if (DAG.isBaseWithConstantOffset(Loc)) { Base = Loc.getOperand(0); Offset += cast(Loc.getOperand(1))->getSExtValue(); @@ -13714,8 +13956,7 @@ } static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base, - unsigned Bytes, int Dist, - SelectionDAG &DAG) { + unsigned Bytes, int Dist, SelectionDAG &DAG) { if (VT.getSizeInBits() / 8 != Bytes) return false; @@ -13724,12 +13965,13 @@ if (BaseLoc.getOpcode() != ISD::FrameIndex) return false; const MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); - int FI = cast(Loc)->getIndex(); + int FI = cast(Loc)->getIndex(); int BFI = cast(BaseLoc)->getIndex(); - int FS = MFI.getObjectSize(FI); + int FS = MFI.getObjectSize(FI); int BFS = MFI.getObjectSize(BFI); - if (FS != BFS || FS != (int)Bytes) return false; - return MFI.getObjectOffset(FI) == (MFI.getObjectOffset(BFI) + Dist*Bytes); + if (FS != BFS || FS != (int)Bytes) + return false; + return MFI.getObjectOffset(FI) == (MFI.getObjectOffset(BFI) + Dist * Bytes); } SDValue Base1 = Loc, Base2 = BaseLoc; @@ -13747,15 +13989,14 @@ bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1); bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2); if (isGA1 && isGA2 && GV1 == GV2) - return Offset1 == (Offset2 + Dist*Bytes); + return Offset1 == (Offset2 + Dist * Bytes); return false; } // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does // not enforce equality of the chain operands. -static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base, - unsigned Bytes, int Dist, - SelectionDAG &DAG) { +static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base, unsigned Bytes, + int Dist, SelectionDAG &DAG) { if (LSBaseSDNode *LS = dyn_cast(N)) { EVT VT = LS->getMemoryVT(); SDValue Loc = LS->getBasePtr(); @@ -13765,7 +14006,8 @@ if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) { EVT VT; switch (cast(N->getOperand(1))->getZExtValue()) { - default: return false; + default: + return false; case Intrinsic::ppc_altivec_lvx: case Intrinsic::ppc_altivec_lvxl: case Intrinsic::ppc_vsx_lxvw4x: @@ -13793,7 +14035,8 @@ if (N->getOpcode() == ISD::INTRINSIC_VOID) { EVT VT; switch (cast(N->getOperand(1))->getZExtValue()) { - default: return false; + default: + return false; case Intrinsic::ppc_altivec_stvx: case Intrinsic::ppc_altivec_stvxl: case Intrinsic::ppc_vsx_stxvw4x: @@ -13849,7 +14092,7 @@ if (isConsecutiveLS(ChainST, St, StoreSize, 1, DAG)) { Other = dyn_cast(ChainST); return Other != nullptr && !ChainST->isPredecessorOf(St) && - !St->isPredecessorOf(ChainST); + !St->isPredecessorOf(ChainST); } if (!Visited.count(ChainST->getChain().getNode())) Queue.push_back(ChainST->getChain().getNode()); @@ -13871,7 +14114,8 @@ Queue.clear(); for (SmallSet::iterator I = StoreRoots.begin(), - IE = StoreRoots.end(); I != IE; ++I) { + IE = StoreRoots.end(); + I != IE; ++I) { Queue.push_back(*I); while (!Queue.empty()) { @@ -13883,14 +14127,16 @@ if (isConsecutiveLS(ChainST, St, StoreSize, 1, DAG)) { Other = dyn_cast(ChainST); return Other != nullptr && !ChainST->isPredecessorOf(St) && - !St->isPredecessorOf(ChainST); + !St->isPredecessorOf(ChainST); } } for (SDNode::use_iterator UI = StoreRoot->use_begin(), - UE = StoreRoot->use_end(); UI != UE; ++UI) + UE = StoreRoot->use_end(); + UI != UE; ++UI) if (((isa(*UI) && - cast(*UI)->getChain().getNode() == StoreRoot) || - UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI)) + cast(*UI)->getChain().getNode() == StoreRoot) || + UI->getOpcode() == ISD::TokenFactor) && + !Visited.count(*UI)) Queue.push_back(*UI); } } @@ -13945,7 +14191,8 @@ Queue.clear(); for (SmallSet::iterator I = LoadRoots.begin(), - IE = LoadRoots.end(); I != IE; ++I) { + IE = LoadRoots.end(); + I != IE; ++I) { Queue.push_back(*I); while (!Queue.empty()) { @@ -13971,10 +14218,10 @@ return false; } -/// This function is called when we have proved that a SETCC node can be replaced -/// by subtraction (and other supporting instructions) so that the result of -/// comparison is kept in a GPR instead of CR. This function is purely for -/// codegen purposes and has some flags to guide the codegen process. +/// This function is called when we have proved that a SETCC node can be +/// replaced by subtraction (and other supporting instructions) so that the +/// result of comparison is kept in a GPR instead of CR. This function is purely +/// for codegen purposes and has some flags to guide the codegen process. static SDValue generateEquivalentSub(SDNode *N, int Size, bool Complement, bool Swap, SDLoc &DL, SelectionDAG &DAG) { assert(N->getOpcode() == ISD::SETCC && "ISD::SETCC Expected."); @@ -14032,7 +14279,8 @@ if (OpSize < Size) { switch (CC) { - default: break; + default: + break; case ISD::SETULT: return generateEquivalentSub(N, Size, false, false, DL, DAG); case ISD::SETULE: @@ -14062,21 +14310,19 @@ // Note that trunc here can be an actual i1 trunc, or can be the effective // truncation that comes from a setcc or select_cc. - if (N->getOpcode() == ISD::TRUNCATE && - N->getValueType(0) != MVT::i1) + if (N->getOpcode() == ISD::TRUNCATE && N->getValueType(0) != MVT::i1) return SDValue(); if (N->getOperand(0).getValueType() != MVT::i32 && N->getOperand(0).getValueType() != MVT::i64) return SDValue(); - if (N->getOpcode() == ISD::SETCC || - N->getOpcode() == ISD::SELECT_CC) { + if (N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) { // If we're looking at a comparison, then we need to make sure that the // high bits (all except for the first) don't matter the result. - ISD::CondCode CC = - cast(N->getOperand( - N->getOpcode() == ISD::SETCC ? 2 : 4))->get(); + ISD::CondCode CC = cast( + N->getOperand(N->getOpcode() == ISD::SETCC ? 2 : 4)) + ->get(); unsigned OpBits = N->getOperand(0).getValueSizeInBits(); if (ISD::isSignedIntSetCC(CC)) { @@ -14085,9 +14331,9 @@ return SDValue(); } else if (ISD::isUnsignedIntSetCC(CC)) { if (!DAG.MaskedValueIsZero(N->getOperand(0), - APInt::getHighBitsSet(OpBits, OpBits-1)) || + APInt::getHighBitsSet(OpBits, OpBits - 1)) || !DAG.MaskedValueIsZero(N->getOperand(1), - APInt::getHighBitsSet(OpBits, OpBits-1))) + APInt::getHighBitsSet(OpBits, OpBits - 1))) return (N->getOpcode() == ISD::SETCC ? ConvertSETCCToSubtract(N, DCI) : SDValue()); } else { @@ -14099,8 +14345,10 @@ // We don't really care about what is known about the first bit (if // anything), so pretend that it is known zero for both to ensure they can // be compared as constants. - Op1Known.Zero.setBit(0); Op1Known.One.clearBit(0); - Op2Known.Zero.setBit(0); Op2Known.One.clearBit(0); + Op1Known.Zero.setBit(0); + Op1Known.One.clearBit(0); + Op2Known.Zero.setBit(0); + Op2Known.One.clearBit(0); if (!Op1Known.isConstant() || !Op2Known.isConstant() || Op1Known.getConstant() != Op2Known.getConstant()) @@ -14112,7 +14360,7 @@ // make sure that all of the intermediate operations are bit operations, and // all inputs are extensions. if (N->getOperand(0).getOpcode() != ISD::AND && - N->getOperand(0).getOpcode() != ISD::OR && + N->getOperand(0).getOpcode() != ISD::OR && N->getOperand(0).getOpcode() != ISD::XOR && N->getOperand(0).getOpcode() != ISD::SELECT && N->getOperand(0).getOpcode() != ISD::SELECT_CC && @@ -14124,7 +14372,7 @@ if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) && N->getOperand(1).getOpcode() != ISD::AND && - N->getOperand(1).getOpcode() != ISD::OR && + N->getOperand(1).getOpcode() != ISD::OR && N->getOperand(1).getOpcode() != ISD::XOR && N->getOperand(1).getOpcode() != ISD::SELECT && N->getOperand(1).getOpcode() != ISD::SELECT_CC && @@ -14142,7 +14390,7 @@ if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND || N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND || N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) && - N->getOperand(i).getOperand(0).getValueType() == MVT::i1) || + N->getOperand(i).getOperand(0).getValueType() == MVT::i1) || isa(N->getOperand(i))) Inputs.push_back(N->getOperand(i)); else @@ -14176,7 +14424,7 @@ isa(BinOp.getOperand(i))) { Inputs.push_back(BinOp.getOperand(i)); } else if (BinOp.getOperand(i).getOpcode() == ISD::AND || - BinOp.getOperand(i).getOpcode() == ISD::OR || + BinOp.getOperand(i).getOpcode() == ISD::OR || BinOp.getOperand(i).getOpcode() == ISD::XOR || BinOp.getOperand(i).getOpcode() == ISD::SELECT || BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC || @@ -14285,15 +14533,21 @@ unsigned C; switch (PromOp.getOpcode()) { - default: C = 0; break; - case ISD::SELECT: C = 1; break; - case ISD::SELECT_CC: C = 2; break; + default: + C = 0; + break; + case ISD::SELECT: + C = 1; + break; + case ISD::SELECT_CC: + C = 2; + break; } if ((!isa(PromOp.getOperand(C)) && PromOp.getOperand(C).getValueType() != MVT::i1) || - (!isa(PromOp.getOperand(C+1)) && - PromOp.getOperand(C+1).getValueType() != MVT::i1)) { + (!isa(PromOp.getOperand(C + 1)) && + PromOp.getOperand(C + 1).getValueType() != MVT::i1)) { // The to-be-promoted operands of this node have not yet been // promoted (this should be rare because we're going through the // list backward, but if one of the operands has several users in @@ -14307,11 +14561,11 @@ // If there are any constant inputs, make sure they're replaced now. for (unsigned i = 0; i < 2; ++i) - if (isa(Ops[C+i])) - Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]); + if (isa(Ops[C + i])) + Ops[C + i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C + i]); - DAG.ReplaceAllUsesOfValueWith(PromOp, - DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops)); + DAG.ReplaceAllUsesOfValueWith( + PromOp, DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops)); } // Now we're left with the initial truncation itself. @@ -14342,8 +14596,7 @@ // the return values of functions. Because it is so similar, it is handled // here as well. - if (N->getValueType(0) != MVT::i32 && - N->getValueType(0) != MVT::i64) + if (N->getValueType(0) != MVT::i32 && N->getValueType(0) != MVT::i64) return SDValue(); if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) || @@ -14351,7 +14604,7 @@ return SDValue(); if (N->getOperand(0).getOpcode() != ISD::AND && - N->getOperand(0).getOpcode() != ISD::OR && + N->getOperand(0).getOpcode() != ISD::OR && N->getOperand(0).getOpcode() != ISD::XOR && N->getOperand(0).getOpcode() != ISD::SELECT && N->getOperand(0).getOpcode() != ISD::SELECT_CC) @@ -14382,7 +14635,7 @@ isa(BinOp.getOperand(i))) { Inputs.push_back(BinOp.getOperand(i)); } else if (BinOp.getOperand(i).getOpcode() == ISD::AND || - BinOp.getOperand(i).getOpcode() == ISD::OR || + BinOp.getOperand(i).getOpcode() == ISD::OR || BinOp.getOperand(i).getOpcode() == ISD::XOR || BinOp.getOperand(i).getOpcode() == ISD::SELECT || BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) { @@ -14414,15 +14667,15 @@ // SELECT_CC, record them for truncation. if (User->getOpcode() == ISD::SELECT) { if (User->getOperand(0) == Inputs[i]) - SelectTruncOp[0].insert(std::make_pair(User, - User->getOperand(0).getValueType())); + SelectTruncOp[0].insert( + std::make_pair(User, User->getOperand(0).getValueType())); } else if (User->getOpcode() == ISD::SELECT_CC) { if (User->getOperand(0) == Inputs[i]) - SelectTruncOp[0].insert(std::make_pair(User, - User->getOperand(0).getValueType())); + SelectTruncOp[0].insert( + std::make_pair(User, User->getOperand(0).getValueType())); if (User->getOperand(1) == Inputs[i]) - SelectTruncOp[1].insert(std::make_pair(User, - User->getOperand(1).getValueType())); + SelectTruncOp[1].insert( + std::make_pair(User, User->getOperand(1).getValueType())); } } } @@ -14436,15 +14689,15 @@ // SELECT_CC, record them for truncation. if (User->getOpcode() == ISD::SELECT) { if (User->getOperand(0) == PromOps[i]) - SelectTruncOp[0].insert(std::make_pair(User, - User->getOperand(0).getValueType())); + SelectTruncOp[0].insert( + std::make_pair(User, User->getOperand(0).getValueType())); } else if (User->getOpcode() == ISD::SELECT_CC) { if (User->getOperand(0) == PromOps[i]) - SelectTruncOp[0].insert(std::make_pair(User, - User->getOperand(0).getValueType())); + SelectTruncOp[0].insert( + std::make_pair(User, User->getOperand(0).getValueType())); if (User->getOperand(1) == PromOps[i]) - SelectTruncOp[1].insert(std::make_pair(User, - User->getOperand(1).getValueType())); + SelectTruncOp[1].insert( + std::make_pair(User, User->getOperand(1).getValueType())); } } } @@ -14458,17 +14711,16 @@ if (isa(Inputs[i])) continue; - unsigned OpBits = - Inputs[i].getOperand(0).getValueSizeInBits(); + unsigned OpBits = Inputs[i].getOperand(0).getValueSizeInBits(); assert(PromBits < OpBits && "Truncation not to a smaller bit count?"); if ((N->getOpcode() == ISD::ZERO_EXTEND && - !DAG.MaskedValueIsZero(Inputs[i].getOperand(0), - APInt::getHighBitsSet(OpBits, - OpBits-PromBits))) || + !DAG.MaskedValueIsZero( + Inputs[i].getOperand(0), + APInt::getHighBitsSet(OpBits, OpBits - PromBits))) || (N->getOpcode() == ISD::SIGN_EXTEND && DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) < - (OpBits-(PromBits-1)))) { + (OpBits - (PromBits - 1)))) { ReallyNeedsExt = true; break; } @@ -14488,14 +14740,14 @@ if (Inputs[i].getValueType() == N->getValueType(0)) DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc); else if (N->getOpcode() == ISD::SIGN_EXTEND) - DAG.ReplaceAllUsesOfValueWith(Inputs[i], - DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0))); + DAG.ReplaceAllUsesOfValueWith( + Inputs[i], DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0))); else if (N->getOpcode() == ISD::ZERO_EXTEND) - DAG.ReplaceAllUsesOfValueWith(Inputs[i], - DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0))); + DAG.ReplaceAllUsesOfValueWith( + Inputs[i], DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0))); else - DAG.ReplaceAllUsesOfValueWith(Inputs[i], - DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0))); + DAG.ReplaceAllUsesOfValueWith( + Inputs[i], DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0))); } std::list PromOpHandles; @@ -14512,15 +14764,21 @@ unsigned C; switch (PromOp.getOpcode()) { - default: C = 0; break; - case ISD::SELECT: C = 1; break; - case ISD::SELECT_CC: C = 2; break; + default: + C = 0; + break; + case ISD::SELECT: + C = 1; + break; + case ISD::SELECT_CC: + C = 2; + break; } if ((!isa(PromOp.getOperand(C)) && PromOp.getOperand(C).getValueType() != N->getValueType(0)) || - (!isa(PromOp.getOperand(C+1)) && - PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) { + (!isa(PromOp.getOperand(C + 1)) && + PromOp.getOperand(C + 1).getValueType() != N->getValueType(0))) { // The to-be-promoted operands of this node have not yet been // promoted (this should be rare because we're going through the // list backward, but if one of the operands has several users in @@ -14547,17 +14805,17 @@ // If this node has constant inputs, then they'll need to be promoted here. for (unsigned i = 0; i < 2; ++i) { - if (!isa(Ops[C+i])) + if (!isa(Ops[C + i])) continue; - if (Ops[C+i].getValueType() == N->getValueType(0)) + if (Ops[C + i].getValueType() == N->getValueType(0)) continue; if (N->getOpcode() == ISD::SIGN_EXTEND) - Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0)); + Ops[C + i] = DAG.getSExtOrTrunc(Ops[C + i], dl, N->getValueType(0)); else if (N->getOpcode() == ISD::ZERO_EXTEND) - Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0)); + Ops[C + i] = DAG.getZExtOrTrunc(Ops[C + i], dl, N->getValueType(0)); else - Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0)); + Ops[C + i] = DAG.getAnyExtOrTrunc(Ops[C + i], dl, N->getValueType(0)); } // If we've promoted the comparison inputs of a SELECT or SELECT_CC, @@ -14572,8 +14830,8 @@ Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]); } - DAG.ReplaceAllUsesOfValueWith(PromOp, - DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops)); + DAG.ReplaceAllUsesOfValueWith( + PromOp, DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops)); } // Now we're left with the initial extension itself. @@ -14585,11 +14843,10 @@ if (N->getOpcode() == ISD::ZERO_EXTEND) return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0), DAG.getConstant(APInt::getLowBitsSet( - N->getValueSizeInBits(0), PromBits), + N->getValueSizeInBits(0), PromBits), dl, N->getValueType(0))); - assert(N->getOpcode() == ISD::SIGN_EXTEND && - "Invalid extension type"); + assert(N->getOpcode() == ISD::SIGN_EXTEND && "Invalid extension type"); EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0), DAG.getDataLayout()); SDValue ShiftCst = DAG.getConstant(N->getValueSizeInBits(0) - PromBits, dl, ShiftAmountTy); @@ -14599,10 +14856,8 @@ ShiftCst); } -SDValue PPCTargetLowering::combineSetCC(SDNode *N, - DAGCombinerInfo &DCI) const { - assert(N->getOpcode() == ISD::SETCC && - "Should be called with a SETCC node"); +SDValue PPCTargetLowering::combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const { + assert(N->getOpcode() == ISD::SETCC && "Should be called with a SETCC node"); ISD::CondCode CC = cast(N->getOperand(2))->get(); if (CC == ISD::SETNE || CC == ISD::SETEQ) { @@ -14634,7 +14889,7 @@ static bool isFPExtLoad(SDValue Op) { if (LoadSDNode *LD = dyn_cast(Op.getNode())) return LD->getExtensionType() == ISD::EXTLOAD && - Op.getValueType() == MVT::f64; + Op.getValueType() == MVT::f64; return false; } @@ -14645,9 +14900,8 @@ /// single floating to integer conversion of the vector. /// Namely (build_vector (fptosi $A), (fptosi $B), ...) /// becomes (fptosi (build_vector ($A, $B, ...))) -SDValue PPCTargetLowering:: -combineElementTruncationToVectorTruncation(SDNode *N, - DAGCombinerInfo &DCI) const { +SDValue PPCTargetLowering::combineElementTruncationToVectorTruncation( + SDNode *N, DAGCombinerInfo &DCI) const { assert(N->getOpcode() == ISD::BUILD_VECTOR && "Should be called with a BUILD_VECTOR node"); @@ -14661,13 +14915,11 @@ // This combine happens after legalization so the fp_to_[su]i nodes are // already converted to PPCSISD nodes. unsigned FirstConversion = FirstInput.getOperand(0).getOpcode(); - if (FirstConversion == PPCISD::FCTIDZ || - FirstConversion == PPCISD::FCTIDUZ || - FirstConversion == PPCISD::FCTIWZ || - FirstConversion == PPCISD::FCTIWUZ) { + if (FirstConversion == PPCISD::FCTIDZ || FirstConversion == PPCISD::FCTIDUZ || + FirstConversion == PPCISD::FCTIWZ || FirstConversion == PPCISD::FCTIWUZ) { bool IsSplat = true; - bool Is32Bit = FirstConversion == PPCISD::FCTIWZ || - FirstConversion == PPCISD::FCTIWUZ; + bool Is32Bit = + FirstConversion == PPCISD::FCTIWZ || FirstConversion == PPCISD::FCTIWUZ; EVT SrcVT = FirstInput.getOperand(0).getValueType(); SmallVector Ops; EVT TargetVT = N->getValueType(0); @@ -14703,9 +14955,9 @@ if (In.isUndef()) Ops.push_back(DAG.getUNDEF(SrcVT)); else { - SDValue Trunc = DAG.getNode(ISD::FP_ROUND, dl, - MVT::f32, In.getOperand(0), - DAG.getIntPtrConstant(1, dl)); + SDValue Trunc = + DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, In.getOperand(0), + DAG.getIntPtrConstant(1, dl)); Ops.push_back(Trunc); } } else @@ -14713,8 +14965,7 @@ } unsigned Opcode; - if (FirstConversion == PPCISD::FCTIDZ || - FirstConversion == PPCISD::FCTIWZ) + if (FirstConversion == PPCISD::FCTIDZ || FirstConversion == PPCISD::FCTIWZ) Opcode = ISD::FP_TO_SINT; else Opcode = ISD::FP_TO_UINT; @@ -14763,13 +15014,14 @@ if (IsRoundOfExtLoad && N->getOperand(i).getOpcode() != ISD::FP_ROUND) return SDValue(); - SDValue NextInput = IsRoundOfExtLoad ? N->getOperand(i).getOperand(0) : - N->getOperand(i); + SDValue NextInput = + IsRoundOfExtLoad ? N->getOperand(i).getOperand(0) : N->getOperand(i); if (NextInput.getOpcode() != ISD::LOAD) return SDValue(); - SDValue PreviousInput = - IsRoundOfExtLoad ? N->getOperand(i-1).getOperand(0) : N->getOperand(i-1); + SDValue PreviousInput = IsRoundOfExtLoad + ? N->getOperand(i - 1).getOperand(0) + : N->getOperand(i - 1); LoadSDNode *LD1 = dyn_cast(PreviousInput); LoadSDNode *LD2 = dyn_cast(NextInput); @@ -14791,10 +15043,10 @@ "The loads cannot be both consecutive and reverse consecutive."); SDValue FirstLoadOp = - IsRoundOfExtLoad ? FirstInput.getOperand(0) : FirstInput; + IsRoundOfExtLoad ? FirstInput.getOperand(0) : FirstInput; SDValue LastLoadOp = - IsRoundOfExtLoad ? N->getOperand(N->getNumOperands()-1).getOperand(0) : - N->getOperand(N->getNumOperands()-1); + IsRoundOfExtLoad ? N->getOperand(N->getNumOperands() - 1).getOperand(0) + : N->getOperand(N->getNumOperands() - 1); LoadSDNode *LD1 = dyn_cast(FirstLoadOp); LoadSDNode *LDL = dyn_cast(LastLoadOp); @@ -14981,9 +15233,8 @@ MemoryType == MVT::i32 || MemoryType == MVT::i64; // Ensure that the load from the narrow width is being zero extended to i128. - if (!ValidLDType || - (LD->getExtensionType() != ISD::ZEXTLOAD && - LD->getExtensionType() != ISD::EXTLOAD)) + if (!ValidLDType || (LD->getExtensionType() != ISD::ZEXTLOAD && + LD->getExtensionType() != ISD::EXTLOAD)) return SDValue(); SDValue LoadOps[] = { @@ -15057,8 +15308,8 @@ SDValue Ext1 = FirstInput.getOperand(0); SDValue Ext2 = N->getOperand(1).getOperand(0); - if(Ext1.getOpcode() != ISD::EXTRACT_VECTOR_ELT || - Ext2.getOpcode() != ISD::EXTRACT_VECTOR_ELT) + if (Ext1.getOpcode() != ISD::EXTRACT_VECTOR_ELT || + Ext2.getOpcode() != ISD::EXTRACT_VECTOR_ELT) return SDValue(); ConstantSDNode *Ext1Op = dyn_cast(Ext1.getOperand(1)); @@ -15080,10 +15331,11 @@ return SDValue(); SDValue SrcVec = Ext1.getOperand(0); - auto NodeType = (N->getOperand(1).getOpcode() == ISD::SINT_TO_FP) ? - PPCISD::SINT_VEC_TO_FP : PPCISD::UINT_VEC_TO_FP; - return DAG.getNode(NodeType, dl, MVT::v2f64, - SrcVec, DAG.getIntPtrConstant(SubvecIdx, dl)); + auto NodeType = (N->getOperand(1).getOpcode() == ISD::SINT_TO_FP) + ? PPCISD::SINT_VEC_TO_FP + : PPCISD::UINT_VEC_TO_FP; + return DAG.getNode(NodeType, dl, MVT::v2f64, SrcVec, + DAG.getIntPtrConstant(SubvecIdx, dl)); } SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N, @@ -15111,33 +15363,30 @@ SDValue FirstOperand(Op.getOperand(0)); bool SubWordLoad = FirstOperand.getOpcode() == ISD::LOAD && - (FirstOperand.getValueType() == MVT::i8 || - FirstOperand.getValueType() == MVT::i16); + (FirstOperand.getValueType() == MVT::i8 || + FirstOperand.getValueType() == MVT::i16); if (Subtarget.hasP9Vector() && Subtarget.hasP9Altivec() && SubWordLoad) { bool Signed = N->getOpcode() == ISD::SINT_TO_FP; bool DstDouble = Op.getValueType() == MVT::f64; - unsigned ConvOp = Signed ? - (DstDouble ? PPCISD::FCFID : PPCISD::FCFIDS) : - (DstDouble ? PPCISD::FCFIDU : PPCISD::FCFIDUS); - SDValue WidthConst = - DAG.getIntPtrConstant(FirstOperand.getValueType() == MVT::i8 ? 1 : 2, - dl, false); + unsigned ConvOp = Signed ? (DstDouble ? PPCISD::FCFID : PPCISD::FCFIDS) + : (DstDouble ? PPCISD::FCFIDU : PPCISD::FCFIDUS); + SDValue WidthConst = DAG.getIntPtrConstant( + FirstOperand.getValueType() == MVT::i8 ? 1 : 2, dl, false); LoadSDNode *LDN = cast(FirstOperand.getNode()); - SDValue Ops[] = { LDN->getChain(), LDN->getBasePtr(), WidthConst }; + SDValue Ops[] = {LDN->getChain(), LDN->getBasePtr(), WidthConst}; SDValue Ld = DAG.getMemIntrinsicNode(PPCISD::LXSIZX, dl, DAG.getVTList(MVT::f64, MVT::Other), Ops, MVT::i8, LDN->getMemOperand()); // For signed conversion, we need to sign-extend the value in the VSR if (Signed) { - SDValue ExtOps[] = { Ld, WidthConst }; + SDValue ExtOps[] = {Ld, WidthConst}; SDValue Ext = DAG.getNode(PPCISD::VEXTS, dl, MVT::f64, ExtOps); return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ext); } else return DAG.getNode(ConvOp, dl, DstDouble ? MVT::f64 : MVT::f32, Ld); } - // For i32 intermediate values, unfortunately, the conversion functions // leave the upper 32 bits of the value are undefined. Within the set of // scalar instructions, we have no method for zero- or sign-extending the @@ -15173,16 +15422,16 @@ return SDValue(); } - unsigned FCTOp = - Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ : - PPCISD::FCTIDUZ; + unsigned FCTOp = Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT + ? PPCISD::FCTIDZ + : PPCISD::FCTIDUZ; SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src); SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp); if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) { - FP = DAG.getNode(ISD::FP_ROUND, dl, - MVT::f32, FP, DAG.getIntPtrConstant(0, dl)); + FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, + DAG.getIntPtrConstant(0, dl)); DCI.AddToWorklist(FP.getNode()); } @@ -15235,7 +15484,7 @@ MVT VecTy = N->getValueType(0).getSimpleVT(); - SDValue LoadOps[] = { Chain, Base }; + SDValue LoadOps[] = {Chain, Base}; SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl, DAG.getVTList(MVT::v2f64, MVT::Other), LoadOps, MVT::v2f64, MMO); @@ -15314,10 +15563,9 @@ DAG.getVTList(MVT::v2f64, MVT::Other), Chain, Src); DCI.AddToWorklist(Swap.getNode()); Chain = Swap.getValue(1); - SDValue StoreOps[] = { Chain, Swap, Base }; - SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl, - DAG.getVTList(MVT::Other), - StoreOps, VecTy, MMO); + SDValue StoreOps[] = {Chain, Swap, Base}; + SDValue Store = DAG.getMemIntrinsicNode( + PPCISD::STXVD2X, dl, DAG.getVTList(MVT::Other), StoreOps, VecTy, MMO); DCI.AddToWorklist(Store.getNode()); return Store; } @@ -15328,9 +15576,8 @@ return Op; } -bool -PPCTargetLowering::combine256BitVectorStores(StoreSDNode *ST, - DAGCombinerInfo &DCI) const { +bool PPCTargetLowering::combine256BitVectorStores(StoreSDNode *ST, + DAGCombinerInfo &DCI) const { assert(ST->getMemOperand()->getSizeInBits() == 128 && "Can only combine pairs of 128-bit vector stores."); @@ -15420,9 +15667,8 @@ return nullptr; } -bool -PPCTargetLowering::combine256BitVectorLoads(LoadSDNode *LD, - DAGCombinerInfo &DCI) const { +bool PPCTargetLowering::combine256BitVectorLoads(LoadSDNode *LD, + DAGCombinerInfo &DCI) const { EVT NarrowVT = LD->getValueType(0); assert(NarrowVT.is128BitVector() && "Can only combine pairs of 128-bit vector loads"); @@ -15509,8 +15755,8 @@ SDLoc dl(N); unsigned Opcode = N->getOperand(1).getOpcode(); - assert((Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT) - && "Not a FP_TO_INT Instruction!"); + assert((Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT) && + "Not a FP_TO_INT Instruction!"); SDValue Val = N->getOperand(1).getOperand(0); EVT Op1VT = N->getOperand(1).getValueType(); @@ -15521,8 +15767,8 @@ // Only perform combine for conversion to i64/i32 or power9 i16/i8. bool ValidTypeForStoreFltAsInt = - (Op1VT == MVT::i32 || Op1VT == MVT::i64 || - (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8))); + (Op1VT == MVT::i32 || Op1VT == MVT::i64 || + (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8))); if (ResVT == MVT::f128 && !Subtarget.hasP9Vector()) return SDValue(); @@ -15538,24 +15784,23 @@ } // Set signed or unsigned conversion opcode. - unsigned ConvOpcode = (Opcode == ISD::FP_TO_SINT) ? - PPCISD::FP_TO_SINT_IN_VSR : - PPCISD::FP_TO_UINT_IN_VSR; + unsigned ConvOpcode = (Opcode == ISD::FP_TO_SINT) ? PPCISD::FP_TO_SINT_IN_VSR + : PPCISD::FP_TO_UINT_IN_VSR; - Val = DAG.getNode(ConvOpcode, - dl, ResVT == MVT::f128 ? MVT::f128 : MVT::f64, Val); + Val = DAG.getNode(ConvOpcode, dl, ResVT == MVT::f128 ? MVT::f128 : MVT::f64, + Val); DCI.AddToWorklist(Val.getNode()); // Set number of bytes being converted. unsigned ByteSize = Op1VT.getScalarSizeInBits() / 8; - SDValue Ops[] = { N->getOperand(0), Val, N->getOperand(2), - DAG.getIntPtrConstant(ByteSize, dl, false), - DAG.getValueType(Op1VT) }; + SDValue Ops[] = {N->getOperand(0), Val, N->getOperand(2), + DAG.getIntPtrConstant(ByteSize, dl, false), + DAG.getValueType(Op1VT)}; Val = DAG.getMemIntrinsicNode(PPCISD::ST_VSR_SCAL_INT, dl, - DAG.getVTList(MVT::Other), Ops, - cast(N)->getMemoryVT(), - cast(N)->getMemOperand()); + DAG.getVTList(MVT::Other), Ops, + cast(N)->getMemoryVT(), + cast(N)->getMemOperand()); DCI.AddToWorklist(Val.getNode()); return Val; @@ -15851,7 +16096,7 @@ LSBaseSDNode *LSBase, DAGCombinerInfo &DCI) const { assert((ISD::isNormalLoad(LSBase) || ISD::isNormalStore(LSBase)) && - "Not a reverse memop pattern!"); + "Not a reverse memop pattern!"); auto IsElementReverse = [](const ShuffleVectorSDNode *SVN) -> bool { auto Mask = SVN->getMask(); @@ -15879,7 +16124,7 @@ if (!Subtarget.hasP9Vector()) return SDValue(); - if(!IsElementReverse(SVN)) + if (!IsElementReverse(SVN)) return SDValue(); if (LSBase->getOpcode() == ISD::LOAD) { @@ -15921,7 +16166,8 @@ SelectionDAG &DAG = DCI.DAG; SDLoc dl(N); switch (N->getOpcode()) { - default: break; + default: + break; case ISD::ADD: return combineADD(N, DCI); case ISD::SHL: @@ -15937,11 +16183,11 @@ return combineFMALike(N, DCI); case PPCISD::SHL: if (isNullConstant(N->getOperand(0))) // 0 << V -> 0. - return N->getOperand(0); + return N->getOperand(0); break; case PPCISD::SRL: if (isNullConstant(N->getOperand(0))) // 0 >>u V -> 0. - return N->getOperand(0); + return N->getOperand(0); break; case PPCISD::SRA: if (ConstantSDNode *C = dyn_cast(N->getOperand(0))) { @@ -15995,14 +16241,14 @@ unsigned Opcode = N->getOperand(1).getOpcode(); if (Opcode == ISD::FP_TO_SINT || Opcode == ISD::FP_TO_UINT) { - SDValue Val= combineStoreFPToInt(N, DCI); + SDValue Val = combineStoreFPToInt(N, DCI); if (Val) return Val; } if (Opcode == ISD::VECTOR_SHUFFLE && ISD::isNormalStore(N)) { ShuffleVectorSDNode *SVN = cast(N->getOperand(1)); - SDValue Val= combineVReverseMemOP(SVN, cast(N), DCI); + SDValue Val = combineVReverseMemOP(SVN, cast(N), DCI); if (Val) return Val; } @@ -16035,13 +16281,12 @@ BSwapOp = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BSwapOp); } - SDValue Ops[] = { - N->getOperand(0), BSwapOp, N->getOperand(2), DAG.getValueType(mVT) - }; - return - DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other), - Ops, cast(N)->getMemoryVT(), - cast(N)->getMemOperand()); + SDValue Ops[] = {N->getOperand(0), BSwapOp, N->getOperand(2), + DAG.getValueType(mVT)}; + return DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, + DAG.getVTList(MVT::Other), Ops, + cast(N)->getMemoryVT(), + cast(N)->getMemOperand()); } // STORE Constant:i32<0> -> STORE Constant:i64<0> @@ -16050,8 +16295,8 @@ isa(N->getOperand(1)) && Op1VT == MVT::i32) { // Need to sign-extended to 64-bits to handle negative values. EVT MemVT = cast(N)->getMemoryVT(); - uint64_t Val64 = SignExtend64(N->getConstantOperandVal(1), - MemVT.getSizeInBits()); + uint64_t Val64 = + SignExtend64(N->getConstantOperandVal(1), MemVT.getSizeInBits()); SDValue Const64 = DAG.getConstant(Val64, dl, MVT::i64); // DAG.getTruncStore() can't be used here because it doesn't accept @@ -16098,14 +16343,13 @@ // std::complex, and other similar structures, because of the way we // canonicalize structure copies. However, if we lack direct moves, // then the final bitcasts from the extracted integer values to the - // floating-point numbers turn into store/load pairs. Even with direct moves, - // just loading the two floating-point numbers is likely better. + // floating-point numbers turn into store/load pairs. Even with direct + // moves, just loading the two floating-point numbers is likely better. auto ReplaceTwoFloatLoad = [&]() { if (VT != MVT::i64) return false; - if (LD->getExtensionType() != ISD::NON_EXTLOAD || - LD->isVolatile()) + if (LD->getExtensionType() != ISD::NON_EXTLOAD || LD->isVolatile()) return false; // We're looking for a sequence like this: @@ -16120,16 +16364,17 @@ return false; auto UI = LD->use_begin(); - while (UI.getUse().getResNo() != 0) ++UI; + while (UI.getUse().getResNo() != 0) + ++UI; SDNode *Trunc = *UI++; - while (UI.getUse().getResNo() != 0) ++UI; + while (UI.getUse().getResNo() != 0) + ++UI; SDNode *RightShift = *UI; if (Trunc->getOpcode() != ISD::TRUNCATE) std::swap(Trunc, RightShift); if (Trunc->getOpcode() != ISD::TRUNCATE || - Trunc->getValueType(0) != MVT::i32 || - !Trunc->hasOneUse()) + Trunc->getValueType(0) != MVT::i32 || !Trunc->hasOneUse()) return false; if (RightShift->getOpcode() != ISD::SRL || !isa(RightShift->getOperand(1)) || @@ -16139,8 +16384,7 @@ SDNode *Trunc2 = *RightShift->use_begin(); if (Trunc2->getOpcode() != ISD::TRUNCATE || - Trunc2->getValueType(0) != MVT::i32 || - !Trunc2->hasOneUse()) + Trunc2->getValueType(0) != MVT::i32 || !Trunc2->hasOneUse()) return false; SDNode *Bitcast = *Trunc->use_begin(); @@ -16163,9 +16407,8 @@ if (LD->isIndexed()) { assert(LD->getAddressingMode() == ISD::PRE_INC && "Non-pre-inc AM on PPC?"); - BasePtr = - DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, - LD->getOffset()); + BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, + LD->getOffset()); } auto MMOFlags = @@ -16173,9 +16416,8 @@ SDValue FloatLoad = DAG.getLoad(MVT::f32, dl, LD->getChain(), BasePtr, LD->getPointerInfo(), LD->getAlign(), MMOFlags, LD->getAAInfo()); - SDValue AddPtr = - DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), - BasePtr, DAG.getIntPtrConstant(4, dl)); + SDValue AddPtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), + BasePtr, DAG.getIntPtrConstant(4, dl)); SDValue FloatLoad2 = DAG.getLoad( MVT::f32, dl, SDValue(FloatLoad.getNode(), 1), AddPtr, LD->getPointerInfo().getWithOffset(4), @@ -16255,19 +16497,17 @@ // reading up to (sizeof(vector)-1) bytes below the address of the // original unaligned load. MachineFunction &MF = DAG.getMachineFunction(); - MachineMemOperand *BaseMMO = - MF.getMachineMemOperand(LD->getMemOperand(), - -(long)MemVT.getStoreSize()+1, - 2*MemVT.getStoreSize()-1); + MachineMemOperand *BaseMMO = MF.getMachineMemOperand( + LD->getMemOperand(), -(long)MemVT.getStoreSize() + 1, + 2 * MemVT.getStoreSize() - 1); // Create the new base load. SDValue LDXIntID = DAG.getTargetConstant(IntrLD, dl, getPointerTy(MF.getDataLayout())); - SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr }; - SDValue BaseLoad = - DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl, - DAG.getVTList(PermTy, MVT::Other), - BaseLoadOps, LDTy, BaseMMO); + SDValue BaseLoadOps[] = {Chain, LDXIntID, Ptr}; + SDValue BaseLoad = DAG.getMemIntrinsicNode( + ISD::INTRINSIC_W_CHAIN, dl, DAG.getVTList(PermTy, MVT::Other), + BaseLoadOps, LDTy, BaseMMO); // Note that the value of IncOffset (which is provided to the next // load's pointer info offset value, and thus used to calculate the @@ -16291,17 +16531,15 @@ DAG.getConstant(IncValue, dl, getPointerTy(MF.getDataLayout())); Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); - MachineMemOperand *ExtraMMO = - MF.getMachineMemOperand(LD->getMemOperand(), - 1, 2*MemVT.getStoreSize()-1); - SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr }; - SDValue ExtraLoad = - DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl, - DAG.getVTList(PermTy, MVT::Other), - ExtraLoadOps, LDTy, ExtraMMO); + MachineMemOperand *ExtraMMO = MF.getMachineMemOperand( + LD->getMemOperand(), 1, 2 * MemVT.getStoreSize() - 1); + SDValue ExtraLoadOps[] = {Chain, LDXIntID, Ptr}; + SDValue ExtraLoad = DAG.getMemIntrinsicNode( + ISD::INTRINSIC_W_CHAIN, dl, DAG.getVTList(PermTy, MVT::Other), + ExtraLoadOps, LDTy, ExtraMMO); SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, - BaseLoad.getValue(1), ExtraLoad.getValue(1)); + BaseLoad.getValue(1), ExtraLoad.getValue(1)); // Because vperm has a big-endian bias, we must reverse the order // of the input vectors and complement the permute control vector @@ -16310,110 +16548,109 @@ // and ExtraLoad here. SDValue Perm; if (isLittleEndian) - Perm = BuildIntrinsicOp(IntrPerm, - ExtraLoad, BaseLoad, PermCntl, DAG, dl); + Perm = + BuildIntrinsicOp(IntrPerm, ExtraLoad, BaseLoad, PermCntl, DAG, dl); else - Perm = BuildIntrinsicOp(IntrPerm, - BaseLoad, ExtraLoad, PermCntl, DAG, dl); + Perm = + BuildIntrinsicOp(IntrPerm, BaseLoad, ExtraLoad, PermCntl, DAG, dl); if (VT != PermTy) Perm = Subtarget.hasAltivec() ? DAG.getNode(ISD::BITCAST, dl, VT, Perm) : DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, DAG.getTargetConstant(1, dl, MVT::i64)); - // second argument is 1 because this rounding - // is always exact. + // second argument is 1 because this rounding + // is always exact. // The output of the permutation is our loaded result, the TokenFactor is // our new chain. DCI.CombineTo(N, Perm, TF); return SDValue(N, 0); } - } - break; - case ISD::INTRINSIC_WO_CHAIN: { - bool isLittleEndian = Subtarget.isLittleEndian(); - unsigned IID = cast(N->getOperand(0))->getZExtValue(); - Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr - : Intrinsic::ppc_altivec_lvsl); - if (IID == Intr && N->getOperand(1)->getOpcode() == ISD::ADD) { - SDValue Add = N->getOperand(1); - - int Bits = 4 /* 16 byte alignment */; - - if (DAG.MaskedValueIsZero(Add->getOperand(1), - APInt::getAllOnes(Bits /* alignment */) - .zext(Add.getScalarValueSizeInBits()))) { - SDNode *BasePtr = Add->getOperand(0).getNode(); - for (SDNode *U : BasePtr->uses()) { - if (U->getOpcode() == ISD::INTRINSIC_WO_CHAIN && - cast(U->getOperand(0))->getZExtValue() == IID) { - // We've found another LVSL/LVSR, and this address is an aligned - // multiple of that one. The results will be the same, so use the - // one we've just found instead. - - return SDValue(U, 0); - } + } break; + case ISD::INTRINSIC_WO_CHAIN: { + bool isLittleEndian = Subtarget.isLittleEndian(); + unsigned IID = cast(N->getOperand(0))->getZExtValue(); + Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr + : Intrinsic::ppc_altivec_lvsl); + if (IID == Intr && N->getOperand(1)->getOpcode() == ISD::ADD) { + SDValue Add = N->getOperand(1); + + int Bits = 4 /* 16 byte alignment */; + + if (DAG.MaskedValueIsZero(Add->getOperand(1), + APInt::getAllOnes(Bits /* alignment */) + .zext(Add.getScalarValueSizeInBits()))) { + SDNode *BasePtr = Add->getOperand(0).getNode(); + for (SDNode *U : BasePtr->uses()) { + if (U->getOpcode() == ISD::INTRINSIC_WO_CHAIN && + cast(U->getOperand(0))->getZExtValue() == IID) { + // We've found another LVSL/LVSR, and this address is an aligned + // multiple of that one. The results will be the same, so use the + // one we've just found instead. + + return SDValue(U, 0); } } + } - if (isa(Add->getOperand(1))) { - SDNode *BasePtr = Add->getOperand(0).getNode(); - for (SDNode *U : BasePtr->uses()) { - if (U->getOpcode() == ISD::ADD && - isa(U->getOperand(1)) && - (cast(Add->getOperand(1))->getZExtValue() - - cast(U->getOperand(1))->getZExtValue()) % - (1ULL << Bits) == - 0) { - SDNode *OtherAdd = U; - for (SDNode *V : OtherAdd->uses()) { - if (V->getOpcode() == ISD::INTRINSIC_WO_CHAIN && - cast(V->getOperand(0))->getZExtValue() == - IID) { - return SDValue(V, 0); - } + if (isa(Add->getOperand(1))) { + SDNode *BasePtr = Add->getOperand(0).getNode(); + for (SDNode *U : BasePtr->uses()) { + if (U->getOpcode() == ISD::ADD && + isa(U->getOperand(1)) && + (cast(Add->getOperand(1))->getZExtValue() - + cast(U->getOperand(1))->getZExtValue()) % + (1ULL << Bits) == + 0) { + SDNode *OtherAdd = U; + for (SDNode *V : OtherAdd->uses()) { + if (V->getOpcode() == ISD::INTRINSIC_WO_CHAIN && + cast(V->getOperand(0))->getZExtValue() == + IID) { + return SDValue(V, 0); } } } } } + } - // Combine vmaxsw/h/b(a, a's negation) to abs(a) - // Expose the vabsduw/h/b opportunity for down stream - if (!DCI.isAfterLegalizeDAG() && Subtarget.hasP9Altivec() && - (IID == Intrinsic::ppc_altivec_vmaxsw || - IID == Intrinsic::ppc_altivec_vmaxsh || - IID == Intrinsic::ppc_altivec_vmaxsb)) { - SDValue V1 = N->getOperand(1); - SDValue V2 = N->getOperand(2); - if ((V1.getSimpleValueType() == MVT::v4i32 || - V1.getSimpleValueType() == MVT::v8i16 || - V1.getSimpleValueType() == MVT::v16i8) && - V1.getSimpleValueType() == V2.getSimpleValueType()) { - // (0-a, a) - if (V1.getOpcode() == ISD::SUB && - ISD::isBuildVectorAllZeros(V1.getOperand(0).getNode()) && - V1.getOperand(1) == V2) { - return DAG.getNode(ISD::ABS, dl, V2.getValueType(), V2); - } - // (a, 0-a) - if (V2.getOpcode() == ISD::SUB && - ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()) && - V2.getOperand(1) == V1) { - return DAG.getNode(ISD::ABS, dl, V1.getValueType(), V1); - } - // (x-y, y-x) - if (V1.getOpcode() == ISD::SUB && V2.getOpcode() == ISD::SUB && - V1.getOperand(0) == V2.getOperand(1) && - V1.getOperand(1) == V2.getOperand(0)) { - return DAG.getNode(ISD::ABS, dl, V1.getValueType(), V1); - } + // Combine vmaxsw/h/b(a, a's negation) to abs(a) + // Expose the vabsduw/h/b opportunity for down stream + if (!DCI.isAfterLegalizeDAG() && Subtarget.hasP9Altivec() && + (IID == Intrinsic::ppc_altivec_vmaxsw || + IID == Intrinsic::ppc_altivec_vmaxsh || + IID == Intrinsic::ppc_altivec_vmaxsb)) { + SDValue V1 = N->getOperand(1); + SDValue V2 = N->getOperand(2); + if ((V1.getSimpleValueType() == MVT::v4i32 || + V1.getSimpleValueType() == MVT::v8i16 || + V1.getSimpleValueType() == MVT::v16i8) && + V1.getSimpleValueType() == V2.getSimpleValueType()) { + // (0-a, a) + if (V1.getOpcode() == ISD::SUB && + ISD::isBuildVectorAllZeros(V1.getOperand(0).getNode()) && + V1.getOperand(1) == V2) { + return DAG.getNode(ISD::ABS, dl, V2.getValueType(), V2); + } + // (a, 0-a) + if (V2.getOpcode() == ISD::SUB && + ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()) && + V2.getOperand(1) == V1) { + return DAG.getNode(ISD::ABS, dl, V1.getValueType(), V1); + } + // (x-y, y-x) + if (V1.getOpcode() == ISD::SUB && V2.getOpcode() == ISD::SUB && + V1.getOperand(0) == V2.getOperand(1) && + V1.getOperand(1) == V2.getOperand(0)) { + return DAG.getNode(ISD::ABS, dl, V1.getValueType(), V1); } } } + } - break; + break; case ISD::INTRINSIC_W_CHAIN: // For little endian, VSX loads require generating lxvd2x/xxswapd. // Not needed on ISA 3.0 based CPUs since we have a non-permuting load. @@ -16455,15 +16692,15 @@ LoadSDNode *LD = cast(Load); // Create the byte-swapping load. SDValue Ops[] = { - LD->getChain(), // Chain - LD->getBasePtr(), // Ptr - DAG.getValueType(N->getValueType(0)) // VT + LD->getChain(), // Chain + LD->getBasePtr(), // Ptr + DAG.getValueType(N->getValueType(0)) // VT }; - SDValue BSLoad = - DAG.getMemIntrinsicNode(PPCISD::LBRX, dl, - DAG.getVTList(N->getValueType(0) == MVT::i64 ? - MVT::i64 : MVT::i32, MVT::Other), - Ops, LD->getMemoryVT(), LD->getMemOperand()); + SDValue BSLoad = DAG.getMemIntrinsicNode( + PPCISD::LBRX, dl, + DAG.getVTList(N->getValueType(0) == MVT::i64 ? MVT::i64 : MVT::i32, + MVT::Other), + Ops, LD->getMemoryVT(), LD->getMemOperand()); // If this is an i16 load, insert the truncate. SDValue ResVal = BSLoad; @@ -16517,8 +16754,7 @@ // node, use its result instead of this node (VCMP_rec computes both a CR6 // and a normal output). // - if (!N->getOperand(0).hasOneUse() && - !N->getOperand(1).hasOneUse() && + if (!N->getOperand(0).hasOneUse() && !N->getOperand(1).hasOneUse() && !N->getOperand(2).hasOneUse()) { // Scan all of the users of the LHS, looking for VCMP_rec's that match. @@ -16568,7 +16804,7 @@ if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN && cast(Cond.getOperand(1))->getZExtValue() == - Intrinsic::loop_decrement) { + Intrinsic::loop_decrement) { // We now need to make the intrinsic dead (it cannot be instruction // selected). @@ -16576,11 +16812,10 @@ assert(Cond.getNode()->hasOneUse() && "Counter decrement has more than one use"); - return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other, - N->getOperand(0), Target); + return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other, N->getOperand(0), + Target); } - } - break; + } break; case ISD::BR_CC: { // If this is a branch on an altivec predicate comparison, lower this so // that we don't have to do a MFOCRF: instead, branch directly on CR6. This @@ -16594,21 +16829,20 @@ if (LHS.getOpcode() == ISD::AND && LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN && cast(LHS.getOperand(0).getOperand(1))->getZExtValue() == - Intrinsic::loop_decrement && + Intrinsic::loop_decrement && isa(LHS.getOperand(1)) && !isNullConstant(LHS.getOperand(1))) LHS = LHS.getOperand(0); if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN && cast(LHS.getOperand(1))->getZExtValue() == - Intrinsic::loop_decrement && + Intrinsic::loop_decrement && isa(RHS)) { assert((CC == ISD::SETEQ || CC == ISD::SETNE) && "Counter decrement comparison is not EQ or NE"); unsigned Val = cast(RHS)->getZExtValue(); - bool isBDNZ = (CC == ISD::SETEQ && Val) || - (CC == ISD::SETNE && !Val); + bool isBDNZ = (CC == ISD::SETEQ && Val) || (CC == ISD::SETNE && !Val); // We now need to make the intrinsic dead (it cannot be instruction // selected). @@ -16632,46 +16866,44 @@ // that the condition is never/always true. unsigned Val = cast(RHS)->getZExtValue(); if (Val != 0 && Val != 1) { - if (CC == ISD::SETEQ) // Cond never true, remove branch. + if (CC == ISD::SETEQ) // Cond never true, remove branch. return N->getOperand(0); // Always !=, turn it into an unconditional branch. - return DAG.getNode(ISD::BR, dl, MVT::Other, - N->getOperand(0), N->getOperand(4)); + return DAG.getNode(ISD::BR, dl, MVT::Other, N->getOperand(0), + N->getOperand(4)); } bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); // Create the PPCISD altivec 'dot' comparison node. - SDValue Ops[] = { - LHS.getOperand(2), // LHS of compare - LHS.getOperand(3), // RHS of compare - DAG.getConstant(CompareOpc, dl, MVT::i32) - }; - EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue }; + SDValue Ops[] = {LHS.getOperand(2), // LHS of compare + LHS.getOperand(3), // RHS of compare + DAG.getConstant(CompareOpc, dl, MVT::i32)}; + EVT VTs[] = {LHS.getOperand(2).getValueType(), MVT::Glue}; SDValue CompNode = DAG.getNode(PPCISD::VCMP_rec, dl, VTs, Ops); // Unpack the result based on how the target uses it. PPC::Predicate CompOpc; switch (cast(LHS.getOperand(1))->getZExtValue()) { - default: // Can't happen, don't crash on invalid number though. - case 0: // Branch on the value of the EQ bit of CR6. + default: // Can't happen, don't crash on invalid number though. + case 0: // Branch on the value of the EQ bit of CR6. CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE; break; - case 1: // Branch on the inverted value of the EQ bit of CR6. + case 1: // Branch on the inverted value of the EQ bit of CR6. CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ; break; - case 2: // Branch on the value of the LT bit of CR6. + case 2: // Branch on the value of the LT bit of CR6. CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE; break; - case 3: // Branch on the inverted value of the LT bit of CR6. + case 3: // Branch on the inverted value of the LT bit of CR6. CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT; break; } return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), DAG.getConstant(CompOpc, dl, MVT::i32), - DAG.getRegister(PPC::CR6, MVT::i32), - N->getOperand(4), CompNode.getValue(1)); + DAG.getRegister(PPC::CR6, MVT::i32), N->getOperand(4), + CompNode.getValue(1)); } break; } @@ -16727,7 +16959,8 @@ unsigned Depth) const { Known.resetAll(); switch (Op.getOpcode()) { - default: break; + default: + break; case PPCISD::LBRX: { // lhbrx is known to have the top bits cleared out. if (cast(Op.getOperand(2))->getVT() == MVT::i16) @@ -16736,7 +16969,8 @@ } case ISD::INTRINSIC_WO_CHAIN: { switch (cast(Op.getOperand(0))->getZExtValue()) { - default: break; + default: + break; case Intrinsic::ppc_altivec_vcmpbfp_p: case Intrinsic::ppc_altivec_vcmpeqfp_p: case Intrinsic::ppc_altivec_vcmpequb_p: @@ -16756,7 +16990,7 @@ case Intrinsic::ppc_altivec_vcmpgtuw_p: case Intrinsic::ppc_altivec_vcmpgtud_p: case Intrinsic::ppc_altivec_vcmpgtuq_p: - Known.Zero = ~1U; // All bits but the low one are known to be zero. + Known.Zero = ~1U; // All bits but the low one are known to be zero. break; } break; @@ -16777,7 +17011,8 @@ Align PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const { switch (Subtarget.getCPUDirective()) { - default: break; + default: + break; case PPC::DIR_970: case PPC::DIR_PWR4: case PPC::DIR_PWR5: @@ -16829,7 +17064,8 @@ PPCTargetLowering::getConstraintType(StringRef Constraint) const { if (Constraint.size() == 1) { switch (Constraint[0]) { - default: break; + default: + break; case 'b': case 'r': case 'f': @@ -16848,9 +17084,8 @@ } } else if (Constraint == "wc") { // individual CR bits. return C_RegisterClass; - } else if (Constraint == "wa" || Constraint == "wd" || - Constraint == "wf" || Constraint == "ws" || - Constraint == "ww" || Constraint == "wi" || + } else if (Constraint == "wa" || Constraint == "wd" || Constraint == "wf" || + Constraint == "ws" || Constraint == "ww" || Constraint == "wi" || Constraint == "wm") { return C_RegisterClass; // VSX registers. } @@ -16865,8 +17100,8 @@ AsmOperandInfo &info, const char *constraint) const { ConstraintWeight weight = CW_Invalid; Value *CallOperandVal = info.CallOperandVal; - // If we don't have a value, we can't do a match, - // but allow it at the lowest weight. + // If we don't have a value, we can't do a match, + // but allow it at the lowest weight. if (!CallOperandVal) return CW_Default; Type *type = CallOperandVal->getType(); @@ -16874,8 +17109,7 @@ // Look at the constraint type. if (StringRef(constraint) == "wc" && type->isIntegerTy(1)) return CW_Register; // an individual CR bit. - else if ((StringRef(constraint) == "wa" || - StringRef(constraint) == "wd" || + else if ((StringRef(constraint) == "wa" || StringRef(constraint) == "wd" || StringRef(constraint) == "wf") && type->isVectorTy()) return CW_Register; @@ -16923,11 +17157,11 @@ if (Constraint.size() == 1) { // GCC RS6000 Constraint Letters switch (Constraint[0]) { - case 'b': // R1-R31 + case 'b': // R1-R31 if (VT == MVT::i64 && Subtarget.isPPC64()) return std::make_pair(0U, &PPC::G8RC_NOX0RegClass); return std::make_pair(0U, &PPC::GPRC_NOR0RegClass); - case 'r': // R0-R31 + case 'r': // R0-R31 if (VT == MVT::i64 && Subtarget.isPPC64()) return std::make_pair(0U, &PPC::G8RCRegClass); return std::make_pair(0U, &PPC::GPRCRegClass); @@ -16957,7 +17191,7 @@ // Scalars in Altivec registers only make sense with VSX. return std::make_pair(0U, &PPC::VFRCRegClass); break; - case 'y': // crrc + case 'y': // crrc return std::make_pair(0U, &PPC::CRRCRegClass); } } else if (Constraint == "wc" && Subtarget.useCRBits()) { @@ -17031,9 +17265,9 @@ // the AsmName field from *RegisterInfo.td, then this would not be necessary. if (R.first && VT == MVT::i64 && Subtarget.isPPC64() && PPC::GPRCRegClass.contains(R.first)) - return std::make_pair(TRI->getMatchingSuperReg(R.first, - PPC::sub_32, &PPC::G8RCRegClass), - &PPC::G8RCRegClass); + return std::make_pair( + TRI->getMatchingSuperReg(R.first, PPC::sub_32, &PPC::G8RCRegClass), + &PPC::G8RCRegClass); // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same. if (!R.second && StringRef("{cc}").equals_insensitive(Constraint)) { @@ -17057,16 +17291,18 @@ /// vector. If it is invalid, don't add anything to Ops. void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, - std::vector&Ops, + std::vector &Ops, SelectionDAG &DAG) const { SDValue Result; // Only support length 1 constraints. - if (Constraint.length() > 1) return; + if (Constraint.length() > 1) + return; char Letter = Constraint[0]; switch (Letter) { - default: break; + default: + break; case 'I': case 'J': case 'K': @@ -17076,42 +17312,44 @@ case 'O': case 'P': { ConstantSDNode *CST = dyn_cast(Op); - if (!CST) return; // Must be an immediate to match. + if (!CST) + return; // Must be an immediate to match. SDLoc dl(Op); int64_t Value = CST->getSExtValue(); EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative // numbers are printed as such. switch (Letter) { - default: llvm_unreachable("Unknown constraint letter!"); - case 'I': // "I" is a signed 16-bit constant. + default: + llvm_unreachable("Unknown constraint letter!"); + case 'I': // "I" is a signed 16-bit constant. if (isInt<16>(Value)) Result = DAG.getTargetConstant(Value, dl, TCVT); break; - case 'J': // "J" is a constant with only the high-order 16 bits nonzero. + case 'J': // "J" is a constant with only the high-order 16 bits nonzero. if (isShiftedUInt<16, 16>(Value)) Result = DAG.getTargetConstant(Value, dl, TCVT); break; - case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. + case 'L': // "L" is a signed 16-bit constant shifted left 16 bits. if (isShiftedInt<16, 16>(Value)) Result = DAG.getTargetConstant(Value, dl, TCVT); break; - case 'K': // "K" is a constant with only the low-order 16 bits nonzero. + case 'K': // "K" is a constant with only the low-order 16 bits nonzero. if (isUInt<16>(Value)) Result = DAG.getTargetConstant(Value, dl, TCVT); break; - case 'M': // "M" is a constant that is greater than 31. + case 'M': // "M" is a constant that is greater than 31. if (Value > 31) Result = DAG.getTargetConstant(Value, dl, TCVT); break; - case 'N': // "N" is a positive constant that is an exact power of two. + case 'N': // "N" is a positive constant that is an exact power of two. if (Value > 0 && isPowerOf2_64(Value)) Result = DAG.getTargetConstant(Value, dl, TCVT); break; - case 'O': // "O" is the constant zero. + case 'O': // "O" is the constant zero. if (Value == 0) Result = DAG.getTargetConstant(Value, dl, TCVT); break; - case 'P': // "P" is a constant whose negation is a signed 16-bit constant. + case 'P': // "P" is a constant whose negation is a signed 16-bit constant. if (isInt<16>(-Value)) Result = DAG.getTargetConstant(Value, dl, TCVT); break; @@ -17145,7 +17383,7 @@ return false; // PPC allows a sign-extended 16-bit immediate field. - if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) + if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16) - 1) return false; // No global is ever allowed as a base. @@ -17154,15 +17392,15 @@ // PPC only support r+r, switch (AM.Scale) { - case 0: // "r+i" or just "i", depending on HasBaseReg. + case 0: // "r+i" or just "i", depending on HasBaseReg. break; case 1: - if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. + if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. return false; // Otherwise we have r+r or r+i. break; case 2: - if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. + if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. return false; // Allow 2*r as r+r. break; @@ -17214,8 +17452,7 @@ MachinePointerInfo()); } -SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, - SelectionDAG &DAG) const { +SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { SDLoc dl(Op); unsigned Depth = cast(Op.getOperand(0))->getZExtValue(); @@ -17234,8 +17471,8 @@ else FrameReg = isPPC64 ? PPC::FP8 : PPC::FP; - SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, - PtrVT); + SDValue FrameAddr = + DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, PtrVT); while (Depth--) FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(), FrameAddr, MachinePointerInfo()); @@ -17244,7 +17481,7 @@ // FIXME? Maybe this could be a TableGen attribute on some registers and // this table could be generated automatically from RegInfo. -Register PPCTargetLowering::getRegisterByName(const char* RegName, LLT VT, +Register PPCTargetLowering::getRegisterByName(const char *RegName, LLT VT, const MachineFunction &MF) const { bool isPPC64 = Subtarget.isPPC64(); @@ -17289,8 +17526,8 @@ return false; } -bool -PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { +bool PPCTargetLowering::isOffsetFoldingLegal( + const GlobalAddressSDNode *GA) const { // The PowerPC target isn't yet aware of offsets. return false; } @@ -17366,8 +17603,8 @@ Info.opc = ISD::INTRINSIC_W_CHAIN; Info.memVT = VT; Info.ptrVal = I.getArgOperand(0); - Info.offset = -VT.getStoreSize()+1; - Info.size = 2*VT.getStoreSize()-1; + Info.offset = -VT.getStoreSize() + 1; + Info.size = 2 * VT.getStoreSize() - 1; Info.align = Align(1); Info.flags = MachineMemOperand::MOLoad; return true; @@ -17406,8 +17643,8 @@ Info.opc = ISD::INTRINSIC_VOID; Info.memVT = VT; Info.ptrVal = I.getArgOperand(1); - Info.offset = -VT.getStoreSize()+1; - Info.size = 2*VT.getStoreSize()-1; + Info.offset = -VT.getStoreSize() + 1; + Info.size = 2 * VT.getStoreSize() - 1; Info.align = Align(1); Info.flags = MachineMemOperand::MOStore; return true; @@ -17529,8 +17766,8 @@ if (Subtarget.pairedVectorMemops() && VT == MVT::v256i1) return true; if (Subtarget.hasVSX()) { - if (VT != MVT::v2f64 && VT != MVT::v2i64 && - VT != MVT::v4f32 && VT != MVT::v4i32) + if (VT != MVT::v2f64 && VT != MVT::v2i64 && VT != MVT::v4f32 && + VT != MVT::v4i32) return false; } else { return false; @@ -17660,15 +17897,12 @@ return true; } -const MCPhysReg * -PPCTargetLowering::getScratchRegisters(CallingConv::ID) const { +const MCPhysReg *PPCTargetLowering::getScratchRegisters(CallingConv::ID) const { // LR is a callee-save register, but we must treat it as clobbered by any call // site. Hence we include LR in the scratch registers, which are in turn added // as implicit-defs for stackmaps and patchpoints. The same reasoning applies // to CTR, which is used by any indirect call. - static const MCPhysReg ScratchRegs[] = { - PPC::X12, PPC::LR8, PPC::CTR8, 0 - }; + static const MCPhysReg ScratchRegs[] = {PPC::X12, PPC::LR8, PPC::CTR8, 0}; return ScratchRegs; } @@ -17683,9 +17917,8 @@ return Subtarget.isPPC64() ? PPC::X4 : PPC::R4; } -bool -PPCTargetLowering::shouldExpandBuildVectorWithShuffles( - EVT VT , unsigned DefinedValues) const { +bool PPCTargetLowering::shouldExpandBuildVectorWithShuffles( + EVT VT, unsigned DefinedValues) const { if (VT == MVT::v2i64) return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves @@ -17825,7 +18058,7 @@ if (!VT.isSimple() || !Subtarget.hasVSX()) return false; - switch(VT.getSimpleVT().SimpleTy) { + switch (VT.getSimpleVT().SimpleTy) { default: // For FP types that are currently not supported by PPC backend, return // false. Examples: f16, f80. @@ -17968,8 +18201,9 @@ auto *Constant = cast(Cmp.getOperand(1)); int64_t NegConstant = 0 - Constant->getSExtValue(); - switch(cast(Cmp.getOperand(2))->get()) { - default: break; + switch (cast(Cmp.getOperand(2))->get()) { + default: + break; case ISD::SETNE: { // when C == 0 // --> addze X, (addic Z, -1).carry @@ -17980,11 +18214,13 @@ SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Z, DAG.getConstant(NegConstant, DL, MVT::i64)); SDValue AddOrZ = NegConstant != 0 ? Add : Z; - SDValue Addc = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i64, MVT::Glue), - AddOrZ, DAG.getConstant(-1ULL, DL, MVT::i64)); - return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64), + SDValue Addc = + DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i64, MVT::Glue), AddOrZ, + DAG.getConstant(-1ULL, DL, MVT::i64)); + return DAG.getNode(ISD::ADDE, DL, VTs, LHS, + DAG.getConstant(0, DL, MVT::i64), SDValue(Addc.getNode(), 1)); - } + } case ISD::SETEQ: { // when C == 0 // --> addze X, (subfic Z, 0).carry @@ -17995,11 +18231,13 @@ SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Z, DAG.getConstant(NegConstant, DL, MVT::i64)); SDValue AddOrZ = NegConstant != 0 ? Add : Z; - SDValue Subc = DAG.getNode(ISD::SUBC, DL, DAG.getVTList(MVT::i64, MVT::Glue), - DAG.getConstant(0, DL, MVT::i64), AddOrZ); - return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64), + SDValue Subc = + DAG.getNode(ISD::SUBC, DL, DAG.getVTList(MVT::i64, MVT::Glue), + DAG.getConstant(0, DL, MVT::i64), AddOrZ); + return DAG.getNode(ISD::ADDE, DL, VTs, LHS, + DAG.getConstant(0, DL, MVT::i64), SDValue(Subc.getNode(), 1)); - } + } } return SDValue(); @@ -18028,7 +18266,7 @@ // Operand zero of PPCISD::MAT_PCREL_ADDR is the GA node. GlobalAddressSDNode *GSDN = dyn_cast(LHS.getOperand(0)); - ConstantSDNode* ConstNode = dyn_cast(RHS); + ConstantSDNode *ConstNode = dyn_cast(RHS); // Check that both casts succeeded. if (!GSDN || !ConstNode) @@ -18120,8 +18358,7 @@ } // BITCAST feeding a TRUNCATE possibly via SRL. - if (Op0.getOpcode() == ISD::BITCAST && - Op0.getValueType() == MVT::i128 && + if (Op0.getOpcode() == ISD::BITCAST && Op0.getValueType() == MVT::i128 && Op0.getOperand(0).getValueType() == MVT::f128) { SDValue Bitcast = DCI.DAG.getBitcast(MVT::v2i64, Op0.getOperand(0)); return DCI.DAG.getNode( @@ -18298,7 +18535,7 @@ const Function *Caller = CI->getParent()->getParent(); if (!areCallingConvEligibleForTCO_64SVR4(Caller->getCallingConv(), CI->getCallingConv())) - return false; + return false; // If the function is local then we have a good chance at tail-calling it return getTargetMachine().shouldAssumeDSOLocal(*Caller->getParent(), Callee); @@ -18309,12 +18546,12 @@ return false; if (Subtarget.hasP9Vector() && VT == MVT::f128) return true; - return VT == MVT::f32 || VT == MVT::f64 || - VT == MVT::v4f32 || VT == MVT::v2f64; + return VT == MVT::f32 || VT == MVT::f64 || VT == MVT::v4f32 || + VT == MVT::v2f64; } -bool PPCTargetLowering:: -isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const { +bool PPCTargetLowering::isMaskAndCmp0FoldingBeneficial( + const Instruction &AndI) const { const Value *Mask = AndI.getOperand(1); // If the mask is suitable for andi. or andis. we should sink the and. if (const ConstantInt *CI = dyn_cast(Mask)) { @@ -18323,7 +18560,7 @@ return false; int64_t ConstVal = CI->getZExtValue(); return isUInt<16>(ConstVal) || - (isUInt<16>(ConstVal >> 16) && !(ConstVal & 0xFFFF)); + (isUInt<16>(ConstVal >> 16) && !(ConstVal & 0xFFFF)); } // For non-constant masks, we can always use the record-form and. @@ -18474,7 +18711,8 @@ static void setAlignFlagsForFI(SDValue N, unsigned &FlagSet, SelectionDAG &DAG) { bool IsAdd = ((N.getOpcode() == ISD::ADD) || (N.getOpcode() == ISD::OR)); - FrameIndexSDNode *FI = dyn_cast(IsAdd ? N.getOperand(0) : N); + FrameIndexSDNode *FI = + dyn_cast(IsAdd ? N.getOperand(0) : N); if (!FI) return; const MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); @@ -18555,10 +18793,10 @@ static bool isPCRelNode(SDValue N) { return (N.getOpcode() == PPCISD::MAT_PCREL_ADDR || - isValidPCRelNode(N) || - isValidPCRelNode(N) || - isValidPCRelNode(N) || - isValidPCRelNode(N)); + isValidPCRelNode(N) || + isValidPCRelNode(N) || + isValidPCRelNode(N) || + isValidPCRelNode(N)); } /// computeMOFlags - Given a node N and it's Parent (a MemSDNode), compute diff --git a/llvm/test/CodeGen/PowerPC/kill-canary-intrinsic.ll b/llvm/test/CodeGen/PowerPC/kill-canary-intrinsic.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/kill-canary-intrinsic.ll @@ -0,0 +1,77 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \ +; RUN: --ppc-asm-full-reg-names < %s | FileCheck %s -check-prefix=AIX +; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux \ +; RUN: --ppc-asm-full-reg-names < %s | FileCheck %s -check-prefix=LINUX + +declare void @llvm.ppc.kill.canary() +define dso_local void @test_kill_canary() { +; AIX-LABEL: test_kill_canary: +; AIX: # %bb.0: # %entry +; AIX-NEXT: blr +; +; LINUX-LABEL: test_kill_canary: +; LINUX: # %bb.0: # %entry +; LINUX-NEXT: blr +entry: + call void @llvm.ppc.kill.canary() + ret void +} + +attributes #0 = { sspreq } +; Function Attrs: sspreq +define dso_local void @test_kill_canary_ssp() #0 { +; AIX-LABEL: test_kill_canary_ssp: +; AIX: # %bb.0: # %entry +; AIX-NEXT: mflr r0 +; AIX-NEXT: std r0, 16(r1) +; AIX-NEXT: stdu r1, -128(r1) +; AIX-NEXT: ld r3, L..C0(r2) # @__ssp_canary_word +; AIX-NEXT: ld r4, 0(r3) +; AIX-NEXT: std r4, 120(r1) +; AIX-NEXT: ld r4, 0(r3) +; AIX-NEXT: xori r4, r4, 65535 +; AIX-NEXT: xoris r4, r4, 65535 +; AIX-NEXT: std r4, 0(r3) +; AIX-NEXT: ld r3, 0(r3) +; AIX-NEXT: ld r4, 120(r1) +; AIX-NEXT: cmpld r3, r4 +; AIX-NEXT: bne cr0, L..BB1_2 +; AIX-NEXT: # %bb.1: # %entry +; AIX-NEXT: addi r1, r1, 128 +; AIX-NEXT: ld r0, 16(r1) +; AIX-NEXT: mtlr r0 +; AIX-NEXT: blr +; AIX-NEXT: L..BB1_2: # %entry +; AIX-NEXT: bl .__stack_chk_fail[PR] +; AIX-NEXT: nop +; +; LINUX-LABEL: test_kill_canary_ssp: +; LINUX: # %bb.0: # %entry +; LINUX-NEXT: mflr r0 +; LINUX-NEXT: std r0, 16(r1) +; LINUX-NEXT: stdu r1, -128(r1) +; LINUX-NEXT: .cfi_def_cfa_offset 128 +; LINUX-NEXT: .cfi_offset lr, 16 +; LINUX-NEXT: ld r3, -28688(r13) +; LINUX-NEXT: std r3, 120(r1) +; LINUX-NEXT: ld r3, -28688(r13) +; LINUX-NEXT: xori r3, r3, 65535 +; LINUX-NEXT: xoris r3, r3, 65535 +; LINUX-NEXT: std r3, 120(r1) +; LINUX-NEXT: ld r3, 120(r1) +; LINUX-NEXT: ld r4, -28688(r13) +; LINUX-NEXT: cmpld r4, r3 +; LINUX-NEXT: bne cr0, .LBB1_2 +; LINUX-NEXT: # %bb.1: # %entry +; LINUX-NEXT: addi r1, r1, 128 +; LINUX-NEXT: ld r0, 16(r1) +; LINUX-NEXT: mtlr r0 +; LINUX-NEXT: blr +; LINUX-NEXT: .LBB1_2: # %entry +; LINUX-NEXT: bl __stack_chk_fail +; LINUX-NEXT: nop +entry: + call void @llvm.ppc.kill.canary() + ret void +}